JPS6382945U - - Google Patents
Info
- Publication number
- JPS6382945U JPS6382945U JP1986176822U JP17682286U JPS6382945U JP S6382945 U JPS6382945 U JP S6382945U JP 1986176822 U JP1986176822 U JP 1986176822U JP 17682286 U JP17682286 U JP 17682286U JP S6382945 U JPS6382945 U JP S6382945U
- Authority
- JP
- Japan
- Prior art keywords
- resin
- covered
- semiconductor device
- utility
- scope
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims 2
- 229920005989 resin Polymers 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第1図aは本考案の第1の実施例を示す断面図
、第1図bは第1図aのA―A線の断面図、第2
図aは本考案の第2の実施例を示す断面図、第2
図bは第2図aのB―B線の断面図である。
1……樹脂A、2……樹脂B、3……外部端子
、4……ステム、5……チツプ、6……リードフ
レーム。
FIG. 1a is a cross-sectional view showing the first embodiment of the present invention, FIG. 1b is a cross-sectional view taken along line AA in FIG. 1a, and FIG.
Figure a is a sectional view showing a second embodiment of the present invention;
Figure b is a sectional view taken along line BB in Figure 2a. 1... Resin A, 2... Resin B, 3... External terminal, 4... Stem, 5... Chip, 6... Lead frame.
Claims (1)
たパツケージの表面を吸湿性の高い樹脂で覆つて
なることを特徴とする半導体装置。 A semiconductor device characterized in that the surface of a package molded from a resin with low hygroscopicity and high insulating properties is covered with a highly hygroscopic resin.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986176822U JPS6382945U (en) | 1986-11-17 | 1986-11-17 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986176822U JPS6382945U (en) | 1986-11-17 | 1986-11-17 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6382945U true JPS6382945U (en) | 1988-05-31 |
Family
ID=31117442
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986176822U Pending JPS6382945U (en) | 1986-11-17 | 1986-11-17 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6382945U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0878558A (en) * | 1994-09-08 | 1996-03-22 | Kyocera Corp | Package for semiconductor element |
-
1986
- 1986-11-17 JP JP1986176822U patent/JPS6382945U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0878558A (en) * | 1994-09-08 | 1996-03-22 | Kyocera Corp | Package for semiconductor element |
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