JPS6373227A - Control driving circuit for liquid crystal panel - Google Patents
Control driving circuit for liquid crystal panelInfo
- Publication number
- JPS6373227A JPS6373227A JP61217323A JP21732386A JPS6373227A JP S6373227 A JPS6373227 A JP S6373227A JP 61217323 A JP61217323 A JP 61217323A JP 21732386 A JP21732386 A JP 21732386A JP S6373227 A JPS6373227 A JP S6373227A
- Authority
- JP
- Japan
- Prior art keywords
- liquid crystal
- crystal panel
- circuit
- distortion
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 40
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 13
- 230000006866 deterioration Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 5
- 238000012935 Averaging Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
Landscapes
- Control Or Security For Electrophotography (AREA)
- Liquid Crystal Display Device Control (AREA)
- Liquid Crystal (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
液晶パネルの電極に印加する駆動パルスの立上り、立下
り時に液晶表示装置自体内に発生する歪電圧による液晶
パネルの表示劣化を防止するため、歪電圧を相殺するパ
ルス電圧を電極駆動パルスに印加するようにした液晶パ
ネルの制御駆動回路である。[Detailed Description of the Invention] [Summary] In order to prevent the display deterioration of the liquid crystal panel due to the strain voltage generated within the liquid crystal display device itself at the rise and fall of the drive pulse applied to the electrodes of the liquid crystal panel, the strain voltage is reduced. This is a control drive circuit for a liquid crystal panel that applies a canceling pulse voltage to an electrode drive pulse.
本発明は液晶表示装置に関する。 The present invention relates to a liquid crystal display device.
Ｃ従来技術〕
液晶（Ｌ ＣＤ）の駆動方法としては、いわゆる電圧平
均化法が知られている（例えば、特公昭５７−５７７１
８号公報）。電圧平均化法では種々の電圧レベルの電圧
を走査電極に供給する必要があるので、液晶パネルの電
源回路としては、第４図に図示のものが知られている。C. Prior Art] As a method for driving a liquid crystal (LCD), the so-called voltage averaging method is known (for example, Japanese Patent Publication No. 57-5771
Publication No. 8). In the voltage averaging method, it is necessary to supply voltages of various voltage levels to the scanning electrodes, so the one shown in FIG. 4 is known as a power supply circuit for a liquid crystal panel.
電源回路１は直列に接続された抵抗器１１〜１６の間に
電圧Ｖ Ｃ＋ ＋ Ｖ Ｃ２の電源を印加し、抵抗器１
１〜１６の接続点からそれぞれ絶縁用アンプ２１〜２５
を介して、電圧■、〜Ｖ、を発生させる。電圧Ｖ Ｃ＋
＋ Ｖ Ｃ２はＬＣＤの容量などにより決まる。また
電圧Ｖ、〜Ｖ６は電圧平均化法によって定める相互関係
をもって決められている。これらの電圧■１〜■６はド
ライバ回路を介して走査電極に選択的に印加される。Power supply circuit 1 applies a power supply of voltage V C+ + V C2 between resistors 11 to 16 connected in series, and resistor 1
Isolation amplifiers 21 to 25 from connection points 1 to 16, respectively
A voltage ■, ~V, is generated through the voltage. Voltage V C+
+V C2 is determined by the capacity of the LCD, etc. Further, the voltages V, to V6 are determined by a mutual relationship determined by a voltage averaging method. These voltages (1) to (6) are selectively applied to the scan electrodes via a driver circuit.
液晶パネル部３は、走査電極および信号電極を具備する
液晶パネル、および、これらの電極駆動用ドライバ回路
を示す。The liquid crystal panel section 3 shows a liquid crystal panel including scanning electrodes and signal electrodes, and a driver circuit for driving these electrodes.
液晶パネルを電気的にみると静電容量成分とみることが
できる。従って、電極駆動用ドライバを介して電源回路
１から走査電極に駆動パルス電圧を印加すると、接続さ
れる抵抗器１１〜１６の抵抗値と液晶パネルの静電容量
成分とにより、駆動パルス電圧の立上り、立下り時に微
分された歪電圧が生じる。この歪電圧は第３図（ａ）に
図示の如く、フレーム切換時ＬＦＣＩ ＋ ｔＦＣＺ
に特に観察される。When looking at a liquid crystal panel electrically, it can be seen as a capacitance component. Therefore, when a drive pulse voltage is applied from the power supply circuit 1 to the scanning electrode via the electrode drive driver, the rise of the drive pulse voltage is caused by the resistance values of the connected resistors 11 to 16 and the capacitance component of the liquid crystal panel. , a differentiated strain voltage occurs at the falling edge. As shown in Fig. 3(a), this distortion voltage is LFCI + tFCZ at the time of frame switching.
Especially observed.
このような歪電圧が印加されると液晶パネルにクロスト
ークが生じる、明るさが変化する等の表示性能の低下が
生じる。When such a distorted voltage is applied, display performance deteriorates, such as crosstalk occurring in the liquid crystal panel and changes in brightness.
上述の歪電圧の除去に対しては通常のフィルタリング処
理が講じられているのであるが、有効に歪電圧を除去す
ることができず表示性能の低下に遭遇している。Although normal filtering processing is used to remove the above-mentioned distorted voltage, it is not possible to effectively remove the distorted voltage, resulting in a decrease in display performance.
〔問題を解決するための手段、および、作用〕本発明は
第１図の原理ブロック図に示すように、液晶パネルおよ
び液晶パネル内の走査電極および信号電極を駆動するド
ライバ回路を含む液晶パネル部３に対し、電源回路１、
主制御回路４、タイミング制御回路５、歪信号相殺信号
発生回路６およびアンプ８から成る制御駆動回路を用い
て液晶表示制御を行う。[Means for Solving the Problems and Effects] As shown in the principle block diagram of FIG. 3, power supply circuit 1,
A control drive circuit including a main control circuit 4, a timing control circuit 5, a distortion signal cancellation signal generation circuit 6, and an amplifier 8 is used to control the liquid crystal display.
歪信号相殺信号発生回路６およびアンプ８が新たに設け
られ、歪信号相殺信号発生回路６を制御するためタイミ
ング制御回路５が機能追加されている。その他の要素は
、従来と同様である。A distortion signal cancellation signal generation circuit 6 and an amplifier 8 are newly provided, and a timing control circuit 5 is added in function to control the distortion signal cancellation signal generation circuit 6. Other elements are the same as before.
主制御回路４は表示内容に応じて表示データＤＡＴＡを
液晶パネル部３の信号電極に印加する。また主制御回路
４はタイミング信号ＴＭＧをタイミング制御回路５に与
える。タイミング制御回路５は電圧平均化法に基づいて
所定の走査電極に所定の電圧パルスが電源回路１から印
加されるようにタイミング制御する。The main control circuit 4 applies display data DATA to the signal electrodes of the liquid crystal panel section 3 according to the display content. The main control circuit 4 also provides a timing signal TMG to the timing control circuit 5. The timing control circuit 5 performs timing control based on a voltage averaging method so that a predetermined voltage pulse is applied from the power supply circuit 1 to a predetermined scanning electrode.
歪信号相殺信号発生回路は、液晶パネルの走査電極を介
して電源回路の抵抗器と作動的に接続される液晶パネル
の静電容量成分および抵抗器の抵抗値とにより規定され
る時定数、および、複数の電圧レベルに応じて規定され
る振幅およびパルス幅を持つパルス電圧を、すなわち、
歪信号相殺信号複数の電圧に重畳させる。この歪信号相
殺イＳ号により、歪成分を除去する。The distortion signal cancellation signal generation circuit has a time constant defined by a capacitance component of the liquid crystal panel and a resistance value of the resistor, which is operatively connected to a resistor of the power supply circuit through the scanning electrode of the liquid crystal panel, and , a pulsed voltage with amplitude and pulse width defined according to multiple voltage levels, i.e.
The distortion signal cancellation signal is superimposed on multiple voltages. Distortion components are removed by this distortion signal canceling signal S.
歪信号相殺信号発生回路は走査電極の駆動タイミングに
応じて作動するが、好適にはフレーム切換時に作動する
のが好ましい。歪信号相殺信号発生回路の作動タイミン
グはタイミング制御回路５が行う。The distortion signal canceling signal generation circuit operates in accordance with the driving timing of the scanning electrodes, and preferably operates at the time of frame switching. The timing control circuit 5 controls the operation timing of the distortion signal cancellation signal generation circuit.
第１図の歪信号相殺信号発生回路６の実施例回路図を第
２図に示す。FIG. 2 shows a circuit diagram of an embodiment of the distortion signal canceling signal generating circuit 6 shown in FIG.
歪信号相殺信号発生回路６は単パルス発生器６０、直列
に接続された可変抵抗器６１〜６５、および可変抵抗器
の接続点に接続されたスイッチ７１〜７５から成る。ス
イッチ７１〜７５の共通接続点がアンプ８を介して第１
図のアンプ２４の出力端に接続される。The distortion signal canceling signal generation circuit 6 includes a single pulse generator 60, variable resistors 61-65 connected in series, and switches 71-75 connected to the connection points of the variable resistors. The common connection point of the switches 71 to 75 is connected to the first
It is connected to the output terminal of the amplifier 24 shown in the figure.
単パルス発生器６０はタイミング制御回路５からトリガ
信号ＴＲＧが印加されることにより単パルスを出力する
。またスイッチ７１〜７５のうち、走査電極に印加すべ
き電圧レベルに相当するもの、例えば、電圧■１に対し
てスイッチ７１が、タイミング制御回路５からの選択信
号ＳＥＬにより一定時間閉成される。各スイッチの閉成
時間は単パルス発生回路６０からの単パルスのパルス幅
より長く、且つ、単パルスが開成期間にあるように定め
である。The single pulse generator 60 outputs a single pulse when the trigger signal TRG is applied from the timing control circuit 5. Further, among the switches 71 to 75, the switch 71 corresponding to the voltage level to be applied to the scanning electrode, for example, the voltage 1, is closed for a certain period of time by the selection signal SEL from the timing control circuit 5. The closing time of each switch is longer than the pulse width of the single pulse from the single pulse generating circuit 60, and is determined such that the single pulse is in the open period.
第３図（ａ）に電極印加パルスのフレーム切換時に生じ
た歪波形を示す。第３図（ａ）の歪成分のみを取り出し
、基準電圧、例えばそれぞれｖ１〜■６に対応する電圧
に対する波形を第３図（ｂ）に示す。従って、歪信号相
殺信号全仕口路６からは、第３図（Ｃ）に図示の如く歪
相殺パルスＳＣＬを出力する。FIG. 3(a) shows a distorted waveform that occurs when switching frames of electrode applied pulses. Only the distortion components in FIG. 3(a) are taken out, and the waveforms for the reference voltages, for example, voltages corresponding to v1 to v6, respectively, are shown in FIG. 3(b). Therefore, the distortion canceling pulse SCL is outputted from the distortion signal canceling signal path 6 as shown in FIG. 3(C).
第１図における電源回路１の電圧を■ｃ１＝＋５Ｖ、Ｖ
ｃｚ＝ ２０Ｖとした場合、歪電圧振幅Ｖｄははゾ２〜
３■程度（絶対値）である。またその時間τｄは数１０
μｓ程度である。歪電圧振幅Ｖｄは基準電圧により変わ
るから、基準電圧に応じて定まる歪電圧振幅に相当する
振幅ＶＣの歪相殺パルスＶＣ１〜ＶＣ５をそれぞれ抵抗
器６１〜６５を介して出力する。単パルスのパルス幅τ
Ｃは歪電圧パルス幅τより若干小さくする。The voltage of power supply circuit 1 in Fig. 1 is c1=+5V, V
When cz = 20V, the distortion voltage amplitude Vd is 2~
It is about 3■ (absolute value). Also, the time τd is several 10
It is about μs. Since the distortion voltage amplitude Vd varies depending on the reference voltage, distortion canceling pulses VC1 to VC5 having an amplitude VC corresponding to the distortion voltage amplitude determined according to the reference voltage are outputted via resistors 61 to 65, respectively. Single pulse pulse width τ
C is made slightly smaller than the strain voltage pulse width τ.
歪成分の振幅Ｖｄ 、ｌ続時間τｄは一般に測定により
得られるものである。このため、測定結果に応じて相殺
パルスが調整し得るように、単パルス発生１８６０にお
いてパルス幅τＣ、パルス振幅、および抵抗器６１〜６
５をそれぞれ可変にできるようにしておくのが好ましい
。The amplitude Vd and duration τd of the distortion component are generally obtained by measurement. For this reason, in the single pulse generation 1860, the pulse width τC, the pulse amplitude, and the resistors 61 to 6 are adjusted so that the cancellation pulse can be adjusted according to the measurement results.
It is preferable to make each of 5 variable.
第２図の回路は主として負側歪パルスの相殺についての
ものであるが、正側歪パルスの相殺についても同様であ
る。Although the circuit of FIG. 2 is mainly concerned with canceling negative side distortion pulses, the same applies to cancellation of positive side distortion pulses.
相殺パルスの発生、重量は、フレーム切換期間が６０〜
８０）１ｚ程度と比較的長く、フレーム切換時に特に歪
が発生することが観察されることから、フレーム切換に
同期して行うのが実際的で且つ効率よい。但し、第３図
（ａ）に図示の如く選択点信号パルスＶｂ、選択点パル
ス■２等の印加時に相殺パルスを発生、重畳させてもよ
い。The generation and weight of cancellation pulses are determined when the frame switching period is 60~
80) It is relatively long, about 1z, and it has been observed that distortion occurs especially when switching frames, so it is practical and efficient to perform it in synchronization with frame switching. However, as shown in FIG. 3(a), a cancellation pulse may be generated and superimposed upon application of the selection point signal pulse Vb, selection point pulse 2, etc.
以上に述べたように本発明によれば、液晶表示装置内に
発生する歪成分を相殺し、液晶表示性能の低下を防止す
ることができる。As described above, according to the present invention, it is possible to cancel the distortion components generated in the liquid crystal display device and prevent the liquid crystal display performance from deteriorating.
第１図は本発明の液晶表示側′４１■駆動回路の原理ブ
ロック図、
第２図は第１図の歪信号相殺信号発生回路の実施例回路
図、
第３図（ａ）〜（Ｃ）は第２図回路の動作を説明するタ
イミング図、
第４図は従来の液晶表示制御駆動回路図、である。
（符号の説明）
１・・・電源回路、 ３・・・液晶パネル部、４・
・・主制御回路、 ５・・・タイミング制御回路、
６・・・歪信号相殺信号発生回路。
本発明の液晶表示匍御駆動回路の原理ブロック図３・
液晶・ぐネル部
４ ・主制御回路
５ ・ タイミング制御回路
６ 歪信号相殺信号発生回路
８７ンプ
第１図の歪信号相殺信号発生回路の実施例回路図第２図
第２図回路の動作タイミング図
第３図
従来の液晶表示制御駆動回路図
第４図Figure 1 is a principle block diagram of the liquid crystal display side drive circuit of the present invention; Figure 2 is an embodiment circuit diagram of the distortion signal canceling signal generation circuit of Figure 1; Figures 3 (a) to (C). 2 is a timing diagram explaining the operation of the circuit, and FIG. 4 is a conventional liquid crystal display control drive circuit diagram. (Explanation of symbols) 1... Power supply circuit, 3... Liquid crystal panel section, 4...
...Main control circuit, 5...Timing control circuit,
6...Distortion signal cancellation signal generation circuit. Principle block diagram 3 of the liquid crystal display control drive circuit of the present invention.
Liquid crystal channel section 4 ・Main control circuit 5 ・Timing control circuit 6 Distortion signal cancellation signal generation circuit 87 Amplifier Embodiment circuit diagram of the distortion signal cancellation signal generation circuit shown in FIG. 1 FIG. 2 Operation timing diagram of the circuit Fig. 3 Conventional LCD display control drive circuit diagram Fig. 4
Claims (1)
をドライバ回路を介して液晶パネルの走査電極に印加す
る電源回路を含む液晶パネルの制御駆動回路において、 前記液晶パネルの走査電極を介して前記電源回路の抵抗
器と作動的に接続される液晶パネルの静電容量成分およ
び前記抵抗器の抵抗値とにより規定される時定数、およ
び、前記複数の電圧レベルに応じて規定される振幅およ
びパルス幅を持つパルス電圧を、前記走査電極の駆動タ
イミングに応じて、前記複数の電圧に重畳させる歪信号
相殺信号発生回路を具備したことを特徴とする、液晶パ
ネルの制御駆動回路。 ２、前記歪信号相殺信号発生回路が、前記液晶パネルの
フレーム切換に応じて動作する、特許請求の範囲第１項
に記載の液晶パネルの制御駆動回路。[Claims] 1. A control drive circuit for a liquid crystal panel including a power supply circuit that includes a plurality of resistors and applies a plurality of voltages through the resistors to scanning electrodes of the liquid crystal panel via a driver circuit, a time constant defined by a capacitance component of a liquid crystal panel operatively connected to a resistor of the power supply circuit via a scanning electrode of the liquid crystal panel and a resistance value of the resistor, and the plurality of voltages. A liquid crystal display device comprising: a distortion signal canceling signal generation circuit that superimposes a pulse voltage having an amplitude and a pulse width defined according to a level on the plurality of voltages according to drive timing of the scanning electrode. Panel control drive circuit. 2. The control drive circuit for a liquid crystal panel according to claim 1, wherein the distortion signal canceling signal generation circuit operates in response to frame switching of the liquid crystal panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61217323A JPS6373227A (en) | 1986-09-17 | 1986-09-17 | Control driving circuit for liquid crystal panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61217323A JPS6373227A (en) | 1986-09-17 | 1986-09-17 | Control driving circuit for liquid crystal panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6373227A true JPS6373227A (en) | 1988-04-02 |
Family
ID=16702372
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61217323A Pending JPS6373227A (en) | 1986-09-17 | 1986-09-17 | Control driving circuit for liquid crystal panel |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6373227A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5301047A (en) * | 1989-05-17 | 1994-04-05 | Hitachi, Ltd. | Liquid crystal display |
| CN101814265A (en) * | 2009-03-30 | 2010-08-25 | 矽创电子股份有限公司 | Driving circuit for display panel |
-
1986
- 1986-09-17 JP JP61217323A patent/JPS6373227A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5301047A (en) * | 1989-05-17 | 1994-04-05 | Hitachi, Ltd. | Liquid crystal display |
| CN101814265A (en) * | 2009-03-30 | 2010-08-25 | 矽创电子股份有限公司 | Driving circuit for display panel |
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