JPS636882Y2 - - Google Patents
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- Publication number
- JPS636882Y2 JPS636882Y2 JP14780682U JP14780682U JPS636882Y2 JP S636882 Y2 JPS636882 Y2 JP S636882Y2 JP 14780682 U JP14780682 U JP 14780682U JP 14780682 U JP14780682 U JP 14780682U JP S636882 Y2 JPS636882 Y2 JP S636882Y2
- Authority
- JP
- Japan
- Prior art keywords
- fet
- line
- drain electrode
- main line
- semiconductor switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- 239000004065 semiconductor Substances 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 description 16
- 239000008186 active pharmaceutical agent Substances 0.000 description 6
- 101150079361 fet5 gene Proteins 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
- Waveguide Switches, Polarizers, And Phase Shifters (AREA)
- Waveguides (AREA)
Description
【考案の詳細な説明】
この考案は半導体基板に構成したFETを用い
てマイクロ波を制御する単投双極形半導体スイツ
チの改良に関するものである。[Detailed description of the invention] This invention relates to an improvement of a single-throw bipolar semiconductor switch that controls microwaves using an FET constructed on a semiconductor substrate.
第１図は従来の単投双極形半導体スイツチの構
成例を斜視図で示す。 FIG. 1 is a perspective view showing an example of the configuration of a conventional single-throw bipolar semiconductor switch.
図中、１は半導体基板、２は地導体、３は地導
体２と共に構成されるマイクロストリツプ線路か
ら成る主線路、４ａは同じくマイクロストリツプ
線路による第１の副線路、４ｂは同じくマイクロ
ストリツプ線路による第２の副線路、５はFET、
６はFET５のドレイン電極、７ａはFET５の第
１のソース電極、７ｂはFET５の第２のソース
電極、８ａはFET５の第１のゲート電極、８ｂ
はFET５の第２のゲート電極、９は1/4波長の長
さの高インピーダンス線路、１０は高インピーダ
ンス線路９を接地するための貫通導体、１１ａ，
１１ｂはそれぞれ第１及び第２のゲート電極８
ａ，８ｂにバイアスを印加するためのマイクロス
トリツプ線路から成るバイアス回路である。 In the figure, 1 is a semiconductor substrate, 2 is a ground conductor, 3 is a main line consisting of a microstrip line configured together with the ground conductor 2, 4a is a first sub-line also made of a microstrip line, and 4b is also a The second sub line is a microstrip line, 5 is an FET,
6 is the drain electrode of FET5, 7a is the first source electrode of FET5, 7b is the second source electrode of FET5, 8a is the first gate electrode of FET5, 8b
is the second gate electrode of the FET 5, 9 is a high impedance line with a length of 1/4 wavelength, 10 is a through conductor for grounding the high impedance line 9, 11a,
11b are the first and second gate electrodes 8, respectively.
This is a bias circuit consisting of a microstrip line for applying a bias to a and 8b.
従来の単投双極形半導体スイツチは、主線路３
と第１及び第２の副線路４ａ，４ｂとは直角の関
係に配置され、FET５のドレイン電極６は主線
路３の先端近くの側面に、又第１のソース電極７
ａ及び第２のソース電極７ｂはそれぞれ第１の副
線路４ａ及び第２の副線路４ｂに接続され、
FET５のドレイン電極６と第１のソース電極７
ａ間及びドレイン電極６と第２のソース電極７ｂ
間に第１のゲート電極８ａ及び第２のゲート電極
８ｂをそれぞれ形成している。 A conventional single-throw double-pole semiconductor switch has three main lines.
and the first and second sub-lines 4a, 4b are arranged in a right-angled relationship, and the drain electrode 6 of the FET 5 is located on the side near the tip of the main line 3, and the first source electrode 7
a and the second source electrode 7b are connected to the first sub-line 4a and the second sub-line 4b, respectively,
Drain electrode 6 and first source electrode 7 of FET 5
a and between the drain electrode 6 and the second source electrode 7b
A first gate electrode 8a and a second gate electrode 8b are respectively formed between them.
加えて、主線路３には先端を貫通導体１０で接
地した1/4波長の長さの高インピーダンス線路９
を付加し、FET５の第１のゲート電極８ａ及び
第２のゲート電極８ｂにバイアス電圧を印加する
場合の直流リターン回路を形成している。 In addition, the main line 3 includes a high impedance line 9 with a length of 1/4 wavelength whose tip is grounded with a through conductor 10.
is added to form a DC return circuit when applying a bias voltage to the first gate electrode 8a and the second gate electrode 8b of the FET 5.
第２図は一般的なFETの特性説明に用いる図
で、ゲート電極のバイアス電圧を変えた時のソー
ス電極とドレイン電極間の電圧・電流特性であ
る。図中１２ａ，１２ｂはそれぞれゲート電極の
バイアス電圧を零、ピンチオフ状態としたときの
特性曲線である。 Figure 2 is a diagram used to explain the characteristics of a typical FET, and shows the voltage and current characteristics between the source and drain electrodes when the bias voltage of the gate electrode is changed. In the figure, 12a and 12b are characteristic curves when the bias voltage of the gate electrode is zero and in a pinch-off state, respectively.
なお、説明の都合上、ここではソース電極とド
レイン電極との間の電圧をVDS、電流をIDSとす
る。 Note that for convenience of explanation, the voltage between the source electrode and the drain electrode is V DS and the current is I DS here.
この時、ソース電極とドレイン電極との間の抵
抗RDSは、RDS＝VDS／IDSで示される。 At this time, the resistance R DS between the source electrode and the drain electrode is expressed as R DS =V DS /I DS .
第３図ａ，ｂは一般的なマイクロストリツプ線
路から成る90度コーナ部の説明に用いる図で、ａ
は90度コーナ部の内部導体パターンを示し、ｂは
90度コーナ部の等価回路を示す。図中１３は内部
導体、１４は90度コーナ部で生じる容量である。 Figures 3a and 3b are diagrams used to explain a 90-degree corner section consisting of a general microstrip line.
indicates the internal conductor pattern at the 90 degree corner, and b indicates the internal conductor pattern at the 90 degree corner.
The equivalent circuit of a 90 degree corner is shown. In the figure, 13 is an internal conductor, and 14 is a capacitance generated at a 90-degree corner.
以下、これらの図を用いて従来の単投双極形半
導体スイツチについて説明する。 A conventional single-throw double-pole semiconductor switch will be described below with reference to these figures.
今、主線路３にマイクロ波を印加した場合を考
える。 Now, consider the case where microwaves are applied to the main line 3.
第１のゲート電極８ａにバイアス回路１１ａを
介して零電圧を印加し、第２のゲート電極８ｂに
バイアス回路１１ｂを介してピンチオフ電圧を印
加すると、第２図から判るように、第１のソース
電極７ａとドレイン電極６の間の抵抗は小さな値
を示し、第２のソース電極７ｂとドレイン電極６
の間の抵抗は大きな値を示す。 When zero voltage is applied to the first gate electrode 8a via the bias circuit 11a and a pinch-off voltage is applied to the second gate electrode 8b via the bias circuit 11b, as can be seen from FIG. The resistance between the electrode 7a and the drain electrode 6 shows a small value, and the resistance between the second source electrode 7b and the drain electrode 6 shows a small value.
The resistance between shows a large value.
このため、主線路３からのマイクロ波は第１の
副線路４ａに主に伝わる。 Therefore, the microwave from the main line 3 is mainly transmitted to the first sub-line 4a.
一方、第１のゲート電極８ａと第２のゲート電
極８ｂのバイアス電圧条件を逆にすると、同様に
主線路３からのマイクロ波は第２の幅線路４ｂに
主に伝わる。 On the other hand, if the bias voltage conditions of the first gate electrode 8a and the second gate electrode 8b are reversed, the microwave from the main line 3 is similarly mainly transmitted to the second width line 4b.
このように、第１、第２のゲート電極８ａ，８
ｂへのバイアス電圧を変えることにより、単投双
極形半導体スイツチが実現出来ている。 In this way, the first and second gate electrodes 8a, 8
By changing the bias voltage to b, a single-throw double-pole semiconductor switch can be realized.
しかし、一例として主線路３から第１の副線路
４ａにマイクロ波が伝わる状態をとりあげて考え
てみると、ドレイン電極６を構成している主線路
３の先端部が影響し、単投双極形半導体スイツチ
の整合特性に劣化がみられる。これは、主線路３
から第１の副線路４ａに通じる伝送系が第３図ａ
の90度コーナ部と同一の働きをしているためであ
る。 However, if we take as an example the state in which microwaves are transmitted from the main line 3 to the first sub-line 4a, we can see that the tip of the main line 3 that constitutes the drain electrode 6 has an effect, resulting in a single-throw bipolar type. Deterioration is seen in the matching characteristics of the semiconductor switch. This is main line 3
The transmission system leading from to the first sub-line 4a is shown in Figure 3a.
This is because it has the same function as the 90 degree corner of
以上のように、従来の単投双極形半導体スイツ
チではFET５近辺の形状の影響で、整合特性が
劣化し問題と成つていた。 As described above, in the conventional single-throw bipolar semiconductor switch, the matching characteristics deteriorated due to the shape of the vicinity of the FET 5, which caused problems.
この考案は、上記の問題点を解決するため、主
線路３の先端に直流リターン回路と整合素子の役
目を兼ねて先端が接地された1/4波長以下の長さ
の高インピーダンス線路を装着し、FET５近辺
の形状の影響で生じる単投双極形半導体スイツチ
の整合特性劣化を無くすることを目的としたもの
である。 In order to solve the above problems, this idea installs a high impedance line with a length of 1/4 wavelength or less at the tip of the main line 3, which also serves as a DC return circuit and a matching element, and whose tip is grounded. The purpose of this is to eliminate the deterioration in matching characteristics of a single-throw bipolar semiconductor switch caused by the shape of the vicinity of the FET5.
第４図は、この考案の実施例における単投双極
形半導体スイツチの構成を斜視図で示す。 FIG. 4 is a perspective view showing the structure of a single-throw bipolar semiconductor switch according to an embodiment of this invention.
この考案による単投双極形半導体スイツチは、
主線路３の先端に先端が貫通導体１０で接地され
た1/4波長以下の高インピーダンス１３を装着し、
構成している。 The single-throw bipolar semiconductor switch based on this idea is
A high impedance 13 of 1/4 wavelength or less is attached to the tip of the main line 3, the tip of which is grounded with a through conductor 10,
It consists of
これらの貫通導体１０と高インピーダンス線路
１５は、直流的に観るとFET５の第１のゲート
電極８ａ及び第２のゲート電極８ｂにバイアス電
圧を印加する場合の直流リターン回路の役目を成
し、マイクロ波的に観ると主線路３の先端と地導
体３間にインダクタンスが装荷されたのと等価な
役目を成している。 From a direct current perspective, these through conductors 10 and high impedance lines 15 serve as a direct current return circuit when applying a bias voltage to the first gate electrode 8a and second gate electrode 8b of the FET 5. From a wave perspective, it plays a role equivalent to loading an inductance between the tip of the main line 3 and the ground conductor 3.
以下、これらの図を用いて、この考案による単
投双極形半導体スイツチについて説明する。 The single-throw bipolar semiconductor switch according to this invention will be explained below with reference to these figures.
なお、この考案による単投双極形半導体スイツ
チの基本動作（第１及び第２のゲート電極８ａ，
８ｂのバイアス電圧条件に対するマイクロ波の伝
わり方）は従来の単投双極形半導体スイツチと同
じであるため、説明を省略する。 The basic operation of the single-throw bipolar semiconductor switch according to this invention (first and second gate electrodes 8a,
8b) is the same as that of a conventional single-throw double-pole semiconductor switch, so a description thereof will be omitted.
この考案による単投双極形半導体スイツチで
は、一例として主線路３から第１の副線路４ａに
マイクロ波が伝わる状態をとりあげて考えてみる
と、ドレイン電極６を構成している主線路３の先
端に、マイクロ波的に観て高インピーダンス線路
１５と貫通導体１０による並列インダクタンスを
装着しているため、整合特性が改善されている。 In the single-throw bipolar semiconductor switch according to this invention, if we consider as an example the state in which microwaves are transmitted from the main line 3 to the first sub-line 4a, the tip of the main line 3 forming the drain electrode 6 is Furthermore, since a parallel inductance is provided by the high impedance line 15 and the through conductor 10 from a microwave perspective, the matching characteristics are improved.
これは、主線路３から第１の副線路４ａを通じ
る伝送系の中でかつFET５の近辺で生じる90度
コーナ部と等価な第３図ｂで示される容量１４と
上記並列インダクタンスとで並列共振を実現させ
ているからである。 This is due to the parallel resonance between the capacitance 14 shown in FIG. 3b, which is equivalent to the 90-degree corner that occurs in the transmission system from the main line 3 to the first sub-line 4a, and near the FET 5, and the parallel inductance. This is because it is realized.
このように、この考案による単投双極形半導体
スイツチでは、主線路３の先端に装着した先端が
貫通導体１０で接地された1/4波長以下の長さの
高インピーダンス線路１５により、余分な整合素
子、直流リターン回路を付加する必要もなく、整
合特性を改善している。 In this way, in the single-throw bipolar semiconductor switch according to this invention, redundant matching is achieved by the high impedance line 15 with a length of 1/4 wavelength or less, which is attached to the tip of the main line 3 and whose tip is grounded by the through conductor 10. There is no need to add an element or DC return circuit, and the matching characteristics are improved.
なお、以上は単投双極形半導体スイツチについ
て説明したが、この考案はこれに限らず、スイツ
チドライン形半導体移相器に用いても良い。又、
FETのソース電極、ドレイン電極間をインタデ
イジタル構成でかつインタデイジタル構成内にゲ
ート電極を折り曲げ構成で形成した単投双極形半
導体スイツチにも適用出来る。 Although the above description has been made regarding a single-throw bipolar semiconductor switch, this invention is not limited to this, and may be applied to a switched line type semiconductor phase shifter. or,
It can also be applied to a single-throw bipolar semiconductor switch in which the source electrode and drain electrode of an FET are formed in an interdigital configuration, and the gate electrode is formed in a folded configuration within the interdigital configuration.
以上のように、この考案に係る単投双極形半導
体スイツチでは、直流リターン回路を整合素子と
兼用しているため、特性の改善、構成の簡略化に
効果がある。 As described above, in the single-throw bipolar semiconductor switch according to the present invention, since the DC return circuit also serves as a matching element, it is effective in improving the characteristics and simplifying the configuration.
第１図は従来の単投双極形半導体スイツチの構
成を示す斜視図、第２図は一般的なFETの説明
に用いるFETの静特性を示す図、第３図ａ，ｂ
は一般的なマイクロストリツプ線路から成る90度
コーナの説明に用いる図で同図ａは90度コーナの
内部導体パターン図、同図ｂは90度コーナの等価
回路図、第４図はこの考案の一実施例による単投
双極形半導体スイツチの構成を示す斜視図であ
る。
図中、１は半導体基板、２は地導体、３は主線
路、４ａ，４ｂは第１及び第２の副線路、５は
FET、６はドレイン電極、７ａ，７ｂは第１及
び第２のソース電極、８ａ，８ｂは第１及び第２
のゲート電極、９は長さ1/4波長の高インピーダ
ンス線路、１０は貫通導体、１１ａ，１１ｂはバ
イアス回路、１２ａ，１２ｂは特性曲線、１３は
90度コーナの内部導体パターン、１４は90度コー
ナで生じる容量、１５は長さ1/4波長以下の高イ
ンピーダンス線路である。なお、図中同一あるい
は相当部分には同一符号を付して示してある。
Figure 1 is a perspective view showing the configuration of a conventional single-throw bipolar semiconductor switch, Figure 2 is a diagram showing the static characteristics of FET used to explain general FETs, Figure 3 a, b
Figure 4 is a diagram used to explain a 90 degree corner made of a general microstrip line. 1 is a perspective view showing the structure of a single-throw bipolar semiconductor switch according to an embodiment of the invention; FIG. In the figure, 1 is a semiconductor substrate, 2 is a ground conductor, 3 is a main line, 4a and 4b are first and second sub-lines, and 5 is a ground conductor.
FET, 6 is a drain electrode, 7a, 7b are first and second source electrodes, 8a, 8b are first and second
9 is a high impedance line with a length of 1/4 wavelength, 10 is a through conductor, 11a and 11b are bias circuits, 12a and 12b are characteristic curves, and 13 is a
The internal conductor pattern at the 90 degree corner, 14 is the capacitance generated at the 90 degree corner, and 15 is a high impedance line with a length of 1/4 wavelength or less. It should be noted that the same or corresponding parts in the figures are indicated by the same reference numerals.
Claims (1)
基板に構成したマイクロストリツプ線路とを接
続して成る単双極形半導体スイツチにおいて、
上記マイクロストリツプ線路から成る主線路、
第１の副線路及び第２の副線路の先端を開放端
とし、上記主線路と上記第１及び第２の副線路
とがそれぞれ直交するように、上記第１及び第
２の副線路の先端と上記主線路の先端に近い側
面とを臨接して配置するとともに、上記隣接部
の主線路を上記FETのドレイン電極とし、同
じく隣接部の上記第１及び第２の副線路をそれ
ぞれ上記FETの第１及び第２のソース電極と
し、上記FETのドレイン電極と第１のソース
電極の間に第１のゲート電極を形成し、同じく
FETのドレイン電極と第２のソース電極の間
に第２のゲート電極を形成し、上記主線路の先
端には一端が接地された1/4波長以下の長さの
高インピーダンス線路を付加し、上記FETの
第１及び第２のゲート電極にはそれぞれバイア
ス電圧を印加する手段を具備した事を特徴とす
る単投双極形半導体スイツチ。 (2) 上記FETのドレイン電極と第１のソース電
極間及びドレイン電極と第２のソース電極間を
それぞれインタデイジタル構成とし、上記イン
タデイジタル部にそれぞれ上記FETの第１及
び第２のゲート電極を折り曲げ構造で形成した
ことを特徴とする実用新案登録請求の範囲第(1)
項記載の単投双極形半導体スイツチ。[Claims for Utility Model Registration] (1) In a single bipolar semiconductor switch that connects an FET configured on a semiconductor substrate and a microstrip line configured on the semiconductor substrate,
A main line consisting of the above microstrip line,
The tips of the first and second sub-lines are open ends, and the tips of the first and second sub-lines are arranged such that the main line and the first and second sub-lines are perpendicular to each other. and a side surface near the tip of the main line are placed in close contact with each other, the main line in the adjacent part is used as the drain electrode of the FET, and the first and second sub-lines in the adjacent part are respectively used as the drain electrode of the FET. a first gate electrode is formed between the drain electrode and the first source electrode of the FET;
A second gate electrode is formed between the drain electrode and the second source electrode of the FET, and a high impedance line with a length of 1/4 wavelength or less with one end grounded is added to the tip of the main line, A single-throw bipolar semiconductor switch, comprising means for applying a bias voltage to each of the first and second gate electrodes of the FET. (2) An interdigital structure is formed between the drain electrode and the first source electrode and between the drain electrode and the second source electrode of the FET, and the first and second gate electrodes of the FET are provided in the interdigital part, respectively. Utility model registration claim No. (1) characterized by being formed with a folded structure
Single-throw double-pole semiconductor switch as described in .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14780682U JPS5952702U (en) | 1982-09-29 | 1982-09-29 | Single throw double pole semiconductor switch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14780682U JPS5952702U (en) | 1982-09-29 | 1982-09-29 | Single throw double pole semiconductor switch |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5952702U JPS5952702U (en) | 1984-04-06 |
| JPS636882Y2 true JPS636882Y2 (en) | 1988-02-27 |
Family
ID=30328582
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14780682U Granted JPS5952702U (en) | 1982-09-29 | 1982-09-29 | Single throw double pole semiconductor switch |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5952702U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8941096B2 (en) | 2001-12-05 | 2015-01-27 | Semiconductor Energy Laboratory Co., Ltd. | Organic semiconductor element |
-
1982
- 1982-09-29 JP JP14780682U patent/JPS5952702U/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8941096B2 (en) | 2001-12-05 | 2015-01-27 | Semiconductor Energy Laboratory Co., Ltd. | Organic semiconductor element |
| US9312507B2 (en) | 2001-12-05 | 2016-04-12 | Semiconductor Energy Laboratory Co., Ltd. | Organic semiconductor element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5952702U (en) | 1984-04-06 |
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