JPS636864A - Transistor device - Google Patents

Transistor device

Info

Publication number
JPS636864A
JPS636864A JP61150420A JP15042086A JPS636864A JP S636864 A JPS636864 A JP S636864A JP 61150420 A JP61150420 A JP 61150420A JP 15042086 A JP15042086 A JP 15042086A JP S636864 A JPS636864 A JP S636864A
Authority
JP
Japan
Prior art keywords
heat
metal plate
transistor
plate
dielectric substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61150420A
Other languages
Japanese (ja)
Inventor
Sukeyuki Masuno
升野　祐之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61150420A priority Critical patent/JPS636864A/en
Publication of JPS636864A publication Critical patent/JPS636864A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To enable radiation of heat generated from a transistor to be performed in a short time, by making cooling elements using a Peltier effect formed between a dielectric substrate and a heat dissipation plate. CONSTITUTION:Cooling elements using a Peltier effect, such as a metallic plate 9a-a P-type semiconductor 11-a metallic plate 9b are formed between a dielectric substrate 2 and a heat dissipation plate 1. Current flowing from an output lead 8 is made to flow through a metallized part 3b, a conductive matter 10, metallic plate 9b, the semiconductor 11, the metallic plate 9a to the heat dissipation plate 1. As regards dissipation of heat, the heat is forcedly absorbed by the Peltier effect in the junction part between the metallic part 9b and the semiconductor 11, and then the heat generated in the junction part between the metallic plate 9a and the semiconductor 11 is dissipated in the heat dissipation plate 1. Therefore, the dissipation of the heat generated from the transistor 4 can be performed in a short time.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、トランジスタ装置、特に、ペルチェ効果を
利用して放熱をよくするトランジスタ装置に関するもの
である◇ 〔従来の技術〕 従来例によるこの種の高周波高出力トランジスタ装置の
概要構成を第２図に示す。この図において、符号（１）
は放熱板、（”’）は板面にパターニングされたメタラ
イズ部（３ｍ）　（３ｂ）を有して放熱板（１）上に取
り付けられた誘電体基板、（４）はこの誘電体基板（２
ａ）上に塔載されるトランジスタであり、また（５）お
よび（６）は接地部および入力部へそれぞれ接続される
接地および入力ワイヤ、（７）および（８）は人力部お
よび出力部の入力および出力リードである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a transistor device, particularly a transistor device that utilizes the Peltier effect to improve heat dissipation. FIG. 2 shows a schematic configuration of the high-frequency, high-output transistor device. In this figure, code (1)
is a heat sink, ('') is a dielectric substrate that has a patterned metallized portion (3m) (3b) on the plate surface and is attached to the heat sink (1), (4) is this dielectric substrate ( 2
(5) and (6) are the ground and input wires connected to the ground section and the input section, respectively, and (7) and (8) are the transistors mounted on the power section and the output section. Input and output leads.

そして、この従来例の構成にあって、トランジスタ（４
）により発生した熱は下方に流れ、メタライズ部（３ａ
）　（３ｂ）を有した誘電体基板（２１Ｌ）を通して、
放熱板（１）により放熱される。In the configuration of this conventional example, transistors (4
) The heat generated by the metallized part (3a
) (3b) through the dielectric substrate (21L),
Heat is radiated by the heat sink (1).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

この従来例構成の場合、トランジスタ（４）の熱抵抗、
および誘電体基板（２ａ）のメタライズ部（５１））へ
のダイボンドの良否により、熱拡散が悪くなる可能性が
あった。In the case of this conventional configuration, the thermal resistance of the transistor (4),
Also, depending on the quality of the die bonding to the metallized portion (51) of the dielectric substrate (2a), heat diffusion may deteriorate.

この発明は、上記のような問題点を解消するためになさ
れたもので、トランジスタ（４）の温度を低く保ち、熱
による特性の低下を最小限におさえることのできるトラ
ンジスタ装置を得ることを目的とする。This invention was made to solve the above-mentioned problems, and aims to provide a transistor device that can keep the temperature of the transistor (4) low and minimize the deterioration of characteristics due to heat. shall be.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係るトランジスタ装置は、ベルチェ効果を利
用した冷却素子を有するものである。A transistor device according to the present invention includes a cooling element that utilizes the Beltier effect.

〔作用〕[Effect]

この発明におけるベルチェ効果を利用した冷却素子は、
トランジスタにより発生した熱を強制的に吸熱する。The cooling element using the Beltier effect in this invention is
The heat generated by the transistor is forcibly absorbed.

〔実施例〕〔Example〕

以下、この発明の一実施例を図につ−て説明する。第１
図にお−て、符号（１）は放熱板、（２）は板面の両面
にパターニングされたメタライズ部（３ａ）（３ｂ）を
有して放熱板（１）に取り付けられた誘電体基板、（４
）はこの誘電体基板（２）上に塔載される高周波高出力
トランジスタであり、（９−）　（９ｂ）は放熱板（１
）および誘電体基板（２）に取り付けられた金属板、（
１０は金属板（９ｂ）とメタライズ部（ｓｂ）をつなぐ
導電体、■はＰ型半導体である。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, symbol (1) is a heat sink, and (2) is a dielectric substrate that has metallized parts (3a) and (3b) patterned on both sides of the plate surface and is attached to the heat sink (1). , (4
) is a high frequency, high output transistor mounted on this dielectric substrate (2), (9-) (9b) is a heat sink (1)
) and a metal plate attached to the dielectric substrate (2), (
10 is a conductor connecting the metal plate (9b) and the metallized portion (sb), and 2 is a P-type semiconductor.

この実施例構成においては、出力リード（８）から流れ
てくる電流は、メタライズ部（３ｂ）　、導電体αＯ９
金属板（９ｂ）、Ｉ’型半導体０．金属板（９ａ）を通
り放熱板（１）に流れる。放熱に関してみるとき、ベル
チェ効果によシ金属板（９ｂ）とＰ型半導体Ｉとの接合
部は強制的に吸熱され、金属板（９＆）とＰ型半導体０
との接合部で発生した熱は、放熱板（１）により放熱す
る。そのため、トランジスタ（４）により発生した熱は
すぐに放熱し得るのである。In this embodiment configuration, the current flowing from the output lead (8) flows through the metallized portion (3b) and the conductor αO9.
Metal plate (9b), I' type semiconductor 0. It flows through the metal plate (9a) to the heat sink (1). Regarding heat radiation, heat is forcibly absorbed at the junction between the metal plate (9b) and the P-type semiconductor I due to the Beltier effect, and the junction between the metal plate (9&) and the P-type semiconductor I
The heat generated at the joint with the heat sink is radiated by the heat sink (1). Therefore, the heat generated by the transistor (4) can be quickly dissipated.

なお、上記実施例では、ベルチェ効果を用いた冷却素子
として、金属板−Ｐ型半導体−金属板を用いたものを示
したが、金属板−金属板、金属板−Ｎ型半導体−金属板
を用−てもよい。In the above example, a cooling element using the Beltier effect was shown using a metal plate-P-type semiconductor-metal plate, but a metal plate-metal plate, a metal plate-N-type semiconductor-metal plate, etc. It may be used.

また、金属板（９ａ）を放熱板（１）で代用してもよい
。Further, the metal plate (9a) may be replaced by a heat sink (1).

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれは、トランジスタ下部に
強制的に吸熱が行なわれるように構成したので、トラン
ジスタにより発生し上熱の放熱が短時間で可能になり、
熱によるトランジスタの特性低下を最小限におさえるこ
とができるものである。As described above, the present invention is configured such that heat is forcibly absorbed at the bottom of the transistor, so that the upper heat generated by the transistor can be dissipated in a short time.
This makes it possible to minimize deterioration of transistor characteristics due to heat.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、この発明の一実施例による高周波高山トラン
ジスタ装置を示す断面側面図、第２図は従来の高周波高
出力トランジスタ装置を示す断面側面図である。 図において、（１）・・・放熱板、（２）（２ａ）・・
・誘電体基板、（３ａ）　（３ｂ）・・・メタライズ部
、（４）・・・トランジスタ、ｔＳ＞および（６）・・
・接地および入力ワイヤ、（７）および（８）・・・入
力および出力リード、（９−）　（９ｂ）・・・金属板
、ＱＯ・・・導電体、α℃・・・Ｐｉ半導体である。 なお、図中、同一符号は同一、または相当部分を示す。FIG. 1 is a cross-sectional side view showing a high-frequency high-power transistor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional side view showing a conventional high-frequency high-output transistor device. In the figure, (1)...heat sink, (2)(2a)...
・Dielectric substrate, (3a) (3b)...metalized part, (4)...transistor, tS> and (6)...
・Grounding and input wires, (7) and (8)...Input and output leads, (9-) (9b)...Metal plate, QO...Conductor, α℃...Pi semiconductor . In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (2)

【特許請求の範囲】[Claims] （１）板面にパターニングされたメタライズ部を有して
、放熱板上に取り付けられた誘電体基板と、この誘電体
基板上に塔載されるトランジスタとを備えた構成におい
て、前記誘電体基板と放熱板の間にペルチエ効果を用い
た冷却素子を形成したことを特徴とするトランジスタ装
置。(1) In a configuration including a dielectric substrate having a patterned metallized portion on the plate surface and mounted on a heat sink, and a transistor mounted on the dielectric substrate, the dielectric substrate A transistor device characterized in that a cooling element using the Peltier effect is formed between a heat sink and a heat sink. （２）上記ペルチエ効果を用いた冷却素子が、金属板−
金属板、金属板−Ｎ型半導体−金属板、または金属板−
Ｐ型半導体−金属板であることを特徴とする特許請求の
範囲第１項記載のトランジスタ装置。(2) The cooling element using the above Peltier effect is a metal plate
Metal plate, metal plate - N-type semiconductor - metal plate or metal plate -
2. The transistor device according to claim 1, wherein the transistor device is a P-type semiconductor-metal plate.
JP61150420A 1986-06-26 1986-06-26 Transistor device Pending JPS636864A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61150420A JPS636864A (en) 1986-06-26 1986-06-26 Transistor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61150420A JPS636864A (en) 1986-06-26 1986-06-26 Transistor device

Publications (1)

Publication Number Publication Date
JPS636864A true JPS636864A (en) 1988-01-12

Family

ID=15496547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61150420A Pending JPS636864A (en) 1986-06-26 1986-06-26 Transistor device

Country Status (1)

Country Link
JP (1) JPS636864A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0456354U (en) * 1990-09-21 1992-05-14
US5818052A (en) * 1996-04-18 1998-10-06 Loral Fairchild Corp. Low light level solid state image sensor
US5895964A (en) * 1993-06-30 1999-04-20 Pioneer Electronic Corporation Thermoelectric cooling system
JP2004516653A (en) * 2000-12-11 2004-06-03 インターナショナル・ビジネス・マシーンズ・コーポレーション Thermoelectric spot cooling device for RF and microwave communication integrated circuits
WO2010050490A1 (en) * 2008-10-28 2010-05-06 株式会社ワイ・ワイ・エル Semiconductor device and cooling method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0456354U (en) * 1990-09-21 1992-05-14
US5895964A (en) * 1993-06-30 1999-04-20 Pioneer Electronic Corporation Thermoelectric cooling system
US5818052A (en) * 1996-04-18 1998-10-06 Loral Fairchild Corp. Low light level solid state image sensor
JP2004516653A (en) * 2000-12-11 2004-06-03 インターナショナル・ビジネス・マシーンズ・コーポレーション Thermoelectric spot cooling device for RF and microwave communication integrated circuits
WO2010050490A1 (en) * 2008-10-28 2010-05-06 株式会社ワイ・ワイ・エル Semiconductor device and cooling method
JP5453296B2 (en) * 2008-10-28 2014-03-26 株式会社ワイ・ワイ・エル Semiconductor device

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