JPS6365249U - - Google Patents

Info

Publication number
JPS6365249U
JPS6365249U JP15918986U JP15918986U JPS6365249U JP S6365249 U JPS6365249 U JP S6365249U JP 15918986 U JP15918986 U JP 15918986U JP 15918986 U JP15918986 U JP 15918986U JP S6365249 U JPS6365249 U JP S6365249U
Authority
JP
Japan
Prior art keywords
chip
equivalent circuit
type
diode
diffusion layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15918986U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15918986U priority Critical patent/JPS6365249U/ja
Publication of JPS6365249U publication Critical patent/JPS6365249U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本考案による１チツプ構成のシリー
ズダイオードの断面図であり、第２図は、それの
等価回路である。第３図は、Ｐ型とＮ型を入れか
えた場合の等価回路である。第４図は、シリーズ
ダイオードの等価回路を示したものであり、第５
図は従来の方法による２チツプ構成のシリーズダ
イオードの平面図である。第６図は１チツプ構成
による従来のシリーズダイオードの側を断面図で
示したものであり、第７図は、それの等価回路で
ある。 １……ダイオードペレツト、２……金属細線、
３……リードフレーム（コモン端子となる）、４
……金属電極、５……Ｎ型拡散層、６……Ｐ型低
濃度拡散層、７……Ｐ型拡散層、８……Ｎ型拡散
層、９……Ｐ型高濃度層（サブストレート）、１
０……ダイボンデイング用導電性ソルダー、１１
……等価回路における逆方向ダイオード、１２…
…チツプ表面とフレームとを接続する金属細線、
１３……上記１２を等価回路上で表わしたもの。 FIG. 1 is a sectional view of a one-chip series diode according to the present invention, and FIG. 2 is an equivalent circuit thereof. FIG. 3 is an equivalent circuit when the P type and N type are exchanged. Figure 4 shows the equivalent circuit of a series diode.
The figure is a plan view of a two-chip series diode constructed by a conventional method. FIG. 6 is a cross-sectional view of a conventional series diode having a one-chip configuration, and FIG. 7 is an equivalent circuit thereof. 1...Diode pellet, 2...Metal thin wire,
3...Lead frame (becomes a common terminal), 4
...Metal electrode, 5...N type diffusion layer, 6...P type low concentration diffusion layer, 7...P type diffusion layer, 8...N type diffusion layer, 9...P type high concentration layer (substrate ), 1
0... Conductive solder for die bonding, 11
...Reverse diode in equivalent circuit, 12...
...Thin metal wire that connects the chip surface and the frame,
13...Representation of the above 12 on an equivalent circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ワンチツプでシリーズ接続プレーナ構造のダイ
オードにおいて２つのダイオードの中間に位置す
るコモン電極を形成するためにワイヤーボンデイ
ング技術により素子表面とチツプ裏面を接続する
事を特徴とした半導体装置。 A semiconductor device characterized by connecting the front surface of the element and the back surface of the chip using wire bonding technology to form a common electrode located between two diodes in a series-connected planar structure diode in one chip.
JP15918986U 1986-10-17 1986-10-17 Pending JPS6365249U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15918986U JPS6365249U (en) 1986-10-17 1986-10-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15918986U JPS6365249U (en) 1986-10-17 1986-10-17

Publications (1)

Publication Number Publication Date
JPS6365249U true JPS6365249U (en) 1988-04-30

Family

ID=31083386

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15918986U Pending JPS6365249U (en) 1986-10-17 1986-10-17

Country Status (1)

Country Link
JP (1) JPS6365249U (en)

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