JPS6362336A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS6362336A
JPS6362336A JP20816186A JP20816186A JPS6362336A JP S6362336 A JPS6362336 A JP S6362336A JP 20816186 A JP20816186 A JP 20816186A JP 20816186 A JP20816186 A JP 20816186A JP S6362336 A JPS6362336 A JP S6362336A
Authority
JP
Japan
Prior art keywords
power supply
potential
ground potential
internal circuits
potential line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20816186A
Other languages
Japanese (ja)
Inventor
Hitoshi Mitani
三谷　仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP20816186A priority Critical patent/JPS6362336A/en
Publication of JPS6362336A publication Critical patent/JPS6362336A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To contrive to reduce a potential fluctuation generated in a specified internal circuit to be transmitted to other internal circuit by a method wherein one side or both of the power source potential conductors and earthing potential conductors of an internal circuit easy to be subjected to the effect of a power source variation are isolatedly formed and they individually transmit each potential. CONSTITUTION:Power source potential conductors 5a and 5b and earthing potential conductors 2a and 2b are each isolatedly formed and they are each formed in a constitution wherein the respective potential is transmitted by an individual bonding wire 3. Thereby, as a power source potential and an earth potential from outside of a chip can be given to an internal circuit 1a and internal circuits 1b and 1c independently of one another, the earth potential variation to generate in the internal circuit 1a becomes hard to transmit to the internal circuits 1b and 1c. Moreover, the number of the bonding wires 3 can be increased according to the magnitude of consumption current of the internal circuits 1a-1c.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路装置に関し、特にボンディング
線により内部回路の電源電位線及び接地電位線と電源電
位リード部及び接地電位リード部とをそれぞれボンディ
ング接続する半導体集積回路装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and particularly relates to a semiconductor integrated circuit device, in which a bonding line connects a power supply potential line and a ground potential line of an internal circuit to a power supply potential lead portion and a ground potential lead portion, respectively. The present invention relates to a semiconductor integrated circuit device connected by bonding.

〔従来の技術〕[Conventional technology]

従来、この種の半導体集積回路装置は、第２図に示すよ
うに、チップ内に設けられた内部回路１、〜・１３．に
電源電圧を供給する電源電位線５及び接地電位線２は、
それぞれ一体化された形状をしており、それぞれ所定の
位置において２本のボンディング線により対応する電源
電位リード部６と接地電位リード部４とにボンディング
接続される構造となっていた。Conventionally, this type of semiconductor integrated circuit device, as shown in FIG. 2, has internal circuits 1, . The power supply potential line 5 and the ground potential line 2 supplying the power supply voltage to the
Each of them has an integrated shape, and is structured to be bonded to the corresponding power supply potential lead part 6 and ground potential lead part 4 by two bonding wires at a predetermined position.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の半導体集積回路装置は、電源電位線５及
び接地電位線２がそれぞれ一体化された形状をしており
、それぞれ２本のボンディング線３によりそれぞれ電源
電位リード部６及び接地電位リード部４にボンディング
接続されているので、入・出力回路等のように、電源電
位及び接地電位の変動を生じやすい内部回路部１．で生
ずる電源電位線５及び接地電位線２の電位変動が、共通
の電源電位線５及び接地電位線２を介して差動増幅回路
等のように電位変動の影響を受けやすい内部回路１ｂ、
１ａに直接伝達され、回路特性の劣化や誤動作等を引き
起こす原因となるという欠点があった。The conventional semiconductor integrated circuit device described above has a shape in which the power supply potential line 5 and the ground potential line 2 are each integrated, and the power supply potential lead portion 6 and the ground potential lead portion are connected to each other by two bonding wires 3, respectively. Since the internal circuit section 1.4 is bonded to the internal circuit section 1.4, the power supply potential and ground potential are likely to fluctuate, such as input/output circuits. Internal circuits 1b, which are susceptible to potential fluctuations, such as differential amplifier circuits,
1a, which has the disadvantage of causing deterioration of circuit characteristics and malfunction.

本発明の目的は、特定の内部回路で発生した電源電位線
及び接地電位線の電位変動が他の内部回路に伝達される
ことを低減し、回路特性の劣化や誤動作を防止すること
のできる半導体集積回路装置を提供することにある。An object of the present invention is to reduce the transmission of potential fluctuations of a power supply potential line and a ground potential line generated in a specific internal circuit to other internal circuits, and to prevent deterioration of circuit characteristics and malfunction of a semiconductor device. An object of the present invention is to provide an integrated circuit device.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体集積回路装置は、チップ内に設けられた
複数の内部回路と、前記チップ内に設けられこれら各内
部回路にそれぞれ所定の電源電圧を供給する電源電位線
及び接地電位線と、片端をこれら電源電位線及び接地電
位線とそれぞれ複数本でボンディング接続するボンディ
ング線と、前記電源電圧を外部から供給するための電源
電位リード端子及び接地電位リード端子とそれぞれ接続
され、前記各ボンディング線の他端をそれぞれ対応して
ボンディング接続する電源電位リード部及び接地電位リ
ード部とを有する半導体集積回路装置において、前記各
内部回路を動作させたときに電位変動を生じやすい内部
回路の電源電位線及び接地電位線に対し、前記電位変動
の影響を受けやすい内部回路の電源電位線及び接地電位
線の片方又は両方を分離形成し、それぞれ別々に前記ボ
ンディング線で対応する前記電源電位リード部及び接地
電位リード部にボンディング接続して構成される。The semiconductor integrated circuit device of the present invention includes a plurality of internal circuits provided in a chip, a power supply potential line and a ground potential line provided in the chip and supplying predetermined power supply voltages to each of these internal circuits, and one end of the semiconductor integrated circuit device. A plurality of bonding wires are bonded to each of these power supply potential lines and ground potential lines, and each of the bonding wires is connected to a power supply potential lead terminal and a ground potential lead terminal for supplying the power supply voltage from the outside. In a semiconductor integrated circuit device having a power supply potential lead part and a ground potential lead part whose other ends are respectively bonded and connected, the power supply potential line and One or both of the power supply potential line and the ground potential line of the internal circuit that are susceptible to the potential fluctuations are formed separately from the ground potential line, and the corresponding power supply potential lead portion and the ground potential are separately formed using the bonding wire. It is configured by bonding to the lead part.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の一実施例を示す平面図である。FIG. 1 is a plan view showing one embodiment of the present invention.

この実施例が第２図に示された従来の半導体集積回路装
置と相違する点は、入・出力回路等のように電位変動の
発生しやすい内部回路１．の電源電位線５３及び接地電
位線２３をそれぞれ、差動増幅回路等のように電位変動
の影響を受けやすい内部回路１ｂ、１ｃの電源電位線５
ｂ及び接地電位線２ｂと分離形成し、これら電源電位線
５．。This embodiment is different from the conventional semiconductor integrated circuit device shown in FIG. The power supply potential line 53 and ground potential line 23 of
b and the ground potential line 2b, and these power supply potential lines 5. .

５ｂ及び接地電位線２−．２ｂをそれぞれ別々のボンデ
ィング線３により対応する電源電位リード部６及び接地
電位リード部４にボンディング接続した点にある。5b and ground potential line 2-. 2b are bonded to the corresponding power supply potential lead portion 6 and ground potential lead portion 4 by separate bonding wires 3, respectively.

この実施例のように、電源電位線５−．５ｂ及び接地電
位線２−．２ｂをそれぞれ分離形成し、それぞれ別々の
ボンディング線によりそれぞれの電位を伝達する構成に
することにより、内部回路１゜と内部回路１ｂ、１゜と
に互いに独立してチップ外部からの電源電位及び接地電
位を与えることができるので、内部回路１３で生ずる接
地電位変動は、内部回路１ｂ、ｌａに伝達しにくくなる
。As in this embodiment, power supply potential lines 5-. 5b and ground potential line 2-. By separately forming the circuits 2b and 1b and transmitting their respective potentials through separate bonding lines, the internal circuit 1゜ and the internal circuits 1b and 1゜ can be independently connected to the power supply potential and ground from outside the chip. Since a potential can be applied, ground potential fluctuations occurring in internal circuit 13 are less likely to be transmitted to internal circuits 1b and la.

なお、この実施例においては、それぞれの電源電位線５
．．５ｂ及び接地電位線２−．２ｂをそれぞれ１本のボ
ンディング線３により電源電位リード部６及び接地電位
リード部４に接続する構成となっているが、内部回路１
．〜ＩＣの消費電流の大きさに応じボンディング線３の
数を増すことができる。また、内部回路１ｂ＋１ｃにお
いては電源電位線５ｂ及び接地電位線２ｂをそれぞれ共
通としたが、これらをそれぞれ分離形成してもよい。Note that in this embodiment, each power supply potential line 5
．． ．． 5b and ground potential line 2-. 2b is connected to the power supply potential lead part 6 and the ground potential lead part 4 by one bonding wire 3, respectively, but the internal circuit 1
．． ~The number of bonding lines 3 can be increased depending on the amount of current consumed by the IC. Furthermore, although the power supply potential line 5b and the ground potential line 2b are common in the internal circuits 1b+1c, they may be formed separately.

また、この実施例においては、電源電位線５１゜５ｂ及
び接地電位線２−．２ｂを共に分離形成する構成をした
が、電位変動の状況に応じ、電源電位線または接地電位
線の何れが一方のみを分離形成する構成とすることもで
きる。Further, in this embodiment, the power supply potential line 51.5b and the ground potential line 2-. 2b are formed separately, however, depending on the situation of potential fluctuation, it is also possible to adopt a structure in which only one of the power supply potential line and the ground potential line is formed separately.

〔発明の効果〕 以上説明したように本発明は、電位変動の発生しやすい
内部回路の電源電位線及び接地電位線に対し、電源変動
の影響を受けやすい内部回路の電源電位線及び接地電位
線の片方または両方を分離形成し別々に各電位を伝達す
る構成とすることにより、特定の内部回路において発生
した電位変動が、他の内部回路に伝達されることを低減
するので、回路特性の劣化や誤動作を防止することがで
きる効果がある。[Effects of the Invention] As explained above, the present invention provides power supply potential lines and ground potential lines for internal circuits that are susceptible to power fluctuations, as opposed to power supply potential lines and ground potential lines for internal circuits that are susceptible to potential fluctuations. By forming one or both of them separately and transmitting each potential separately, it is possible to reduce the transmission of potential fluctuations occurring in a specific internal circuit to other internal circuits, thereby reducing the deterioration of circuit characteristics. This has the effect of preventing malfunctions and malfunctions.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す平面図、第２図は従来
の半導体集積回路装置の一例を示す平面図である。 １、〜１ｃ・・・内部回路、２．２−．２ｂ・・・接地
電位線、３・・・ボンディング線、４・・・接地電位リ
ード部、５．５−．５ｂ・・・電源電位線、６・・・電
源電位リード部。 差　ｌ　箇FIG. 1 is a plan view showing an embodiment of the present invention, and FIG. 2 is a plan view showing an example of a conventional semiconductor integrated circuit device. 1, ~1c...internal circuit, 2.2-. 2b... Ground potential line, 3... Bonding wire, 4... Ground potential lead portion, 5.5-. 5b...Power potential line, 6...Power potential lead part. Difference l

Claims (1)

【特許請求の範囲】[Claims] チップ内に設けられた複数の内部回路と、前記チップ内
に設けられこれら各内部回路にそれぞれ所定の電源電圧
を供給する電源電位線及び接地電位線と、片端をこれら
電源電位線及び接地電位線とそれぞれ複数本でボンディ
ング接続するボンディング線と、前記電源電圧を外部か
ら供給するための電源電位リード端子及び接地電位リー
ド端子とそれぞれ接続され、前記各ボンディング線の他
端をそれぞれ対応してボンディング接続する電源電位リ
ード部及び接地電位リード部とを有する半導体集積回路
装置において、前記各内部回路を動作させたときに電位
変動を生じやすい内部回路の電源電位線及び接地電位線
に対し、前記電位変動の影響を受けやすい内部回路の電
源電位線及び接地電位線の片方又は両方を分離形成し、
それぞれ別々に前記ボンディング線で対応する前記電源
電位リード部及び接地電位リード部にボンディング接続
したことを特徴とする半導体集積回路装置。A plurality of internal circuits provided in the chip, a power supply potential line and a ground potential line provided in the chip and supplying predetermined power supply voltages to each of these internal circuits, and one end connected to these power supply potential lines and the ground potential line. a plurality of bonding wires each connected by bonding, and a power supply potential lead terminal and a ground potential lead terminal for supplying the power supply voltage from the outside, respectively, and the other ends of each of the bonding wires are respectively connected by bonding. In a semiconductor integrated circuit device having a power supply potential lead portion and a ground potential lead portion, the potential fluctuation is caused to occur with respect to the power supply potential line and the ground potential line of the internal circuits that are likely to cause potential fluctuations when the respective internal circuits are operated. Separate one or both of the power supply potential line and ground potential line of internal circuits that are susceptible to
A semiconductor integrated circuit device, characterized in that the bonding wires are separately bonded to the corresponding power supply potential lead portion and ground potential lead portion.
JP20816186A 1986-09-03 1986-09-03 Semiconductor integrated circuit device Pending JPS6362336A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20816186A JPS6362336A (en) 1986-09-03 1986-09-03 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20816186A JPS6362336A (en) 1986-09-03 1986-09-03 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6362336A true JPS6362336A (en) 1988-03-18

Family

ID=16551663

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20816186A Pending JPS6362336A (en) 1986-09-03 1986-09-03 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6362336A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5621937A (en) * 1994-04-04 1997-04-22 S. Sclavos, S.A. Jet dyeing apparatus and method
WO2007114057A1 (en) * 2006-04-04 2007-10-11 Panasonic Corporation Semiconductor integrated circuit device, pdp driver and plasma display panel

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6077436A (en) * 1983-10-04 1985-05-02 Nec Corp Semiconductor integrated circuit
JPS622627A (en) * 1985-06-28 1987-01-08 Toshiba Corp Semiconductor integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6077436A (en) * 1983-10-04 1985-05-02 Nec Corp Semiconductor integrated circuit
JPS622627A (en) * 1985-06-28 1987-01-08 Toshiba Corp Semiconductor integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5621937A (en) * 1994-04-04 1997-04-22 S. Sclavos, S.A. Jet dyeing apparatus and method
WO2007114057A1 (en) * 2006-04-04 2007-10-11 Panasonic Corporation Semiconductor integrated circuit device, pdp driver and plasma display panel
US7855447B2 (en) 2006-04-04 2010-12-21 Panasonic Corporation Semiconductor integrated circuit device, PDP driver, and plasma display panel

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