JPS636121B2 - - Google Patents
Info
- Publication number
- JPS636121B2 JPS636121B2 JP55181363A JP18136380A JPS636121B2 JP S636121 B2 JPS636121 B2 JP S636121B2 JP 55181363 A JP55181363 A JP 55181363A JP 18136380 A JP18136380 A JP 18136380A JP S636121 B2 JPS636121 B2 JP S636121B2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- chip
- resistors
- layer
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 9
- 239000012212 insulator Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 description 17
- 239000000919 ceramic Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000654 additive Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229910010413 TiO 2 Inorganic materials 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910000859 α-Fe Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Description
【発明の詳細な説明】
本発明は、固体抵抗器、特に積層チツプ型抵抗
器に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to solid state resistors, in particular to multilayer chip resistors.
従来、固定抵抗器を含む各種の抵抗器は、リー
ド線間に配される抵抗体の材質と長さにより抵抗
値を設定している。しかしながら、この種の従来
の抵抗器は、要求される抵抗値に応じて長さが
種々変えられるので、一定の二次元寸法をもつこ
とが望まれるチツプ型の部品を構成するには不向
きである。また、最近、チツプ型の抵抗器とし
て、アルミナ等より成るベース（基体）上へ抵抗
ペーストを印刷して抵抗体層を形成し、両端に端
子電極を形成して成るものも製造されているが、
別個の材料より成るベースを必要とする上、抵抗
器の長さ方向において抵抗値を調節することには
変わりはないから、一定の二次元寸法のチツプ型
抵抗器を得ることは難しかつた。 Conventionally, the resistance value of various resistors including fixed resistors is set by the material and length of the resistor arranged between lead wires. However, because the length of this type of conventional resistor can be varied depending on the required resistance value, it is not suitable for constructing chip-type parts that are desired to have fixed two-dimensional dimensions. . Recently, chip-type resistors have also been manufactured in which a resistor layer is formed by printing a resistor paste on a base made of alumina, etc., and terminal electrodes are formed at both ends. ,
It has been difficult to obtain chip resistors with constant two-dimensional dimensions because they require a base of a separate material and the resistance is still adjustable along the length of the resistor.
本発明は、従来の抵抗器の概念と全く異なる概
念によりこの種の問題の解決を図つたもので、逐
次の導体層が交互に他の端面まで達するように導
体層と抵抗体層とを交互に積層し、この積層体の
厚み方向の少なくとも一面に絶縁体層を配置し、
上記両端面に各交互の導体層にそれぞれ接続され
る端子電極を形成したことを特徴とするチツプ型
抵抗器を提供するものである。従来の抵抗器にお
いて抵抗値が長さにより調節されていたのと異な
り、本発明の抵抗器にあつては、抵抗値は１対の
導体層間に配置される抵抗体材料の厚みにより決
定されるから、抵抗器は、同じ二次元寸法で抵抗
体の厚みの調節により種々の抵抗値のものを得る
ことができる。また抵抗体層は薄くできるので小
抵抗値のものも容易に得られる。 The present invention attempts to solve this type of problem by using a concept completely different from that of conventional resistors, in which conductor layers and resistor layers are alternately arranged so that successive conductor layers alternately reach the other end face. and an insulating layer is arranged on at least one surface of the laminate in the thickness direction,
The present invention provides a chip resistor characterized in that terminal electrodes are formed on both end faces to be connected to the respective alternating conductor layers. Unlike conventional resistors in which the resistance value is adjusted by length, in the resistor of the present invention, the resistance value is determined by the thickness of the resistor material disposed between a pair of conductor layers. Therefore, resistors with the same two-dimensional dimensions can have various resistance values by adjusting the thickness of the resistor. Furthermore, since the resistor layer can be made thin, a resistor layer with a low resistance value can be easily obtained.
使用される抵抗体材料は、TiO2−Ta、Nb、
Sb系、BaTiO3−Ta、Nb、Sb系およびFe2O3−
Ta、Nb、Sb系セラミツク抵抗体材料またはこれ
と類似の材料である。Ta、Nb、Sb等の添加剤を
微量加えることにより、抵抗体の抵抗値は種々変
えることができる。導体層としては、Ag−Pd混
合ペースト、Ag100％ペースト等が使用される。
端子電極も同様のペーストを使用できる。また、
チツプの表面をカバーする絶縁体としては、セラ
ミツク、フエライト、ガラスまたは類似の材料を
使用することができる。 The resistor materials used are TiO 2 −Ta, Nb,
Sb-based, BaTiO 3 −Ta, Nb, Sb-based and Fe 2 O 3 −
Ta, Nb, Sb ceramic resistor material or similar materials. By adding trace amounts of additives such as Ta, Nb, and Sb, the resistance value of the resistor can be varied. As the conductor layer, Ag-Pd mixed paste, 100% Ag paste, etc. are used.
A similar paste can also be used for the terminal electrodes. Also,
Ceramic, ferrite, glass or similar materials can be used as the insulator covering the surface of the chip.
以下、図面を参照して本発明を好ましい具体例
について説明する。 Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
第１図は、本発明の積層チツプ型抵抗器の１具
体例の製造工程を示す図で、セラミツク絶縁体片
１上に抵抗体材料層２を形成し（工程）、その
上にAg−Pd混合ペーストまたはAg100％ペース
ト等の導電ペーストを図示のように右端を残して
帯状に塗布して導体層すなわち電極３を形成する
（工程）。次いで、前記の行程で使用したのと
同じ抵抗体材料により抵抗体層２を形成し（工程
）、その上に工程で使用したのと同じ導電ペ
ーストを図示のように左端を残して帯状に塗布し
て他方の電極３を形成する（工程）。次に、上
で使用したのと同じ抵抗体材料により抵抗体層２
を形成し（工程）、その上にセラミツク絶縁体
片１を配置し（工程）、そして最後に、端子電
極４を形成するため、Ag−Pd混合ペーストまた
は100％ペースト等の導電ペーストを端部に塗布
する（工程）。得られた生の積層体は、炉中に
入れ800℃前後の温度で焼成する。なお、積層体
の上下に配される抵抗体材料層は必須のものでは
ないが、部品に適度の厚みをつけるため支持体と
して挿入されている。 FIG. 1 is a diagram showing the manufacturing process of a specific example of the multilayer chip resistor of the present invention, in which a resistor material layer 2 is formed on a ceramic insulator piece 1 (step), and Ag-Pd A conductive paste such as a mixed paste or 100% Ag paste is applied in a strip shape leaving the right end as shown in the figure to form a conductive layer, that is, an electrode 3 (step). Next, a resistor layer 2 is formed using the same resistor material used in the previous step (step), and the same conductive paste used in the step is applied on top of it in a strip shape, leaving the left end as shown. to form the other electrode 3 (step). Next, resistor layer 2 is made of the same resistor material used above.
(step), place the ceramic insulator piece 1 thereon (step), and finally, apply a conductive paste such as Ag-Pd mixed paste or 100% paste to the end to form the terminal electrode 4. (process). The resulting raw laminate is placed in a furnace and fired at a temperature of around 800°C. Although the resistor material layers disposed above and below the laminate are not essential, they are inserted as supports in order to give the component an appropriate thickness.
使用される抵抗体材料は、前述のようにTiO2
−Ta、Nb、Sb系、BaTiO3−Ta、Nb、Sb系、
Fe2O3−Ta、Nb、Sb系セラミツク抵抗体材料ま
たは類似の材料であり、そして添加剤Ta、Nb、
Sbは酸化物の型で、すなわちTa2O5、Nb3O5、
Sb2O3の型で混入される。Ta、Nb、Sb等の添加
剤を微量加えることにより、抵抗体の抵抗は抵下
されるので、抵抗器は添加剤の混入と厚みの調節
で広い範囲で抵抗値を調節できる。 The resistor material used is TiO 2 as mentioned above.
−Ta, Nb, Sb type, BaTiO 3 −Ta, Nb, Sb type,
Fe 2 O 3 - Ta, Nb, Sb ceramic resistor material or similar material, and additives Ta, Nb,
Sb is in oxide type, namely Ta 2 O 5 , Nb 3 O 5 ,
It is mixed in the form of Sb 2 O 3 . By adding small amounts of additives such as Ta, Nb, and Sb, the resistance of the resistor can be lowered, so the resistance value of the resistor can be adjusted over a wide range by adding additives and adjusting the thickness.
積層体をカバーする絶縁体層は、上述のように
セラミツク、フエライトガラスまたは類似の材料
より構成されるが、この絶縁体層は、抵抗器が印
刷回路板上に装着されるときその下側を走るジヤ
ンパ線から絶縁する働きをするものであるから、
片側だけに設けてもよいが、両側に設けた方が焼
成の際チツプが反らないので都合がよい。 The insulator layer covering the laminate, consisting of ceramic, ferrite glass, or similar material as described above, covers the underside of the resistor when it is mounted on a printed circuit board. Because it acts as insulation from the running jumper wire,
Although it may be provided on only one side, it is more convenient to provide it on both sides since the chip will not warp during firing.
なお、上記の製造工程は１個のチツプについて
説明したが、多量生産にあたつては、絶縁体層、
抵抗体層および導体層をすべて印刷によりシート
状の層として順次重ねて形成し、格子状のスリツ
トを入れて焼成し、焼後スリツトによりシートを
割つて積層チツプを形成し、そしてこのチツプに
端子電極を焼き付けることにより個々のチツプ型
抵抗器を製造することができる。 The above manufacturing process was explained for one chip, but for mass production, it is necessary to
The resistor layer and the conductor layer are all printed one after another as sheet-like layers, then fired with lattice-like slits made, and after firing, the sheets are divided by the slits to form a laminated chip, and terminals are attached to this chip. Individual chip resistors can be manufactured by baking the electrodes.
第２図は、完成されたチツプ型抵抗器を、第３
図はこの抵抗器の接続図を示している。これらの
図および第１図の工程から分るように、製造途中
工程に続いてからまでの工程を繰り返えせ
ば電流容量の大きい並列接続した抵抗器が得られ
ることが分ろう。 Figure 2 shows the completed chip resistor in the third
The figure shows the connection diagram of this resistor. As can be seen from these figures and the steps shown in FIG. 1, it can be seen that by repeating the steps in the middle of manufacturing and subsequent steps, a parallel-connected resistor with a large current capacity can be obtained.
以上詳しく説明したように、本発明によれば、
二次元寸法をあまり変えないで広い範囲の抵抗値
を有するチツプ型抵抗器を提供することができ、
電流容量の大きい並列接続された抵抗器を得るこ
とも容易であり、しかも従来のチツプ型抵抗器に
おけるように別の材料より成るベースを必要とし
ない。したがつて、本発明の抵抗器は、各種電子
機器に使用して極めて有用であるとともに、多量
生産にもきわめて適しているから、本発明は電子
および電気産業に利用してその効果はすこぶる大
きい。 As explained in detail above, according to the present invention,
It is possible to provide a chip resistor having a wide range of resistance values without significantly changing the two-dimensional dimensions,
It is also easy to obtain parallel-connected resistors with a large current capacity, and there is no need for a base made of a separate material as in conventional chip resistors. Therefore, the resistor of the present invention is extremely useful when used in various electronic devices, and is also extremely suitable for mass production. .
第１図は本発明の積層チツプ型抵抗器の１具体
例を製造工程において示す平面図、第２図は完成
された抵抗器の断面図、第３図は第２図の抵抗器
の接続図である。
１：絶縁体片、２：抵抗体材料層、３：導体層
または電極、４：端子電極。
Fig. 1 is a plan view showing a specific example of the multilayer chip resistor of the present invention during the manufacturing process, Fig. 2 is a sectional view of the completed resistor, and Fig. 3 is a connection diagram of the resistor shown in Fig. 2. It is. 1: Insulator piece, 2: Resistor material layer, 3: Conductor layer or electrode, 4: Terminal electrode.
Claims (1)
うに導体層と抵抗体層とを交互に積層するととも
に、該積層体の厚み方向の少なくとも一面に絶縁
体を配置し、前記両端面に各交互の導体層にそれ
ぞれ接続される端子電極を形成したことを特徴と
する積層チツプ型抵抗器。1. Conductor layers and resistor layers are alternately laminated so that successive conductive layers alternately reach the other end surfaces, and an insulator is arranged on at least one surface in the thickness direction of the laminate, and each end surface is provided with an insulator. A multilayer chip resistor characterized by forming terminal electrodes connected to alternate conductor layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55181363A JPS57106001A (en) | 1980-12-23 | 1980-12-23 | Laminated chip resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55181363A JPS57106001A (en) | 1980-12-23 | 1980-12-23 | Laminated chip resistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57106001A JPS57106001A (en) | 1982-07-01 |
| JPS636121B2 true JPS636121B2 (en) | 1988-02-08 |
Family
ID=16099407
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55181363A Granted JPS57106001A (en) | 1980-12-23 | 1980-12-23 | Laminated chip resistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57106001A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61274397A (en) * | 1985-05-30 | 1986-12-04 | 株式会社住友金属セラミックス | Low temperature baked ceramic substrate and manufacture thereof |
| JPS62117393A (en) * | 1985-11-16 | 1987-05-28 | 鳴海製陶株式会社 | Low temperature sintered ceramics multilayer circuit substrate |
| JPS62137804A (en) * | 1985-12-12 | 1987-06-20 | 株式会社村田製作所 | Laminated chip thermistor |
| JPS62137805A (en) * | 1985-12-12 | 1987-06-20 | 株式会社村田製作所 | Laminated chip thermistor |
| JPH0547444Y2 (en) * | 1986-10-22 | 1993-12-14 | ||
| NL8800156A (en) * | 1988-01-25 | 1989-08-16 | Philips Nv | CHIP RESISTOR AND METHOD FOR MANUFACTURING A CHIP RESISTOR. |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54156158A (en) * | 1978-05-30 | 1979-12-08 | Matsushita Electric Ind Co Ltd | Method of producing laminated ceramic varister |
-
1980
- 1980-12-23 JP JP55181363A patent/JPS57106001A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54156158A (en) * | 1978-05-30 | 1979-12-08 | Matsushita Electric Ind Co Ltd | Method of producing laminated ceramic varister |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57106001A (en) | 1982-07-01 |
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