JPS635940B2 - - Google Patents
Info
- Publication number
- JPS635940B2 JPS635940B2 JP53161192A JP16119278A JPS635940B2 JP S635940 B2 JPS635940 B2 JP S635940B2 JP 53161192 A JP53161192 A JP 53161192A JP 16119278 A JP16119278 A JP 16119278A JP S635940 B2 JPS635940 B2 JP S635940B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- output
- input signal
- frequency
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000007257 malfunction Effects 0.000 claims description 5
- 230000002265 prevention Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000010355 oscillation Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/14—Demodulator circuits; Receiver circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
【発明の詳細な説明】
本発明は搬送電信装置におけるFSK受信機の
誤動作防止装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for preventing malfunction of an FSK receiver in a carrier telegraph device.
まず従来のFSK受信機を第１図について説明
すると、１は入力信号を増幅する増幅器、２は入
力信号の搬送波帯域だけを通過させる帯域フイル
タ、３は入力信号の振幅を一定にするリミツタ、
４は復調器で、入力信号と後記電圧制御発振器７
の出力との位相または周波数を比較しその差に応
じた誤差信号を生じる位相比較器５と、上記誤差
信号中の高周波成分を除去する低域フイルタ６
と、その出力により発振周波数が制御される電圧
制御発振器７とからなるPLL８と、基準電圧発
生器９と、その基準電圧と上記低域フイルタ６の
出力電圧とを比較する電圧比較器１０とで構成さ
れる。また１１は入力信号中に含まれるノイズに
よつて受信機の出力を断つスケルチ回路である。
そして増幅器１、帯域フイルタ２、リミツタ３、
位相比較器５、低域フイルタ６、電圧比較器１０
およびスケルチ回路１１は入力端子INと出力端
子OUTとの間に順次に接続されるとともに、帯
域フイルタ２とスケルチ回路１１とは直接にも接
続され、また電圧制御発振器７は位相比較器５と
低域フイルタ６との間に、基準電圧発生器９は電
圧比較器１０にそれぞれ接続されている。 First, a conventional FSK receiver will be explained with reference to FIG. 1. 1 is an amplifier that amplifies the input signal, 2 is a band filter that passes only the carrier band of the input signal, 3 is a limiter that keeps the amplitude of the input signal constant,
4 is a demodulator, which receives the input signal and a voltage controlled oscillator 7, which will be described later.
a phase comparator 5 that compares the phase or frequency with the output of the output and generates an error signal according to the difference; and a low-pass filter 6 that removes high frequency components from the error signal.
and a voltage controlled oscillator 7 whose oscillation frequency is controlled by its output, a reference voltage generator 9, and a voltage comparator 10 that compares the reference voltage with the output voltage of the low-pass filter 6. configured. Further, 11 is a squelch circuit that cuts off the output of the receiver due to noise contained in the input signal.
And amplifier 1, band filter 2, limiter 3,
Phase comparator 5, low pass filter 6, voltage comparator 10
The squelch circuit 11 is connected sequentially between the input terminal IN and the output terminal OUT, and the bandpass filter 2 and the squelch circuit 11 are also directly connected, and the voltage controlled oscillator 7 is connected to the phase comparator 5 and A reference voltage generator 9 is connected to a voltage comparator 10 between the range filter 6 and the voltage comparator 10 .
つぎにその動作を説明すると、入力端子INに
入力信号が到来しないときは低域フイルタ６の誤
差信号が０となり電圧制御発振器７は自走周波数
oで発振している。そこで入力端子INに上記o
を中心とする正負の周波数およびhおよびlに
周波数変調された２進化の信号が入力されると増
幅器１で増幅されたのちその周波数h，lを含む
所定の周波数帯域だけが帯域フイルタ２を通り、
さらにリミツタ３で振幅が一定にされて位相比較
器５へ送られる。そしてそのhまたはlと上記o
とが比較されてその誤差信号を生じ低域フイルタ
６へ送られるが上記hおよびlは上記oを中心と
する所定の帯域すなわちキヤプチレンジに含まれ
るようになつておりしたがつて上記誤差信号の周
波数は低いので低域フイルタ６で減衰されずさら
に電圧制御発振器７へ送られてoがhまたはlに
近づくように制御され上記hまたはlと一致して
o′となり、この帰還作用によりPLL８がロツク
されまた上記hまたはlはoを中心とするロツク
レンジにも含まれるのでその状態が保持される。
そして上記低域フイルタ６の出力電圧は入力信号
の周波数hまたはlと電圧制御発振器７の自走周
波数oとの周波数差に比例した電圧となりそれ
が電圧比較器１０で基準電圧発生器９の基準電圧
と比較されるが、この基準電圧は上記電圧制御発
振器７が自走周波数oで発振しているときにお
ける低域フイルタ６の出力電圧と等しいので入力
信号の周波数がhのときはこの基準電圧より低
域フイルタ６の出力電圧のほうが高くなつて電圧
比較器１０の出力はハイレベルＨとなり、また入
力信号の周波数がlのときは基準電圧より低域フ
イルタ６の出力電圧のほうが低くなつて電圧比較
器１０の出力はローレベルＬとなりスケルチ回路
１１を通じて出力端子OUTに復調出力として取
り出せる。 Next, to explain its operation, when no input signal arrives at the input terminal IN, the error signal of the low-pass filter 6 becomes 0, and the voltage-controlled oscillator 7 operates at a free-running frequency.
It oscillates at o. Therefore, the above o is connected to the input terminal IN.
When positive and negative frequencies centering on , and frequency-modulated binary signals at h and l are input, they are amplified by amplifier 1, and only a predetermined frequency band including the frequencies h and l passes through band filter 2. ,
Furthermore, the amplitude is made constant by the limiter 3 and sent to the phase comparator 5. and that h or l and o above
are compared to generate an error signal, which is sent to the low-pass filter 6. Since h and l are included in a predetermined band centered on o, that is, a capture range, the frequency of the error signal is Since o is low, it is not attenuated by the low-pass filter 6, but is further sent to the voltage controlled oscillator 7, where it is controlled so that o approaches h or l, so that it matches h or l above.
o', and this feedback action locks the PLL 8, and since h or l is also included in the lock range centered on o, that state is maintained.
The output voltage of the low-pass filter 6 becomes a voltage proportional to the frequency difference between the frequency h or l of the input signal and the free-running frequency o of the voltage controlled oscillator 7, and this voltage is used as the reference voltage by the voltage comparator 10 and the reference voltage generator 9. This reference voltage is equal to the output voltage of the low-pass filter 6 when the voltage-controlled oscillator 7 is oscillating at the free-running frequency o, so when the input signal frequency is h, this reference voltage The output voltage of the low-pass filter 6 becomes higher, and the output of the voltage comparator 10 becomes a high level H. Also, when the frequency of the input signal is l, the output voltage of the low-pass filter 6 becomes lower than the reference voltage. The output of the voltage comparator 10 becomes a low level L and can be taken out as a demodulated output through the squelch circuit 11 to the output terminal OUT.
しかし入力信号中に不規則なノイズが混入する
と入力信号の周波数成分の外に入力信号の周波数
を中心とするノイズの周波数成分が重畳されるの
で、もしノイズ入力が大きいと位相比較器５に入
力される周波数が不安定となり、その入力周波数
が電圧制御発振器７の自走時の周波数oをはさ
んで上記h側とl側とに交互に変移するとそのた
びに電圧比較器１０の出力がハイレベルＨからロ
ーレベルＬへまたローレベルＬからハイレベルＨ
へ変移してしまうことがある。 However, if irregular noise is mixed into the input signal, the frequency component of the noise centered around the frequency of the input signal will be superimposed on the frequency component of the input signal, so if the noise input is large, it will be input to the phase comparator 5. When the input frequency becomes unstable and the input frequency shifts alternately to the above H side and L side across the free-running frequency o of the voltage controlled oscillator 7, the output of the voltage comparator 10 goes high each time. From level H to low level L and from low level L to high level H
It may shift to.
そこで本発明は電圧制御発振器７の出力を位相
比較器５に帰還するとともに、位相比較器５より
前段において入力信号と混合することにより上記
のような誤動作を簡単に防止できるようにしたも
ので、以下その一実施例を第２図について説明す
ると、第１図におけるスケルチ回路１１がない代
わりに電圧制御発振器７の出力をリミツタ３に帰
還させる帰還回路１２がリミツタ３と電圧制御発
振器７との間に接続されているほかは第１図と変
わらない。なおこの帰還回路１２は、リミツタ３
との接続関係を説明するため第３図に上記リミツ
タ３の一般的な回路とともに示すように、リミツ
タ３内の入力抵抗R1と並列接続されて上記抵抗
R1とともに混合器を構成する入力抵抗R2とその
抵抗R2の入力電圧を決める分割抵抗R3およびR4
とからなつている。 Therefore, the present invention feeds back the output of the voltage controlled oscillator 7 to the phase comparator 5 and mixes it with the input signal at a stage before the phase comparator 5, thereby easily preventing the above-mentioned malfunction. One embodiment of this will be explained below with reference to FIG. 2. Instead of the squelch circuit 11 in FIG. It is the same as in Figure 1 except that it is connected to. Note that this feedback circuit 12 is connected to the limiter 3.
In order to explain the connection relationship with the limiter 3, as shown in FIG. 3 together with the general circuit of the limiter 3 , the input resistor R
The input resistor R 2 , which together with R 1 constitutes the mixer, and the dividing resistors R 3 and R 4 , which determine the input voltage of that resistor R 2
It is made up of.
つづいて動作を説明すると、PLL８が入力信
号の周波数hまたはlにロツクされているときは
入力信号の周波数hまたはlと電圧制御発振器７
の周波数o′とが一致しているが、電圧制御発振
器７の出力は帰還回路１２を通じてリミツタ３に
帰還されるので、入力信号がたとえばhからlに
変移する場合、入力信号hが消失した時点では
位相比較器５に前時点でロツクしていた周波数
o′が帰還信号として帰還回路１２とリミツタ３
とを通じて入力されているので、PLL８は依然
o′のロツクを保ち、したがつてこの帰還信号の
電力を超える新たな入力信号lが到来したときl
がリミツタ３内と帰還回路１２内とに分設された
入力抵抗R1とR2とでなる混合器において電圧制
御発振器７から帰還されている上記o′と合成さ
れてsとなり、それがPLL８の位相比較器５で上
記o′と比較されるのでPLL８はo′をsに近づけ
るように制御するためそれによつてsがl側に引
きもどされ、それを繰り返しながらo′が変移さ
れたlと一致して初めてPLL８がlにロツクす
る。すなわち入力信号の変移時において入力信号
中に上記のようなノイズが混入し上記hをlにま
たはlをhに変移させようとしても、上記ノイズ
は瞬時的なものなので、電圧比較器１０の出力信
号がハイレベルＨからローレベルＬにまたはロー
レベルＬからハイレベルＨに変移するまでに消滅
してしまうため上記出力信号は変移しない。 Continuing with the operation, when the PLL 8 is locked to the frequency h or l of the input signal, the frequency h or l of the input signal and the voltage controlled oscillator 7
However, since the output of the voltage controlled oscillator 7 is fed back to the limiter 3 through the feedback circuit 12, when the input signal changes from h to l, for example, the time when the input signal h disappears. Then, the frequency that was locked to the phase comparator 5 at the previous point.
o′ is the feedback signal and the feedback circuit 12 and limiter 3
Since the input is through
o' remains locked, so that when a new input signal l arrives that exceeds the power of this feedback signal l
is synthesized with the above o′ fed back from the voltage controlled oscillator 7 in a mixer consisting of input resistors R 1 and R 2 that are separated into the limiter 3 and the feedback circuit 12 to form s, which is then output to the PLL 8. Since the phase comparator 5 compares it with the above o', the PLL 8 controls o' to bring it closer to s, thereby pulling s back to the l side, and repeating this, o' is shifted. PLL8 locks to l only when it matches. In other words, even if the above-mentioned noise mixes into the input signal when the input signal changes and an attempt is made to change the above-mentioned h to l or l to h, since the above-mentioned noise is instantaneous, the output of the voltage comparator 10 The output signal does not change because it disappears before the signal changes from high level H to low level L or from low level L to high level H.
なお電圧制御発振器７の出力は常時帰還回路１
２を通じてリミツタ３に帰還されているが、入力
信号の到来前においては、PLL８に自己の発振
出力oが帰還されることとなるので低域フイル
タ６の出力に誤差信号が生じないので電圧制御発
振器７は自走周波数oで発振を続ける。そして
入力信号が初めて到来したときも、入力信号h
またはlは上記混合器によりoと混合されるが、
hまたはlとoとの混合比は上記抵抗R1および
R2の抵抗比によつて前者が大となるためPLL８
のロツクが遅れるのみでPLL８自身の動作には
影響しない。またPLL８がロツクしているとき
は、入力信号と帰還信号の周波数は同じであるが
位相が異なつているので、上記入力信号はリミツ
タ３の入力側と出力側との間に帰還信号との電圧
比によつて決まる位相差が生じるが、入力信号自
身の周波数は変化しないのでPLL８の動作には
なんら影響を与えない。 Note that the output of the voltage controlled oscillator 7 is constantly fed back to the feedback circuit 1.
However, before the input signal arrives, its own oscillation output o is fed back to the PLL 8, so no error signal is generated at the output of the low-pass filter 6, so the voltage controlled oscillator 7 continues to oscillate at free running frequency o. Also, when the input signal arrives for the first time, the input signal h
or l is mixed with o by the above mixer,
The mixing ratio of h or l and o is the above resistance R 1 and
Since the former becomes large depending on the resistance ratio of R 2 , PLL8
This only delays the locking of the PLL 8 and does not affect the operation of the PLL 8 itself. Furthermore, when the PLL 8 is locked, the input signal and the feedback signal have the same frequency but different phases, so the input signal has a voltage between the input side and the output side of the limiter 3 and the feedback signal. A phase difference determined by the ratio occurs, but since the frequency of the input signal itself does not change, it does not affect the operation of the PLL 8 in any way.
また上記の実施例においては、帰還回路１２を
通じて帰還される電圧制御発振器７の出力をリミ
ツタ３に帰還させる場合について述べたが、この
出力は位相比較器５より前段に帰還させればよい
ので、帯域フイルタ２または増幅器１に帰還され
るようにしてもよい。そしていずれに帰還させる
場合でも、それらに帰還回路１２の入力抵抗R2
とともに混合器を構成する入力抵抗R1を上記抵
抗R2と並列に接続されるように設ければよく、
それによつて帰還されるリミツタ３などはそれ自
身の動作が変わることはない。 Furthermore, in the above embodiment, a case has been described in which the output of the voltage controlled oscillator 7, which is fed back through the feedback circuit 12, is fed back to the limiter 3, but since this output may be fed back to a stage before the phase comparator 5, It may be fed back to the bandpass filter 2 or the amplifier 1. No matter where the feedback is made, the input resistance R 2 of the feedback circuit 12 is applied to them.
The input resistor R1 , which constitutes the mixer, may be connected in parallel with the resistor R2 .
As a result, the operation of the limiter 3 and the like that are fed back does not change.
本発明は以上のように電圧制御発振器７の出力
を位相比較器５に帰還するとともに、位相比較器
５より前段において入力信号と混合することによ
り上記のようなノイズによる誤動作を従来一般に
用いられていた構成が複雑なスケルチ回路１１を
用いないで簡単に防止できるすぐれた効果があ
る。 As described above, the present invention feeds back the output of the voltage controlled oscillator 7 to the phase comparator 5, and mixes it with the input signal at a stage before the phase comparator 5, thereby eliminating the malfunction caused by noise as described above, which is not commonly used in the past. This has an excellent effect that can be easily prevented without using the squelch circuit 11 which has a complicated structure.
第１図は従来のFSK受信機のブロツク図、第
２図は本発明の一実施例を示すブロツク図、第３
図はリミツタ３に接続された帰還回路１２の一実
施例の回路図である。
４……復調器、５……位相比較器、７……電圧
制御発振器、８……PLL、１２……帰還回路。
Fig. 1 is a block diagram of a conventional FSK receiver, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is a block diagram of a conventional FSK receiver.
The figure is a circuit diagram of one embodiment of the feedback circuit 12 connected to the limiter 3. 4... Demodulator, 5... Phase comparator, 7... Voltage controlled oscillator, 8... PLL, 12... Feedback circuit.
Claims (1)
PLLの電圧制御発振器の出力を位相比較器に帰
還するとともに、位相比較器より前段において入
力信号と混合することによりノイズによる誤動作
を防止した搬送電信装置におけるFSK受信機の
誤動作防止装置。1 In an FSK receiver using a PLL as a demodulator,
A malfunction prevention device for FSK receivers in carrier telegraph equipment that prevents malfunctions due to noise by feeding back the output of the PLL's voltage controlled oscillator to the phase comparator and mixing it with the input signal at a stage before the phase comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16119278A JPS5590164A (en) | 1978-12-28 | 1978-12-28 | Malfunction preventive unit of fsk receiver of carrier telegraph unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16119278A JPS5590164A (en) | 1978-12-28 | 1978-12-28 | Malfunction preventive unit of fsk receiver of carrier telegraph unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5590164A JPS5590164A (en) | 1980-07-08 |
| JPS635940B2 true JPS635940B2 (en) | 1988-02-05 |
Family
ID=15730327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16119278A Granted JPS5590164A (en) | 1978-12-28 | 1978-12-28 | Malfunction preventive unit of fsk receiver of carrier telegraph unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5590164A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62298256A (en) * | 1986-06-18 | 1987-12-25 | Nec Corp | Receiver for frequency shift modulation signal |
-
1978
- 1978-12-28 JP JP16119278A patent/JPS5590164A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5590164A (en) | 1980-07-08 |
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