JPS6352451B2 - - Google Patents
Info
- Publication number
- JPS6352451B2 JPS6352451B2 JP11032483A JP11032483A JPS6352451B2 JP S6352451 B2 JPS6352451 B2 JP S6352451B2 JP 11032483 A JP11032483 A JP 11032483A JP 11032483 A JP11032483 A JP 11032483A JP S6352451 B2 JPS6352451 B2 JP S6352451B2
- Authority
- JP
- Japan
- Prior art keywords
- exposure
- correction
- pattern
- semiconductor substrate
- head
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012937 correction Methods 0.000 claims description 39
- 239000004065 semiconductor Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 16
- 239000013307 optical fiber Substances 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000010276 construction Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000004904 shortening Methods 0.000 description 4
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012356 Product development Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
- G03F7/70441—Optical proximity correction [OPC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Electron Beam Exposure (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Description
【発明の詳細な説明】
本発明は、縮小投影式露光装置に係り、特に露
光マスクとホトレジストを被覆した半導体基板と
を位置合わせして露光を施こした后、該露光マス
ク上の素子パターン（集積回路等のパターン）で
は、施こされていない配線等の修正パターンを、
露光マスクの再製作、交換といつた処置を講ずる
ことなく自動的に追加露光を可能とすることによ
り、半導体集積回路等の製品製作日程の短縮させ
るとともに装置そのものの効率的運用を画り得る
縮小投影式露光装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reduction projection type exposure apparatus, and in particular, after aligning an exposure mask and a semiconductor substrate covered with photoresist and performing exposure, an element pattern ( (patterns for integrated circuits, etc.), correction patterns for wiring etc. that have not been done,
By making it possible to automatically perform additional exposure without having to take steps such as remanufacturing or replacing the exposure mask, it is possible to shorten the production schedule for products such as semiconductor integrated circuits, and to reduce the size of the equipment itself, which can lead to more efficient operation. The present invention relates to a projection exposure apparatus.
最近の超高集積度半導体デバイス、特にゲート
アレー品種などは、少量多種で、しかも製作日程
を極力短縮せねばならない為、途中工程までは共
通に製作し、要求に応じて配線パターンを変化さ
せることによつて対応している。この場合におい
ても配線パターンの露光マスクの作成、さらに修
正などは、工期短縮を実施する上で重要な要素と
なつている。また、上記以外においても新製品の
試作などの場合においても開発期間の短縮という
ことでは、露光マスクの作成、修正などといつた
ことが重要な要素となつている。 Recent ultra-high-integration semiconductor devices, especially gate array types, are manufactured in small quantities and in many varieties, and the production schedule must be shortened as much as possible. Therefore, intermediate steps are commonly manufactured, and wiring patterns can be changed according to requirements. This is supported by Even in this case, the creation and modification of exposure masks for wiring patterns are important elements in shortening the construction period. In addition to the above, creation and modification of exposure masks are important factors in shortening the development period when prototyping new products.
本発明は、上述の従来の方法、すなわち、品種
毎に、その都度露光マスクを作成、修正するとい
つた工期短縮上の問題点を除去し、少量多品種、
新製品開発等の工期を飛躍的に短縮させることを
可能とするとともに、装置そのものの効率的運用
を可能とし得るパターン修正露光機構を具備する
縮小投影式露光装置を提供することを目的とす
る。 The present invention eliminates the problem of shortening the production time of the conventional method described above, that is, creating and modifying an exposure mask each time for each type of product, and enables high-mix low-volume production.
It is an object of the present invention to provide a reduction projection type exposure apparatus that is equipped with a pattern correction exposure mechanism that can dramatically shorten the construction period for new product development, etc., and also enable efficient operation of the apparatus itself.
本発明は、前述の如く露光マスクに描かれた像
をホトレジストを被覆した半導体基板上に露光転
写する縮小投影式露光装置において、露光マスク
上の素子パターンの露光后、同一露光マスク上の
周辺部にあらかじめ用意された複数の修正用パタ
ーンの組合わせ露光により、所望するパターンホ
トレジストを被覆した半導体基板上に形成し得る
ことを特徴とするパターン修正露光機構を具備す
る縮小投影式露光装置である。 The present invention provides a reduction projection type exposure apparatus that exposes and transfers an image drawn on an exposure mask onto a semiconductor substrate covered with a photoresist as described above, in which after exposure of an element pattern on an exposure mask, a peripheral area on the same exposure mask is transferred. This is a reduction projection type exposure apparatus equipped with a pattern correction exposure mechanism that can form a desired pattern on a semiconductor substrate coated with photoresist by combination exposure of a plurality of correction patterns prepared in advance.
すなわち本発明の特徴は、露光マスクとホトレ
ジストを被覆した半導体基板とを位置合わせして
露光を施こす縮小投影式露光装置において、前記
露光マスクの素子パターンの外側であつてかつ最
大露光可能範囲の内側に配置された複数の異なる
形状を有する修正パターン用アパーチヤーと、修
正パターン露光ヘツドと、前記露光ヘツドに露光
光源から露光光を導びくオプテイカル・フアイバ
ーと、前記修正パターン用アパーチヤーのうちの
選ばれた形状上に前記露光ヘツドを位置させる修
正露光機構とを具備し、前記露光マスク上の素子
パターンを縮小投影露光した後の半導体基板を移
動させることによつて、前記修正パターン用アパ
ーチヤーのうちの選ばれた形状が前記露光ヘツド
により投影露光される位置へ該半導体基板の修正
を要する個所を到達せしめてここで該投影露光を
行つて素子パターンを修正する縮小投影式露光装
置にある。本発明によればあらかじめ予想される
修正形状のアパーチヤーをいくつか用意しておい
て修正露光を行うから修正作業が能率よく行なわ
れる。又、修正用の露光光はオプテイカル・フア
イバーで導びかれるから、先に露光された素子パ
ターンの修正以外の個所に影響を及ぼすことはな
い。又、修正手段は最大露光可能範囲の内側に位
置しているから、素子パターンの投影と同じ精度
のレンズ系を使用することとなり、修正パターン
の正確な縮小投影露光を可能とする。 That is, a feature of the present invention is that in a reduction projection type exposure apparatus that performs exposure by aligning an exposure mask and a semiconductor substrate covered with photoresist, a portion of the exposure mask that is outside the element pattern of the exposure mask and within the maximum exposure range is provided. a correction pattern aperture having a plurality of different shapes disposed inside; a correction pattern exposure head; an optical fiber for guiding exposure light from an exposure light source to the exposure head; and a selected one of the correction pattern aperture. a correction exposure mechanism for positioning the exposure head on the shape of the correction pattern, and by moving the semiconductor substrate after reduction projection exposure of the element pattern on the exposure mask, the correction pattern aperture is moved. The present invention is a reduction projection type exposure apparatus that allows the selected shape to reach a portion of the semiconductor substrate that requires correction to a position where the exposure head is projected and exposes the semiconductor substrate, and then performs the projection exposure to correct the element pattern. According to the present invention, since a number of apertures having a predicted corrected shape are prepared in advance and corrective exposure is performed, the corrective work can be carried out efficiently. Further, since the exposure light for correction is guided by an optical fiber, it does not affect the parts other than the correction of the previously exposed element pattern. Further, since the correction means is located inside the maximum exposure possible range, a lens system having the same precision as that for projection of the element pattern is used, making it possible to perform accurate reduction projection exposure of the correction pattern.
以下、本発明の一実施例を図面を参照して詳細
に説明する。第１図は、本発明の一実施例説明図
である。図中、１は露光マスク、２は素子パター
ン、３は最大露光可能範囲、４は修正用パター
ン、５はパターン修正露光機構、６は修正パター
ン用アパーチヤー、７は修正パターン露光ヘツ
ド、８は駆動用パルスモーター、９はスプリニン
グ・ジヨイント、１０はリード・スクリユー、１
１はオプテイカル・フアイバー、１２は平面鏡を
各々示すものとする。 Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is an explanatory diagram of an embodiment of the present invention. In the figure, 1 is an exposure mask, 2 is an element pattern, 3 is a maximum exposure range, 4 is a correction pattern, 5 is a pattern correction exposure mechanism, 6 is an aperture for correction pattern, 7 is a correction pattern exposure head, and 8 is a drive pulse motor, 9 is the springing joint, 10 is the lead screw, 1
1 represents an optical fiber, and 12 represents a plane mirror.
本縮小投影式露光装置におけるパターン修正を
含む露光手順は、まず通常の縮小投影式露光装置
と同様ホトレジストを被覆した半導体基板を位置
合わせ后、露光マスク１、上の素子パターン２を
該半導体基板上へステツプ・アンド・リピートに
より投影露光を行なう。次に、あらかじめ、露光
マスク１上の最大露光可能範囲３の内側で、しか
も素子パターン２の外側の指定された位置に配置
された複数の修正パターン４の内から適当と思わ
れる修正パターン４を選択し、露光データとして
入力されておけば、そのデータに基き、パターン
修正露光機構５が動作を開始する。まず駆動用パ
ルスモーター８、とスプリング・ジヨイント９、
リード・スクリユ１０により、修正パターン用ア
パーチヤー６及び修正パターン露光ヘツド７が所
定の修正パターン４にセツトされる。次にこのパ
ターンが投影されるべき位置へ該半導体基板の修
正部が移動し、所定の位置（すなわち、修正を要
する位置）に達すると、露光光源からの露光光が
オプテイカル・フアイバー１１と平面鏡１２によ
り露光マスク１上の修正パターン４へ導びかれ、
該修正パターン４を該半導体基板上へ投影露光を
施こすことができる。そして、該半導体基板のス
テツプ・アンド・リピートにより該半導体基板上
の全素子に修正パターンを追加露光を施こすこと
ができる。同様に以上を繰返えすことにより複数
の修正パターンを組合せることにより新らたなパ
ターンを形成されることも可能である。 The exposure procedure including pattern correction in this reduction projection exposure apparatus is as in a normal reduction projection exposure apparatus, after aligning the semiconductor substrate coated with photoresist, the exposure mask 1 and the upper element pattern 2 are placed on the semiconductor substrate. Projection exposure is performed by step-and-repeat. Next, a correction pattern 4 that seems appropriate is selected from among a plurality of correction patterns 4 that are arranged in advance at a specified position inside the maximum exposure range 3 on the exposure mask 1 and outside the element pattern 2. Once selected and input as exposure data, the pattern correction exposure mechanism 5 starts operating based on the data. First, the drive pulse motor 8 and the spring joint 9,
The correction pattern aperture 6 and the correction pattern exposure head 7 are set to a predetermined correction pattern 4 by the lead screw 10. Next, the correction section of the semiconductor substrate moves to a position where this pattern is to be projected, and when it reaches a predetermined position (that is, a position that requires correction), the exposure light from the exposure light source is applied to the optical fiber 11 and the plane mirror 12. guided to the correction pattern 4 on the exposure mask 1,
The modified pattern 4 can be projected and exposed onto the semiconductor substrate. Then, by step-and-repeat the semiconductor substrate, all the elements on the semiconductor substrate can be additionally exposed to a corrected pattern. Similarly, by repeating the above steps, it is also possible to form a new pattern by combining a plurality of modified patterns.
以上の様に本発明により、ゲート・アレー等の
少量多品種品や、開発途上の試作品等の如くその
時々に応じて露光マスクを作成、修正するといつ
た工期短縮上の重大な要素を省略することを可能
とし、これにより、工期を飛躍的に短縮すること
を可能とした。また、露光マスクの交換頻度も減
少する為、装置そのものの効率的運用が飛躍的に
向上せしめることが可能となつた。従つて、本発
明の実用上の効果は、極めて大きい。 As described above, the present invention eliminates important elements for shortening the construction period, such as creating and modifying exposure masks depending on the time, such as for small-volume, high-mix products such as gate arrays, and prototype products in the process of development. This made it possible to dramatically shorten the construction period. Furthermore, since the frequency of exchanging exposure masks is reduced, the efficient operation of the apparatus itself can be dramatically improved. Therefore, the practical effects of the present invention are extremely large.
第１図は、本発明の一実施例の説明図である。
尚、図中、１……露光マスク、２……素子パタ
ーン、３……最大露光可能範囲、４……修正用パ
ターン、５……パターン修正露光機構、６……修
正パターン用アパーチヤー、７……修正パターン
露光ヘツド、８……駆動用パルス・モーター、９
……スプリング・ジヨイント、１０……リード・
スクリユー、１１……オプテイカル・フアイバ
ー、１２……平面鏡、である。
FIG. 1 is an explanatory diagram of an embodiment of the present invention. In the figure, 1...exposure mask, 2...element pattern, 3...maximum exposure range, 4...correction pattern, 5...pattern correction exposure mechanism, 6...aperture for correction pattern, 7... ...Correction pattern exposure head, 8...Driving pulse motor, 9
...Spring joint, 10...Lead
Screw, 11...optical fiber, 12...plane mirror.
Claims (1)
基板とを位置合わせして露光を施こす縮小投影式
露光装置において、前記露光マスクの素子パター
ンの外側であつてかつ最大露光可能範囲の内側に
配置された複数の異なる形状を有する修正パター
ン用アパーチヤーと、修正パターン露光ヘツド
と、前記露光ヘツドに露光光源から露光光を導び
くオプテイカル・フアイバーと、前記修正パター
ン用アパーチヤーのうちの選ばれた形状上に前記
露光ヘツドを位置させる修正露光機構とを具備
し、前記露光マスク上の素子パターンを縮小投影
露光した後の半導体基板を移動させることによつ
て、前記修正パターン用アパーチヤーのうちの選
ばれた形状が前記露光ヘツドにより投影露光され
る位置へ該半導体基板の修正を要する個所を到達
せしめてここで該投影露光を行つて素子パターン
を修正するせしめることを特徴とする縮小投影式
露光装置。1. In a reduction projection exposure apparatus that performs exposure by aligning an exposure mask and a semiconductor substrate coated with photoresist, a plurality of lenses are arranged outside the element pattern of the exposure mask and inside the maximum exposure range. a correction pattern aperture having different shapes; a correction pattern exposure head; an optical fiber for guiding exposure light from an exposure light source to the exposure head; a correction exposure mechanism for positioning a head, and by moving the semiconductor substrate after reduction projection exposure of the element pattern on the exposure mask, the selected shape of the correction pattern aperture is adjusted to the shape of the correction pattern aperture. A reduction projection type exposure apparatus characterized in that a portion of the semiconductor substrate requiring correction is reached to a position to be projected exposed by an exposure head, and the projection exposure is performed there to correct the element pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58110324A JPS601829A (en) | 1983-06-20 | 1983-06-20 | Reduction projection type exposure device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58110324A JPS601829A (en) | 1983-06-20 | 1983-06-20 | Reduction projection type exposure device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS601829A JPS601829A (en) | 1985-01-08 |
| JPS6352451B2 true JPS6352451B2 (en) | 1988-10-19 |
Family
ID=14532834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58110324A Granted JPS601829A (en) | 1983-06-20 | 1983-06-20 | Reduction projection type exposure device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS601829A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55132039A (en) * | 1979-04-02 | 1980-10-14 | Mitsubishi Electric Corp | Forming method for repeated figure |
| JPS55165629A (en) * | 1979-06-11 | 1980-12-24 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS5731136A (en) * | 1980-07-31 | 1982-02-19 | Fujitsu Ltd | Forming method for pattern |
| JPS5877232A (en) * | 1981-11-02 | 1983-05-10 | Nec Corp | Semiconductor device |
-
1983
- 1983-06-20 JP JP58110324A patent/JPS601829A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55132039A (en) * | 1979-04-02 | 1980-10-14 | Mitsubishi Electric Corp | Forming method for repeated figure |
| JPS55165629A (en) * | 1979-06-11 | 1980-12-24 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS5731136A (en) * | 1980-07-31 | 1982-02-19 | Fujitsu Ltd | Forming method for pattern |
| JPS5877232A (en) * | 1981-11-02 | 1983-05-10 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS601829A (en) | 1985-01-08 |
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