JPS6348850A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6348850A JPS6348850A JP19349686A JP19349686A JPS6348850A JP S6348850 A JPS6348850 A JP S6348850A JP 19349686 A JP19349686 A JP 19349686A JP 19349686 A JP19349686 A JP 19349686A JP S6348850 A JPS6348850 A JP S6348850A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- heat sink
- gold
- fixed
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000011347 resin Substances 0.000 claims abstract description 17
- 229920005989 resin Polymers 0.000 claims abstract description 17
- 239000000919 ceramic Substances 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 6
- 239000006023 eutectic alloy Substances 0.000 abstract description 14
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 abstract description 13
- 239000000758 substrate Substances 0.000 abstract description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 6
- 239000010931 gold Substances 0.000 abstract description 6
- 229910052737 gold Inorganic materials 0.000 abstract description 6
- 239000007767 bonding agent Substances 0.000 abstract 1
- 239000000853 adhesive Substances 0.000 description 9
- 230000001070 adhesive effect Effects 0.000 description 9
- 230000017525 heat dissipation Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000005855 radiation Effects 0.000 description 4
- 239000004927 clay Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体素子を搭載する半導体装置の製造方法に
関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device mounting a semiconductor element.
（従来の技術）
半導体素子を搭載するＰＧＡ型半導体装置などでは、近
年、パッケージ材を低コスト化する等の理由からガラス
−エポキシ等の樹脂材料によってパッケージ本体が形成
されている。第５図および第６図は従来のＰＧＡ型半導
体装五を示す断面図で、第５図は積層型、第６図は単層
型である。これらの半導体装置を製造する際、従来は半
導体素子１０を載置するステージ部２８に所要の回路パ
ターン（図示せず）が形成された樹脂基板１４を接着剤
１８で接着して本体パッケージを作成した後、前記ステ
ージ部２８に半導体素子１０を接着し、さらに、ワイヤ
でワイヤポンディングし、キヤ・ノブ２１を前記半導体
素子１０を覆うようにパッケージ本体に気密封止するこ
とにより作成している。(Prior Art) In recent years, in PGA type semiconductor devices and the like on which semiconductor elements are mounted, package bodies have been formed of resin materials such as glass-epoxy in order to reduce the cost of packaging materials. 5 and 6 are cross-sectional views showing conventional PGA type semiconductor devices, in which FIG. 5 is a stacked type and FIG. 6 is a single layer type. When manufacturing these semiconductor devices, conventionally, a main body package is created by bonding a resin substrate 14 on which a required circuit pattern (not shown) is formed to a stage portion 28 on which the semiconductor element 10 is placed using an adhesive 18. After that, the semiconductor element 10 is bonded to the stage portion 28, wire bonding is performed using a wire, and the can knob 21 is hermetically sealed to the package body so as to cover the semiconductor element 10. .
この従来例においては、半導体装置本体を形成する樹脂
基板１４等の耐熱性が低いことと、ステージ部２８と樹
脂基板１４を一体化した後に半導体素子１０をステージ
部２８に接合するので、これら半導体素子１０、ステー
ジ部２８、樹脂基：反１４相互間は接着剤によって接合
されている。In this conventional example, the heat resistance of the resin substrate 14 etc. forming the semiconductor device main body is low, and the semiconductor element 10 is bonded to the stage section 28 after the stage section 28 and the resin substrate 14 are integrated. The element 10, the stage part 28, and the resin base plate 14 are bonded to each other with an adhesive.
一方、最近の半導体素子の高集積化に伴ってタネ５発生
の度合いが高まってきたために、より効率的に熱を放散
する半導体装置が求められており、半導体素子を接合す
るステージ部を銅等の熱伝導性の良い金属製にすると共
に、ステージ部を拡張してヒートシンクとしての機能を
もたせる等の改良がなされている。On the other hand, as the degree of generation of seeds 5 has increased with the recent increase in the degree of integration of semiconductor devices, there is a need for semiconductor devices that dissipate heat more efficiently. Improvements have been made, such as making the stage part of a metal with good thermal conductivity and expanding the stage part to function as a heat sink.
（発明が解決しようとする問題点）
しかしながら、上述した従来の半導体装置では、半導体
素子をヒートシンク上に接着剤で接着しているから接着
の際ガスが発生したり接着剤中の不純物が混入するなど
半導体素子とヒートシンクとの接合に悪影習がある。ま
た、接着剤の熱抵抗が高いため熱放散性において劣ると
いう問題点がある。(Problems to be Solved by the Invention) However, in the conventional semiconductor device described above, since the semiconductor element is bonded onto the heat sink with adhesive, gas is generated during bonding and impurities in the adhesive are mixed in. There is a bad habit of bonding semiconductor elements and heat sinks. Furthermore, since the adhesive has a high thermal resistance, there is a problem that the heat dissipation property is poor.
そこで、本発明は上記問題点を解消すべくなされたもの
であり、その目的とするところは半導体素子をヒートシ
ンクに確実かつ良好に固定でき、半導体装置としての信
頼性を高めることができる半導体装置の製造方法を提供
するにある。Therefore, the present invention has been made to solve the above problems, and its purpose is to provide a semiconductor device that can securely and well fix a semiconductor element to a heat sink and improve the reliability of the semiconductor device. To provide a manufacturing method.
（問題点を解決するための手段） 本発明は上記問題点を解消するため次の構成を備える。(Means for solving problems) The present invention has the following configuration to solve the above problems.
すなわち、半導体素子収納穴を有する樹脂パッケージ本
体と、該パッケージ本体に組み込まれたステージ部兼用
のヒートシンクと、該ヒートシンク上に接合された半導
体素子とを有する半導体装置において、セラミックある
いは金泥からなる前記ヒートシンクに、あらかじめ前記
半導体素子を固定し、次にこのヒートシンクを前記半導
体素子が前記半導体素子収納穴内に位置するようにパッ
ケージ本体に固定することを特徴とする。That is, in a semiconductor device having a resin package body having a semiconductor element storage hole, a heat sink that also serves as a stage part built into the package body, and a semiconductor element bonded onto the heat sink, the heat sink is made of ceramic or gold clay. The method is characterized in that the semiconductor element is fixed in advance, and then the heat sink is fixed to the package body so that the semiconductor element is positioned within the semiconductor element storage hole.
（実施例）
以下、本発明の好適な実施例を添付図面に基づいて詳細
に説明する。(Embodiments) Hereinafter, preferred embodiments of the present invention will be described in detail based on the accompanying drawings.
第１図（ａ）、（ｂ）、（ｃ）は本発明に係る半導体装
置の製造方法を示す説明図である。この説明図で、従来
の半導体装置と共通な部材については同一の番号を付し
ている。FIGS. 1(a), (b), and (c) are explanatory diagrams showing a method for manufacturing a semiconductor device according to the present invention. In this explanatory diagram, the same numbers are given to the members common to the conventional semiconductor device.
本発明においては、先ず、金泥あるいはメタライズパタ
ーンが形成されたセラミックで形成されたヒートシンク
１２上に半導体素子１０を接合ずべく、金−シリコン共
晶合金２２により前記半導体素子１０をヒートシンク１
２上に固定しく第１図（ａ））、次に、樹脂基板１４を
前記ヒートシンク１２上に接着剤１８で接着しく第１図
（ｂ））、さらに、前記半導体素子１０をワイヤ２０に
よって所定回路パターンと接合し、半導体素子１０を覆
うようにキャップ２１を本体に固定すること（第１図（
ｑ））により半導体装置を製造する。In the present invention, first, the semiconductor element 10 is attached to the heat sink 12 using a gold-silicon eutectic alloy 22 in order to bond the semiconductor element 10 onto the heat sink 12 made of gold mud or ceramic on which a metallized pattern is formed.
Next, the resin substrate 14 is bonded onto the heat sink 12 with an adhesive 18 (FIG. 1(b)), and the semiconductor element 10 is fixed in place using the wire 20. The cap 21 is bonded to the circuit pattern and fixed to the main body so as to cover the semiconductor element 10 (see FIG. 1).
A semiconductor device is manufactured by q)).
１６は前記半導体素子１０と所定の回路パターンによっ
て導通される入出力用ピンで、半導体装置本体の上面上
から突出する。Reference numeral 16 denotes an input/output pin that is electrically connected to the semiconductor element 10 through a predetermined circuit pattern, and projects from the top surface of the semiconductor device main body.
３０は樹脂パッケージ本体となる樹脂基板１４に形成し
た半導体素子収納穴である。Reference numeral 30 denotes a semiconductor element storage hole formed in the resin substrate 14 which becomes the main body of the resin package.
前記ヒートシンク１２は半導体素子１０を載置するステ
ージ部を兼ねるものである。以下、ステージ部に限定す
る場合以外はヒートシンクと称する。The heat sink 12 also serves as a stage portion on which the semiconductor element 10 is placed. Hereinafter, it will be referred to as a heat sink unless it is limited to the stage section.
上述したように、本発明では先ずヒートシンク１２と半
導体素子１０を金−シリコン共晶合金によって別体で固
定する工程を採用していることに特徴がある。この金−
シリコン共晶合金は、ステージ部上に形成した金めつき
屓と固定する半導体素子とが接触することにより形成さ
れる。すなわち、金−シリコン共晶合金によって半導体
素子１０を固定する際は、４００℃程度の高温中で接合
するが、本発明の方法では、耐熱性の劣る樹脂基板等と
は別体の状態で接合するので加熱処理については何ら問
題がない。As described above, the present invention is characterized in that first, the heat sink 12 and the semiconductor element 10 are fixed separately using a gold-silicon eutectic alloy. This money-
The silicon eutectic alloy is formed by contacting the gold plating layer formed on the stage portion with the semiconductor element to be fixed. That is, when the semiconductor element 10 is fixed using a gold-silicon eutectic alloy, it is bonded at a high temperature of about 400°C, but in the method of the present invention, it is bonded separately from the resin substrate, etc., which has poor heat resistance. Therefore, there is no problem with heat treatment.
この金−シリコン共晶合金による固定方法によれば、半
導体素子１０が完全にヒートシンク１２に密若でき、良
好な放熱性を発揮することができる。According to this fixing method using the gold-silicon eutectic alloy, the semiconductor element 10 can be completely attached to the heat sink 12, and good heat dissipation can be achieved.
また、ヒートシンク１０をセラミックで形成した場合、
セラミックは金泥にくらべてはるかに熱膨張率が低く、
半導体素子と接合した際、両者の熱膨張の不適合が生じ
ないから、半導体素子に歪みを起こさせることがないと
いう利点がある。また、セラミックは金泥とくらべて、
その強度においても優れ、ヒートシンク （ステージ部
）の機械的強度を大きくすることができ、半導体装置全
体としての信頼性を高めることができる。Moreover, when the heat sink 10 is formed of ceramic,
Ceramic has a much lower coefficient of thermal expansion than gold clay.
When bonded to a semiconductor element, there is no mismatch in thermal expansion between the two, which has the advantage of not causing distortion in the semiconductor element. Also, compared to gold clay, ceramic
It is also excellent in strength, making it possible to increase the mechanical strength of the heat sink (stage portion) and increasing the reliability of the semiconductor device as a whole.
また、半導体素子１０をヒートシンク１２に金−シリコ
ン共晶合金によって固定する際、入出力用ピン１６はヒ
ートシンクとは別体になっているから、入出力用ビン１
６のめっきが加熱処理によって劣化することがなく、は
んだ付は性等に悪影響を及ぼすことがない。Furthermore, when the semiconductor element 10 is fixed to the heat sink 12 using a gold-silicon eutectic alloy, the input/output pins 16 are separate from the heat sink, so the input/output pins 16 are separated from the heat sink.
The plating No. 6 does not deteriorate due to heat treatment, and soldering has no adverse effect on properties.
第１図は樹脂基板１４を積層型にしたものであるが、単
層型の樹脂パッケージにおいても同様である。Although FIG. 1 shows a resin substrate 14 of a laminated type, the same applies to a single layer type resin package.
次に、本発明に係る製造方法によって作成した半導体装
置を説明する。Next, a semiconductor device manufactured by the manufacturing method according to the present invention will be described.
第２図は、半導体素子１０を載置するステージ部２６を
金属あるいはセラミックで形成し、半導体素子１０を金
−シリコン共晶合金によってステージ部２６に固定した
後、ステージ部を抱持するように樹脂基板１４に接着剤
で接着して形成したものである。In FIG. 2, a stage part 26 on which a semiconductor element 10 is placed is formed of metal or ceramic, and after the semiconductor element 10 is fixed to the stage part 26 with a gold-silicon eutectic alloy, the stage part 26 is held. It is formed by adhering to the resin substrate 14 with an adhesive.
第３図は、ヒートシンク１２の放熱性を高めるために、
ステージ部を拡大してヒートシンク１２とし、かつヒー
トシンク１２外方に放熱フィン２４を延設し、ヒートシ
ンク１２の放熱面積の増大を図ったものである。このよ
うにヒートシンク１２の表面積を増大することによって
、半導体素子工０から発生する熱を効率的に放散するこ
とができる。FIG. 3 shows that in order to improve the heat dissipation of the heat sink 12,
The heat sink 12 is formed by enlarging the stage portion, and radiation fins 24 are extended to the outside of the heat sink 12 to increase the heat radiation area of the heat sink 12. By increasing the surface area of the heat sink 12 in this way, the heat generated from the semiconductor device 0 can be efficiently dissipated.
この実施例においても、半導体素子１０とヒートシンク
１２とは金−シリコン共晶合金によって固定する。Also in this embodiment, the semiconductor element 10 and the heat sink 12 are fixed by a gold-silicon eutectic alloy.
第４図はヒートシンク１２を、半導体素子１０を載置す
るステージ部２６とこのステージ部２６から延出する放
熱フィン２４から形成したもので、放熱フィン２４を延
出させることによりヒートシンク１２表面積を増大し、
外部への熱放散性を高めている。この実施例においても
、半４体素子１０を金−シリコン共晶合金によりステー
ジ部２６に固定した後接着剤１８で樹脂基板１４に接合
する。In FIG. 4, the heat sink 12 is formed from a stage part 26 on which the semiconductor element 10 is placed and radiation fins 24 extending from the stage part 26. By extending the radiation fins 24, the surface area of the heat sink 12 is increased. death,
Improves heat dissipation to the outside. In this embodiment as well, the half-quad element 10 is fixed to the stage section 26 using a gold-silicon eutectic alloy and then bonded to the resin substrate 14 using the adhesive 18.
（発明の効果）
本発明によれば、上述したように、セラミックあるいは
金属で形成されたヒートシンクにあらかじめ半導体素子
を金−シリコン共晶合金などによって固定することがで
き、半導体素子のステージ部への接合を従来にくらべて
一層確実にし、半導体装置の信頼性を高めることができ
る。また、ヒートシンクを半導体素子を載置するステー
ジ部と一体に形成したから、効率的に熱を放散する半導
体装置を提供することができる。さらに、ヒートシンク
に半導体素子を接合する際、入力用ピンなどの外部リー
ド端子のめっきが加熱処理によって劣化することがなく
、良好なはんだ付は性が得られる。(Effects of the Invention) According to the present invention, as described above, a semiconductor element can be fixed in advance to a heat sink made of ceramic or metal using a gold-silicon eutectic alloy, etc. The bonding can be made more reliable than in the past, and the reliability of the semiconductor device can be improved. Furthermore, since the heat sink is formed integrally with the stage section on which the semiconductor element is placed, it is possible to provide a semiconductor device that efficiently dissipates heat. Furthermore, when bonding a semiconductor element to a heat sink, the plating of external lead terminals such as input pins does not deteriorate due to heat treatment, and good soldering properties can be obtained.
以上本発明につき好適な実施例を挙げて種々説明したが
、本発明はこの実施例に限定されるものではなく、発明
の精神を逸脱しない範囲内で多くの改変を施゛し得るの
はもちろんのことである。Although the present invention has been variously explained above with reference to preferred embodiments, the present invention is not limited to these embodiments, and it goes without saying that many modifications can be made without departing from the spirit of the invention. It is about.
第１図（ａ＞、（ｂ）、（ｃ）は、本発明に係る半導体
装置の製造方法の実施例を示す断面図、第２図、第３図
、第４図は本発明に係る１：ｄ漬方法によって作成した
半導体装置の断面図、第５図および第６図は従来の半導
体装置を示す断面図である。
１０・・・半導体素子、 １２・・・ヒートシンク、
１４・・・樹脂基板、 １６・・・入出力用ビン
、 １８・・・接着剤、 ２ｏ・・・ワイヤ、 ２１
・・・キャップ、 ２２・・・金−シリコン共晶合金、
２４・・・放熱フィン、２８・・・ステージ部、
３０・・・半導体素子収納穴。1(a), (b), and (c) are cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIGS. 5 and 6 are cross-sectional views showing conventional semiconductor devices. 10... Semiconductor element, 12... Heat sink,
14... Resin board, 16... Input/output bottle, 18... Adhesive, 2o... Wire, 21
... Cap, 22 ... Gold-silicon eutectic alloy,
24... Heat dissipation fin, 28... Stage part,
30...Semiconductor element storage hole.
Claims (1)
該パッケージ本体に組み込まれたステージ部兼用のヒー
トシンクと、該ヒートシンク上に接合された半導体素子
とを有する半導体装置において、セラミックあるいは金
属からなる前記ヒートシンクに、あらかじめ前記半導体
素子を固定し、次にこのヒートシンクを前記半導体素子
が前記半導体素子収納穴内に位置するようにパッケージ
本体に固定することを特徴とする半導体装置の製造方法
。1. A resin package body having a semiconductor element storage hole;
In a semiconductor device having a heat sink that also serves as a stage section built into the package body and a semiconductor element bonded onto the heat sink, the semiconductor element is fixed in advance to the heat sink made of ceramic or metal, and then the semiconductor element is fixed to the heat sink made of ceramic or metal. A method of manufacturing a semiconductor device, comprising fixing a heat sink to a package body so that the semiconductor element is located within the semiconductor element storage hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19349686A JPH0797616B2 (en) | 1986-08-19 | 1986-08-19 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19349686A JPH0797616B2 (en) | 1986-08-19 | 1986-08-19 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6348850A true JPS6348850A (en) | 1988-03-01 |
| JPH0797616B2 JPH0797616B2 (en) | 1995-10-18 |
Family
ID=16309009
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19349686A Expired - Lifetime JPH0797616B2 (en) | 1986-08-19 | 1986-08-19 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0797616B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04234199A (en) * | 1990-09-24 | 1992-08-21 | American Teleph & Telegr Co <Att> | Integrated circuit package and its assembly and cluster |
| GB2304455A (en) * | 1995-08-21 | 1997-03-19 | Kitagawa Ind Co Ltd | A heat radiative ceramic plate |
-
1986
- 1986-08-19 JP JP19349686A patent/JPH0797616B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04234199A (en) * | 1990-09-24 | 1992-08-21 | American Teleph & Telegr Co <Att> | Integrated circuit package and its assembly and cluster |
| GB2304455A (en) * | 1995-08-21 | 1997-03-19 | Kitagawa Ind Co Ltd | A heat radiative ceramic plate |
| GB2304455B (en) * | 1995-08-21 | 1998-07-08 | Kitagawa Ind Co Ltd | A heat radiative electronic component |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0797616B2 (en) | 1995-10-18 |
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