JPS6345848A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6345848A JPS6345848A JP61188539A JP18853986A JPS6345848A JP S6345848 A JPS6345848 A JP S6345848A JP 61188539 A JP61188539 A JP 61188539A JP 18853986 A JP18853986 A JP 18853986A JP S6345848 A JPS6345848 A JP S6345848A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- corner
- thermal
- silicon
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 23
- 239000003990 capacitor Substances 0.000 claims abstract description 22
- 230000003647 oxidation Effects 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- 238000001312 dry etching Methods 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract 1
- 230000002542 deteriorative effect Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 206010011224 Cough Diseases 0.000 description 2
- 206010037660 Pyrexia Diseases 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000037237 body shape Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007127 saponification reaction Methods 0.000 description 1
- 238000009958 sewing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000012498 ultrapure water Substances 0.000 description 1
- 210000000689 upper leg Anatomy 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は半導体ｆｃｉｌｔの製造方法に係り、特に凹凸
を有するシリコン層表面に絶縁性に優れた熱酸化膜を形
成する方法に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor fcilt, and in particular to a method for forming a thermal oxide film with excellent insulation properties on the surface of a silicon layer having unevenness. Regarding.
（従来の技術）
ＭＯ８ダイナンツクメモリ（ｄ ＲＡＭ ）は比例縮小
則に従って素子の微細化、高集債化が進められている。(Prior Art) MO8 dynamic memory (dRAM) is undergoing miniaturization of elements and higher debt collection according to the law of proportional reduction.
ｄＲＡＭの構成ｇ１素であるＭ Ｏ８キヤパシタも例外
ではなく、ゲート酸化膜厚ｔｏｘ及び面積８の縮小が進
んでいる。スケ−りング係数をαとすると、ゲート酸化
膜厚はｔｏＸ／αに面積はＳ／α冨になる。へ１０８キ
ャパシタの容ｔｃｔｉ、誘電率をｇとして、Ｃ−ｇｓ／
ｌｏｗと表わされる九め、比例縮小後の容量Ｃ″は、Ｃ
′−Ｃ／αとなり。The MO8 capacitor, which is the component g1 of dRAM, is no exception, and the gate oxide film thickness tox and area 8 are being reduced. When the scaling coefficient is α, the gate oxide film thickness is toX/α and the area is S/α. 108 Capacitance tcti of capacitor, dielectric constant g, C-gs/
The ninth capacitance C″ after proportional reduction, expressed as low, is C
'-C/α.
ｌ／α に小さくなる。こうしてＭＯ８キャパシタの容
量が小さくなると、アルファ線飛来によるソフトエラー
が起り易くなり、またビット線の容量との比が小さくな
ってセンス余裕が小さくなる結果、誤動作を生じる原因
になりたりする。このため一般にＭＯ８キャパシタの面
積はＳ／α８ではなく、８／αの縮小に止めることが行
われていた。It becomes smaller to l/α. If the capacitance of the MO8 capacitor is reduced in this way, soft errors due to alpha rays are likely to occur, and the ratio with the capacitance of the bit line becomes smaller, resulting in a smaller sensing margin, which may cause malfunctions. For this reason, the area of the MO8 capacitor has generally been reduced by 8/α instead of S/α8.
しかし１世代毎に寸法縮小は進み、信ｙ４件の高いｄＲ
ＡＭを得ることは限界に近づきつつある。However, the dimensions have been reduced with each generation, resulting in a high dR
Obtaining AM is approaching its limits.
ＭＯ８キャパシタの容量を大きくする手段として、誘１
！率の大きい絶縁ｇｌ！、例えばＴａ、Ｏ，膜等を用い
ることも検討されているが、未だ実用になっていない、
を九１０ｎｍ以下の極めて薄い信頼性の高いシリコン酸
化膜の適用が検討されているが、これも極めて高純度の
岬水や薬品を必要とし、まｔ清浄度の高いクリーンルー
ムを必要とする１等の理由で実用になっていない。As a means to increase the capacitance of MO8 capacitor, dielectric
! High rate insulation GL! For example, the use of Ta, O, films, etc. is being considered, but it has not been put into practical use yet.
The application of extremely thin and highly reliable silicon oxide films of 10 nm or less is being considered, but this also requires extremely high purity water and chemicals, and requires a highly clean room. It has not been put into practical use for several reasons.
そｃで現在、ＭＯ８キャパシタの容ｉｔ増大する有力な
方法として、半導体表面に溝を掘り、占有面積を増大さ
せることなく実質的にキャパシタ面積の増大を図る方法
が検討されている。ところがこのようなｒ８ ｔ’、反
応性イオンエツチング（几ＩＢ）のような異方性エツチ
ング法により垂直の側壁をもって形成すると、次のよう
な間Ｕが生じる。即ちこの様な溝（凹部）の上部或いＦ
ｉ底部のコーナーの部分（角部）は曲率半径が極めて小
さく、熱酸化によりゲート膜を形成した時、この角部に
おいて平坦部より酸化膜厚が薄くなる。この現象は次の
ように説明されている。コーナ一部のシリコンを酸化す
ると、既に生成された酸化膜は引き続いて生成された酸
化膜によって押し上げられるため形状の変化全余儀なく
される。この之め酸化が進むとシリコン−酸化膜界面の
酸化膜側では圧縮応力が働き％喧述の角部では応力の集
中が起こる結果、酸化が抑制されるものと考えられる。Therefore, currently, as an effective method for increasing the capacity of MO8 capacitors, a method is being considered in which trenches are dug in the semiconductor surface to substantially increase the capacitor area without increasing the occupied area. However, when r8t' is formed with vertical side walls by an anisotropic etching method such as reactive ion etching (IB), the following gap U occurs. In other words, the upper part of such a groove (recess) or F
The corner portion (corner portion) of the i bottom has an extremely small radius of curvature, and when a gate film is formed by thermal oxidation, the oxide film thickness is thinner at this corner portion than at a flat portion. This phenomenon is explained as follows. When the silicon in a part of the corner is oxidized, the oxide film that has already been produced is pushed up by the oxide film that is subsequently produced, forcing the shape to change completely. As this oxidation progresses, compressive stress acts on the oxide film side of the silicon-oxide film interface, and as a result, stress concentration occurs at the corners of the silicon-oxide film interface, and as a result, oxidation is thought to be suppressed.
このように溝の底部或いは上部の角部で酸化膜厚が平坦
部より薄くなると、この部分は耐圧が低い電界で大きい
リーク電流が流れる原因となる。If the oxide film thickness is thinner at the bottom or upper corner of the groove than at the flat area, a large leakage current will flow in this area due to an electric field with a low withstand voltage.
使用電圧でのリーク電流を十分小さく保り九めにゲート
酸化膜厚を厚くすると、平坦部では厚くなシずぎ、溝を
掘って面積を大きくすることによる容量増大の効果が減
殺されることになる。If the leakage current at the operating voltage is kept sufficiently small and the gate oxide film thickness is made thicker, the effect of increasing the capacitance by increasing the area by digging thick grooves and grooves on flat areas will be reduced. become.
（発明が解決しようとする問題点）
本発明は、四部または凸部を形成した半導体基板表面に
均一な厚さの酸化膜１例えばゲート酸化膜を形成して、
ＭＯ８キャパシタ等の信頼性を向上することができる。(Problems to be Solved by the Invention) The present invention involves forming an oxide film 1, for example, a gate oxide film, with a uniform thickness on the surface of a semiconductor substrate on which four parts or convex parts are formed.
The reliability of MO8 capacitors and the like can be improved.
半導体装置の製造方法を提供することを目的とする。The purpose of the present invention is to provide a method for manufacturing a semiconductor device.
（問題点を解決する念めの手段）
本発明は、凹凸が形成されたシリコン層表面に対し熱酸
化によりｇｔの酸化膜を形成し、この第１の酸化膜の一
部を残してエツチング除去した後。(Preliminary measure to solve the problem) The present invention forms a GT oxide film by thermal oxidation on the surface of a silicon layer on which unevenness is formed, and then removes it by etching, leaving a part of this first oxide film. After.
第１の酸化膜残存状態で熱酸化を行って第１の酸化膜下
のシリコン層表面に第２の酸化膜を形成した後、これら
第１および第２のは化ｍをエツチング除去し、露出した
シリコン層表面に改めて熱酸化によシ第３の酸化膜を形
成する。After thermal oxidation is performed with the first oxide film remaining to form a second oxide film on the surface of the silicon layer under the first oxide film, the first and second oxide films are removed by etching and exposed. A third oxide film is again formed on the surface of the silicon layer by thermal oxidation.
（作用）
シリコンの凹凸コーナ一部を熱酸化すると酸化膜の形状
変化に伴う応力が酸化膜中に発生する。(Function) When a portion of the uneven corner of silicon is thermally oxidized, stress is generated in the oxide film due to a change in the shape of the oxide film.
この応力は形状の急峻な変化があるコーナ一部のシリコ
ン−シリコン酸化膜界面に集中する。このような大きな
応力が存在するとシリコンの酸化反応が抑制されること
が見出されている。このため、コーナーでは酸化膜の膜
厚が薄くなる。This stress is concentrated at the silicon-silicon oxide film interface at a part of the corner where there is a sharp change in shape. It has been found that the presence of such a large stress suppresses the oxidation reaction of silicon. Therefore, the thickness of the oxide film becomes thinner at the corners.
凹凸を有するシリコン表面に対し熱酸化によって＠１の
酸化膜を形成するとコーナ一部では平坦部に比べて膜厚
は薄くなる。この第１Ｏ′）酸化１１！Ｉを少くともそ
の一部を残してエツチング除去すると。When a @1 oxide film is formed by thermal oxidation on a silicon surface having irregularities, the film thickness becomes thinner at some corners than at a flat part. This 1st O′) oxidation 11! When I is removed by etching leaving at least a part of it.
コーナ一部では酸化膜厚は十分薄くなる。或いは下地シ
リコン表面が露出することになる。この状態て熱酸化を
行うと、コーナ一部では平坦部に比べて酸化がより進む
ことになり、第２の酸化膜とシリコン界面はコーナ一部
で丸まり會もつ丸形吠となろ、しかる後に、第１及び第
２の酸化膜をエツチング除去すると、コーナ一部で丸み
を帯び九シリコン表面が得られる。このシリコン表面に
対して所望の鹸化ｍを形成すれば、電界県中の少ない高
品質な酸化膜を得ることができる。The oxide film thickness becomes sufficiently thin at some corners. Alternatively, the underlying silicon surface will be exposed. If thermal oxidation is performed in this state, the oxidation will proceed more in the corners than in the flat parts, and the interface between the second oxide film and the silicon will become rounded in the corners, and then When the first and second oxide films are removed by etching, a silicon surface with rounded corners is obtained. By forming a desired saponification m on the silicon surface, a high quality oxide film with less electric field concentration can be obtained.
（実施９’ｌＪ ’）
第１１１（ａ）〜（−は本発明の一笑施例としてダイナ
きツクランダムアクセスメモリ（ＤＲＡＭ）セルの製造
工橿會示す断面図である。先ず第１図（旬に示すように
、比抵抗ｌＯΩ／ ｃｒｓ梅度のＰ型８ｉＪＩｌ仮（１
）に、フィールド酸化１１１（２） を形成し次後、全
面に０、８ ｔｔ ｍ Ｔａｑ（ＤＣＶ Ｄ酸化Ｉｌｌ
（３） をｊｔｌ墳し％ａ常の写真食刻工程を経てキ
ャパシタ形成領域内に窓を形成する６次に＠１［閾（ｂ
）Ｋ示すようにＣＶＤ酸化膜（３） をマスクとしてｄ
ＲＡＭセルのＭＯ８キャパシタの１＃を内に内直璧を有
する深さ２μｍ程度の溝（４）を形成する。との＊ （
４）は例えばｃｐ、 ＠ ａｉ’、 ＊Ｃ０ｊ４等を主
成分とするガス或いはこ九ＫＨが入つ九ガスを用いたａ
ＩＥ去により形成する。この几ＩＢ工礎のマスクは通常
のフォトレジストではそれ自体もエツチングされて消失
する鴨合があるので。(Embodiment 9'lJ') Nos. 111(a) to 111(-) are cross-sectional views showing a manufacturing process of a dynamic random access memory (DRAM) cell as an example of the present invention. As shown in , P type 8i JIl tentative (1
), field oxide 111(2) is formed, and then 0.8 tt m Taq (DCV D oxidation Ill) is formed on the entire surface.
(3) 6th @1 [threshold (b
) K Using the CVD oxide film (3) as a mask, d
A groove (4) having a depth of about 2 μm and having a vertical wall is formed inside 1# of the MO8 capacitor of the RAM cell. Tono* (
4) is, for example, cp, @ai', *a using a gas whose main component is C0j4, etc., or a gas containing KH.
Formed by IE removal. This mask for IB construction has a sag that is etched away and disappears when using normal photoresist.
Ｒｅ１ｉｃ ＶＤＫ ｚルＳ ｉｏ、 ７８ｉ、Ｎ、
７８１０． ｍ等を用いることが好ましい。Re1ic VDK Z io, 78i, N,
7810. It is preferable to use m, etc.
こ°の後、一旦熱酸化によシ好ましくは２００Ａ以上の
酸化膜を形成し、その後この酸化Ｓを厚さ方向く一部を
残してエツチング除去し酸化膜（５’ ＞’を形成する
（第１図（Ｃ） ）、次に、第１図（ｄ） Ｋ示すよう
Ｋｆｆｉ化膜（５つの存在下でその下のシリコン層表面
に対し熱酸化により酸化１１１１［（６） を形成する
。この熱酸化膜（６）は好ましくＦｉｘｏｏｈ以上とす
る。After this, an oxide film of preferably 200A or more is formed by thermal oxidation, and then this oxide S is etched away leaving a portion in the thickness direction to form an oxide film (5'>'). Then, as shown in FIG. 1(d)K, an oxide 1111 [(6) is formed by thermal oxidation on the surface of the silicon layer underneath in the presence of a Kffi film (5). This thermal oxide film (6) preferably has a thickness of Fixoooh or higher.
＠２図（ａ）〜（ｅ）では１以上の１柱でシリコン基板
ｌのそれぞれ凸部コーナーＡに丸みが形成される様子を
拡大して示している。凸部コーナーＡでは。@2 Figures (a) to (e) show enlarged views of how each convex corner A of the silicon substrate l is rounded by one or more pillars. At the convex corner A.
熱酸化時に応力集中が生じ第２図（ａ）【示すように酸
化膜（５）はこの部分では平坦部に比べて薄くなる。Stress concentration occurs during thermal oxidation, and as shown in FIG. 2(a), the oxide film (5) becomes thinner in this area than in the flat area.
この復号化膜５を一部を残してエツチング除去し酸化１
１ａ５’を形成する（第２１ｉＮ（ｂ））、このとき酸
化膜５′はコーナ一部でとくに薄くなるため、この状１
で熱酸化を行えば第２図（Ｃ）に示すようにコーナ一部
の酸化が促進されシリコン−シリコン酸化膜界面は丸み
を帯びる。凹型コーナーについては酸化膜５を形成し九
段階で丸めが得られることになるが、６凰コーナーの暢
合と同様にしてさらに丸みを増すことができる。This decoding film 5 is etched away leaving only a part and oxidized 1
1a5' is formed (21iN(b)). At this time, the oxide film 5' becomes particularly thin at the corner part, so this condition 1a5' is formed.
If thermal oxidation is performed in this step, oxidation of a portion of the corner will be promoted and the silicon-silicon oxide film interface will be rounded, as shown in FIG. 2(C). As for the concave corners, the oxide film 5 is formed and rounding can be obtained in nine stages, but the roundness can be further increased in the same way as in the case of the six-fold corners.
コ（７）後、第１図（ｅ）に示すようにＣｖＬ）ｌ！！
ｌ！Ｉ！化膜５および熱酸化膜６ｔエツチング除去する
。セして４出したシリコン基板１表面に、第１図（ｆ）
に示すようにｎ″″型層９を形成し、改めて熱酸化を行
ってキャパシタ絶縁膜となる熱酸化Ｍ（第３の酸化膜）
７％−形成し、続いて第１層多結晶シリコン膜を堆積、
パターニングしてキャパシタ電極８Ｍ−形さをもって形
成される０次いで第１図（匂に示すように、キャパシタ
領域に隣接する位置にゲート絶縁膜となる熱酸化膜ｌＯ
を形成し％第２層多結晶シリコン膜の堆積、パターニン
グによりゲート電極１１を形成し、例えばＡｓイオン注
入によりソ＋＋
−ス、ドレインとなるｎｔＪ１層１２ｍ１３に形成して
スイッチングＭＯ８）ランジスタを形成する。After (7), as shown in FIG. 1(e), CvL)l! !
l! I! The oxide film 5 and the thermal oxide film 6t are removed by etching. Figure 1 (f)
As shown in the figure, an n'''' type layer 9 is formed, and thermal oxidation is performed again to form a thermally oxidized M (third oxide film) that becomes a capacitor insulating film.
7% - formed, followed by depositing a first layer polycrystalline silicon film,
The capacitor electrode 8M-shaped is formed by patterning.Then, as shown in FIG.
The gate electrode 11 is formed by depositing and patterning a second layer polycrystalline silicon film, and the ntJ1 layer 12m13 which becomes the source and drain is formed by, for example, As ion implantation to form a switching MO8) transistor. .
この後は図示しないが、全面にＣＶＤ酸化校倉堆攪し、
コンタクト孔を開けてＡＩ配線を形成して、ＤＲＡＭを
完成する。After this, although not shown, CVD oxidation is applied to the entire surface.
Contact holes are opened and AI wiring is formed to complete the DRAM.
この実施例によれば、几ＩＩにより形成されたキャパシ
タ溝のコーナーに効果的に丸みを与えることができ、キ
ャパシタ絶碌膜となる熱電（ヒ膜のコーナ一部での薄寝
化が防止される。またコーナ一部に丸みを与えることに
より、電界集中を緩和することができる。従ってこの実
権例によれば、信頼性の高い高集積化ＤＲＡＭ′を得る
ことができる。According to this embodiment, the corners of the capacitor groove formed by the capacitor II can be effectively rounded, and thinning at some corners of the thermoelectric film, which is an insulating film for the capacitor, can be prevented. Further, by rounding a portion of the corner, electric field concentration can be alleviated.Therefore, according to this practical example, a highly reliable and highly integrated DRAM' can be obtained.
本発明は上記実権例に限られるものではない。The present invention is not limited to the above-mentioned examples.
例えば以上では専ら溝掘り型Ｄ ＲＡ Ｍについて説明
し念が、ＤＲＡＭＫ限らず凹凸’ｒＶするシリコン表面
に熱酸化膜を形成する工程を必要とするあらゆる零子に
本発明を適用することができる。For example, although the above description has focused exclusively on trench type DRAMs, the present invention can be applied not only to DRAMKs but also to any device that requires a step of forming a thermal oxide film on an uneven silicon surface.
本発明によれば、凹部ま之は凸部等の車体形状を有する
半導体不板表面に均一な膜厚のゲート酸化膜全形成する
ことができる。これは本発明の条件に従えば、成長する
酸化膜中に残存する応力の膜厚方向の積分値のばらつき
（即ち、凹部や凸部の平坦部と角部での応力の膜厚方向
の積分値の差）が１０係程度以下に呆几れ、この結果［
［；力集中が効果的に防止されるためである。従ってこ
のゲート酸化層を用いて例えば容量が大きく且つリーク
遁流の小さいＭＯＳキャパシタを形成することができる
。ま几このへ１０８キャパシタを用いて１高集積化Ｄ
Ｈ，Ａ Ｍ ｔｌ−Ｗ４成すれば、ＤＲＡＭのソフトエ
ラーによる誤動作の確率を下げ、ま之センスアンプの動
作余裕を大きいものとすることができる。According to the present invention, a gate oxide film having a uniform thickness can be formed entirely on the surface of a semiconductor substrate having a vehicle body shape such as a convex portion or the like. According to the conditions of the present invention, this is due to the variation in the integral value of the stress remaining in the growing oxide film in the thickness direction (i.e., the variation in the integral value of the stress in the thickness direction at the flat parts and corners of concave and convex parts). The difference in values) was reduced to less than a factor of 10, and as a result [
[; This is because force concentration is effectively prevented. Therefore, using this gate oxide layer, for example, a MOS capacitor with a large capacitance and a small leakage current can be formed. 1 high integration using 108 capacitors
If H, A M tl-W4 is implemented, the probability of malfunction due to soft errors in the DRAM can be lowered, and the operating margin of the sense amplifier can be increased.
第１０→−俤は本発明５０几ＡＭに６厘用し九−実施的
の製造工程を示す断面口ｓＬｒ！２図８は４１図におけ
るコーナーＡ部の変化全拡大して示す説明図である。
１・・・シリコン縫仮、２・・・フィールド絶縁膜、３
・ＣＶ Ｄ ｃ１１化＆−４・” Ｊ’を５＃ ５’
”・熱ｔｋＲ（Ｆ−麟（”ｆＧｌの酸化膜）、６・・・
熱咳化腿（第２のは１ヒ膜）、７・・・熱賃化膜（４３
の設化膜、キャパシタ絶縁膜）、８・・・キャパシタ電
極、９・”ｎ″″ｍ層、１０・・・熱酸化膜（ゲート絶
縁膜）、１１・・・ゲート電極、１２゜＋
１３・−ｎ 型層。
代理人 弁理士 則 近 憲 重
量 竹 花 喜久男
第 １ 図
第 ３ 図The 10th→-5 is the cross-sectional opening sLr showing the practical manufacturing process for 6 times the 50-liter AM of the present invention! 2. FIG. 8 is an explanatory diagram showing the change in the corner A section in FIG. 41 in an enlarged manner. 1...Silicon sewing temporary, 2...Field insulating film, 3
・CV D c11 conversion &-4・"J' to 5# 5'
"・Heat tkR (F-Rin ("fGl oxide film), 6...
fever cough thigh (second one is 1hi membrane), 7... fever cough membrane (43
formation film, capacitor insulating film), 8... Capacitor electrode, 9・"n""m layer, 10... Thermal oxide film (gate insulating film), 11... Gate electrode, 12° + 13・-n type layer. Agent Patent attorney Noriyuki Chika Weight Kikuo Takehana Figure 1 Figure 3
Claims (5)
り、一旦シリコン表面に対し熱酸化により第１の酸化膜
を形成する工程と、この第１の酸化膜を少くとも一部を
残し、エッチング除去する工程と、前記第１の酸化膜が
存在する状態でその下のシリコン層表面に熱酸化により
第２の酸化膜を形成する工程と、前記第１および第２の
酸化膜をエッチング除去して露出したシリコン層表面に
所望の第３の酸化膜を形成する工程とを備えたことを特
徴とする半導体装置の製造方法。(1) When oxidizing a silicon surface having an uneven shape, there is a step of first forming a first oxide film on the silicon surface by thermal oxidation, and etching away this first oxide film, leaving at least a part of it. a step of forming a second oxide film by thermal oxidation on the surface of the underlying silicon layer in the presence of the first oxide film; and etching away and exposing the first and second oxide films. forming a desired third oxide film on the surface of the silicon layer.
チング法により形成されたものである特許請求の範囲第
１項記載の半導体装置の製造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein the unevenness on the surface of the silicon layer is formed by an anisotropic dry etching method.
セルのキャパシタ領域に形成された溝であり、前記第３
の酸化膜はキャパシタ絶縁膜である特許請求の範囲第１
項記載の半導体装置の製造方法。(3) The recess on the surface of the silicon layer is a dynamic RAM.
a groove formed in the capacitor region of the cell;
Claim 1, wherein the oxide film is a capacitor insulating film.
A method for manufacturing a semiconductor device according to section 1.
形成され、前記第２の酸化膜は１００Å以上の厚さをも
って形成される特許請求の範囲第１項記載の半導体装置
の製造方法。(4) The method of manufacturing a semiconductor device according to claim 1, wherein the first oxide film is formed to have a thickness of 200 Å or more, and the second oxide film is formed to have a thickness of 100 Å or more.
さをもって形成される特許請求の範囲第１項記載の半導
体装置の製造方法。(5) The method of manufacturing a semiconductor device according to claim 1, wherein the third oxide film is formed to have a thickness of 50 Å or more and 500 Å or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61188539A JPS6345848A (en) | 1986-08-13 | 1986-08-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61188539A JPS6345848A (en) | 1986-08-13 | 1986-08-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6345848A true JPS6345848A (en) | 1988-02-26 |
Family
ID=16225474
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61188539A Pending JPS6345848A (en) | 1986-08-13 | 1986-08-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6345848A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5481127A (en) * | 1992-11-04 | 1996-01-02 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having a capacitor |
| US5541425A (en) * | 1994-01-20 | 1996-07-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having trench structure |
-
1986
- 1986-08-13 JP JP61188539A patent/JPS6345848A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5481127A (en) * | 1992-11-04 | 1996-01-02 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having a capacitor |
| US5633188A (en) * | 1992-11-04 | 1997-05-27 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor memory device having a capacitor |
| US5541425A (en) * | 1994-01-20 | 1996-07-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having trench structure |
| US5795792A (en) * | 1994-01-20 | 1998-08-18 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device having a trench structure |
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