JPS6343897B2 - - Google Patents
Info
- Publication number
- JPS6343897B2 JPS6343897B2 JP54165944A JP16594479A JPS6343897B2 JP S6343897 B2 JPS6343897 B2 JP S6343897B2 JP 54165944 A JP54165944 A JP 54165944A JP 16594479 A JP16594479 A JP 16594479A JP S6343897 B2 JPS6343897 B2 JP S6343897B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor device
- leads
- bonding
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 73
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract 4
- 238000010276 construction Methods 0.000 abstract 2
- 238000005452 bending Methods 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910000531 Co alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- KGWWEXORQXHJJQ-UHFFFAOYSA-N [Fe].[Co].[Ni] Chemical compound [Fe].[Co].[Ni] KGWWEXORQXHJJQ-UHFFFAOYSA-N 0.000 description 1
- PCEXQRKSUSSDFT-UHFFFAOYSA-N [Mn].[Mo] Chemical compound [Mn].[Mo] PCEXQRKSUSSDFT-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- HEPLMSKRHVKCAQ-UHFFFAOYSA-N lead nickel Chemical compound [Ni].[Pb] HEPLMSKRHVKCAQ-UHFFFAOYSA-N 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/79—Apparatus for Tape Automated Bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置に係り、特にギヤングボン
デイングされてなる半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device formed by gigantic bonding.
これまでのフイルムキヤリヤー型半導体装置で
は、半導体装置素子とフイルムキヤリヤーリード
との接続（インナーリードボンデイング）を終了
した後それぞれ個別の半導体装置として、ハイブ
リツドIC用の回路基板やコンピユーター用の配
線基板上に接続（アウターリードボンデイング）
していた。これまでのアウターリードボンデイン
グは半導体装置のリード数が40ピン程度と比較的
少なかつた為、隣接同士のリード間の短絡は余り
問題とはならなかつた。しかしながら、50ピンを
越える程度となると、隣接リード間隔が狭くな
り、アウターリードボンデイング時に隣接リード
や、隣接端子部と短絡を起す等の欠点が発生し
た。 In conventional film carrier type semiconductor devices, after the connection between the semiconductor device element and the film carrier lead (inner lead bonding) is completed, each semiconductor device is sold as an individual semiconductor device, such as a circuit board for a hybrid IC or a wiring board for a computer. Connect to the top (outer lead bonding)
Was. In conventional outer lead bonding, the number of leads in a semiconductor device was relatively small at about 40 pins, so short circuits between adjacent leads did not pose much of a problem. However, when the number of pins exceeds 50, the distance between adjacent leads becomes narrow, resulting in short circuits with adjacent leads or adjacent terminals during outer lead bonding.
本発明の目的はこのような欠点を除去した半導
体装置を提供することにある。 An object of the present invention is to provide a semiconductor device that eliminates such drawbacks.
フイルムキヤリヤー半導体装置をハイブリツド
ICとして使用する場合には、あらかじめメタラ
イズ配線された配線端子部にフイルムキヤリヤー
のリード部を曲げ成形及び切断加工して、熱圧着
法や超音波溶接法やペースト接着法で接続し、半
導体装置の搭載をしていた。 Hybrid film carrier semiconductor device
When used as an IC, the lead part of the film carrier is bent, formed and cut onto the wiring terminal part which has been pre-metallized, and connected by thermocompression bonding, ultrasonic welding or paste bonding, and the semiconductor device It was equipped with.
このハイブリツドIC用配線基板は、動作特性
向上の為と、価格低下を目的として高密度実装が
極めて重要なこととなつている。この為、配線端
子部は通常数100ミクロンピツチで、配線端子巾
は約200ミクロン程度となつているが、半導体装
置のリード数が、50ピンを越える程度となると、
このピツチや配線端子巾が小さくなつて隣接配線
端子間隔も、100ミクロンよりも小さくなる。更
に端子数が増えると、この傾向がひどくなり、半
導体装置のリードを接続した際容易に隣接リード
同士又はリードと隣接端子の短絡が発生しやすく
なる。 High-density packaging is extremely important for wiring boards for hybrid ICs in order to improve operating characteristics and lower prices. For this reason, the wiring terminal section is usually several hundred microns pitch, and the wiring terminal width is about 200 microns, but when the number of leads of a semiconductor device exceeds 50 pins,
As the pitch and wiring terminal width become smaller, the distance between adjacent wiring terminals also becomes smaller than 100 microns. Furthermore, as the number of terminals increases, this tendency becomes more severe, and when the leads of a semiconductor device are connected, short circuits easily occur between adjacent leads or between a lead and an adjacent terminal.
この短絡不良の発生は、半導体装置のリード曲
げ成形や、アウターリードボンデイング時に該リ
ードに付加される応力でリードが曲げられたり、
あるいは内部歪が蓄えられてアウターリードボン
デイング治具が除かれた後に、リード変形を生じ
る為に起る。 This short-circuit failure occurs when the leads are bent due to stress applied to the leads during lead bending of semiconductor devices or during outer lead bonding.
Alternatively, this may occur because internal strain is accumulated and leads are deformed after the outer lead bonding jig is removed.
従来のフイルムキヤリヤー半導体装置で、この
短絡不良が発生するのは、以上の理由丈ではな
く、フイルムキヤリヤーから半導体装置のリード
を切断した際、この切断リード群の切断端部が、
片持ちはり状の自由端となつているからである。 The reason why this short-circuit failure occurs in conventional film carrier semiconductor devices is not due to the length, but when the leads of the semiconductor device are cut from the film carrier, the cut ends of the group of cut leads are
This is because it has a cantilevered free end.
本発明は、これらの発生原因のうち、後者の原
因を除去すれば、前述の短絡不良発生が無くなる
ことを利用したものである。 The present invention takes advantage of the fact that if the latter of these causes is removed, the aforementioned short-circuit failures will no longer occur.
本発明は例えば、半導体素子の各辺毎に、半導
体素子から突出しているリード群を各辺毎に該リ
ード群の端部で支持していることを特徴とする半
導体装置であり、特に絶縁支持部を有するリード
部の部分、又は絶縁支持部と半導体素子との間の
リード部の部分で、アウターリードボンデイング
されている半導体装置である。 The present invention is, for example, a semiconductor device characterized in that, on each side of a semiconductor element, a group of leads protruding from the semiconductor element is supported at the end of the group of leads on each side. This is a semiconductor device in which outer lead bonding is performed at a portion of a lead portion having a portion or a portion of a lead portion between an insulating support portion and a semiconductor element.
即ち本発明によれば、フイルムキヤリヤーを構
成している絶縁フイルムと半導体素子から突出し
ているリード群とを同時に一体切断し、リード先
端部に切断されたリード群と、絶縁フイルムが接
着した状態即ち、リード群が半導体素子と絶縁フ
イルムの両持はり状態とし、リード切断端部が、
自由端とならないようにし、その後に、ハイブリ
ツドIC等の配線基板の配線端子部に該絶縁フイ
ルム部又は、該絶縁フイルム部よりも内側のリー
ド部でアウターリードボンデイングすることによ
り、短絡不良を無くした半導体装置を得ることが
できる。 That is, according to the present invention, the insulating film constituting the film carrier and the lead group protruding from the semiconductor element are simultaneously cut into one piece, and the cut lead group and the insulating film are bonded to the tip of the lead. That is, the lead group is in a state where the semiconductor element and the insulating film are supported on both sides, and the cut end of the lead is
Short-circuit defects are eliminated by ensuring that the leads do not become free ends, and then bonding the outer leads to the wiring terminals of the wiring board of hybrid ICs, etc. with the insulating film part or the lead part inside the insulating film part. A semiconductor device can be obtained.
以下図面を用いて説明する。 This will be explained below using the drawings.
第１図は絶縁フイルム１上に形成されたリード
２に半導体素子３がインナーリードボンデイング
されたフイルムキヤリヤー半導体装置の平面図で
ある。絶縁フイルム１は、100ミクロン厚のポリ
イミドシートで、送り孔４と半導体素子を載置す
る開孔５を有している。 FIG. 1 is a plan view of a film carrier semiconductor device in which a semiconductor element 3 is bonded to leads 2 formed on an insulating film 1 by inner lead bonding. The insulating film 1 is a polyimide sheet with a thickness of 100 microns, and has a feed hole 4 and an opening 5 for placing a semiconductor element.
第２図は、フイルムキヤリヤー半導体装置から
ハイブリツドIC基板に載置する為に切断した個
片の半導体装置の平面図で、従来から行われてい
る形態である。従来は、このようにリード２が半
導体素子３から片持ちはり状の形態で使用されて
いるのでリード２の端部が自由端となつて、外力
が負荷されると容易に位置ずれを起していた。こ
の外力としては、切断時又は切断後の取扱い時あ
るいはアウターリードボンデイング時にかかるも
のが主なものであるが、いずれの時にもリード間
隔が変動して短絡の原因となつていた。 FIG. 2 is a plan view of individual semiconductor devices cut from a film carrier semiconductor device in order to be placed on a hybrid IC board, which is a conventional method. Conventionally, the leads 2 are used in the form of a cantilever from the semiconductor element 3, so the ends of the leads 2 become free ends, which easily cause misalignment when an external force is applied. was. This external force is mainly applied during cutting, handling after cutting, or outer lead bonding, but in any case, the lead spacing fluctuates, causing short circuits.
第３図は、ポリイミドフイルム枠６を残すよう
にフイルムキヤリヤー半導体装置から個片の半導
体装置を切り取つたものでリード２は枠６に支え
られている為に、リード間隔が変動することはな
い。 Figure 3 shows an individual semiconductor device cut out from a film carrier semiconductor device leaving the polyimide film frame 6. Since the leads 2 are supported by the frame 6, the lead spacing does not change. .
第４図は、第３図半導体装置の枠６の四角を切
除した半導体装置の平面図である。第４図におい
て支持枠片７が残つている為、リード２は互いの
リード間隔が変動することはない。 FIG. 4 is a plan view of the semiconductor device shown in FIG. 3, with a square section of the frame 6 removed. In FIG. 4, since the support frame piece 7 remains, the distance between the leads 2 does not change.
第５図は、第４図の半導体装置の断面図であ
る。 FIG. 5 is a cross-sectional view of the semiconductor device of FIG. 4.
第６図は、第５図の半導体装置の支持枠片７を
リード２に沿つて、180゜回転させて、リード２を
「コ」の字状にまげた半導体装置の断面図である。 FIG. 6 is a cross-sectional view of the semiconductor device in which the support frame piece 7 of the semiconductor device shown in FIG. 5 is rotated 180 degrees along the leads 2 and the leads 2 are bent into a U-shape.
第７図は、アルミナ配線基板８の配線端子９に
第６図の半導体装置を熱圧着ボンデイングした状
態を示す断面図である。半導体素子３は、銀ペー
スト１０を用いてあらかじめ基板８にダイボンド
した。リード２は40ミクロン厚の銅で、表面に錫
メツキが１ミクロン施こしてあるので、金メタラ
イズが0.5ミクロン施こしてある配線端子９には、
300℃程度の熱圧着で容易にアウターリード・ボ
ンデイング出来た。このように容易にアウターリ
ード・ボンデイングが出来たのは、第４図で明ら
かなように、リード２の先端が支持枠片７がある
ため互いに接触することなく、曲げ加工や、アウ
ターリード・ボンデイング出来る状態にあるから
である。又、第３図の如き枠６のある半導体装置
では、第６図あるいは後述の第８図、第９図の如
き曲げ加工が出来ないので、リードの曲げ加工方
向が揃つているリード群別にリード支持片が必要
となる。 FIG. 7 is a cross-sectional view showing the semiconductor device shown in FIG. 6 bonded to the wiring terminals 9 of the alumina wiring board 8 by thermocompression bonding. The semiconductor element 3 was die-bonded to the substrate 8 in advance using a silver paste 10. The lead 2 is made of copper with a thickness of 40 microns and has a tin plating of 1 micron on the surface, so the wiring terminal 9 has a gold metallization of 0.5 micron.
Outer lead bonding was easily achieved by thermocompression at around 300°C. The reason why outer lead bonding was easily possible in this way is that, as is clear from FIG. This is because it is possible. In addition, in a semiconductor device having a frame 6 as shown in FIG. 3, bending as shown in FIG. 6 or FIGS. 8 and 9 described later cannot be performed, so the leads are separated into groups whose bending directions are the same. A support piece is required.
第８図、第９図は、リード支持片１１，１２
が、半導体素子３に対して反対側に存在する半導
体装置の断面図である。これらの半導体装置のリ
ードは、支持片１１，１２がリードの導出方向毎
に分かれて、リード群を支持しているので、容易
に第８図、第９図の如くに、曲げ加工が出来た。 8 and 9 show lead support pieces 11 and 12.
is a cross-sectional view of a semiconductor device located on the opposite side to the semiconductor element 3. FIG. The leads of these semiconductor devices can be easily bent as shown in FIGS. 8 and 9 because the support pieces 11 and 12 are separated for each direction in which the leads are led out and support the group of leads. .
第９図のリード２′は半導体装置の電極に対応
した突起端子を有する表面金メツキ処理した70ミ
クロン厚ニツケルリードである。 The lead 2' in FIG. 9 is a 70 micron thick nickel lead whose surface is gold-plated and has protruding terminals corresponding to the electrodes of a semiconductor device.
第１０図は、配線ピツチが100ミクロン、端子
巾が70ミクロン、端子間が30ミクロンの金配線を
有するハイブリツドIC基板に第８図の半導体装
置を、樹脂ダイボンドした後、熱圧着アウターリ
ード・ボンデイングした本発明の実施例半導体装
置を説明する断面図である。 Figure 10 shows the semiconductor device shown in Figure 8 being resin die-bonded to a hybrid IC board that has gold wiring with a wiring pitch of 100 microns, a terminal width of 70 microns, and a distance between terminals of 30 microns, followed by thermocompression outer lead bonding. FIG. 2 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.
第８図の半導体装置は52ピンのリード数を有す
るもので、リード巾は50ミクロン、リードピツチ
を100ミクロンにしたものであるが、ポリイミド
支持片１１によつて、リードピツチのずれは殆ん
ど起つていなく、半導体装置素子３のダイボンド
時にも個々のリード間隔の変動は数ミクロンで、
このような状態での基板端子と、リードの位置合
わせは極めて容易であつた。又、アウターリー
ド・ボンデイングは支持片１１より内側のリード
部のみでの金―金熱圧着とし、極めて安定した短
絡不良発生のないアウターリードボンデイングの
出来た半導体装置が得られた。第１０図に於て、
１３はエポキシペースト、１４はアウターリード
ボンデイング部を示す。 The semiconductor device shown in FIG. 8 has 52 leads, the lead width is 50 microns, and the lead pitch is 100 microns. However, the polyimide support piece 11 prevents most of the lead pitch from shifting. Even during die bonding of the semiconductor device element 3, the individual lead spacing varies by a few microns.
It was extremely easy to align the board terminals and the leads in this state. Further, the outer lead bonding was carried out by thermocompression bonding of only the lead portions inside the support piece 11, and a semiconductor device was obtained in which the outer lead bonding was extremely stable and did not cause short-circuit defects. In Figure 10,
13 is an epoxy paste, and 14 is an outer lead bonding part.
第１１図はガラスエポキシ基板１５に設けられ
た、金メツキ銅配線端子１６を有するIC基板１
５に錫鉛半田１７を用いて、ダイボンド及びアウ
ターリードボンデイングをした本発明の他の実施
例半導体装置断面図である。 FIG. 11 shows an IC board 1 having gold-plated copper wiring terminals 16 provided on a glass epoxy board 15.
5 is a sectional view of a semiconductor device according to another embodiment of the present invention in which die bonding and outer lead bonding are performed using tin-lead solder 17.
第１１図例は、ダイボンド及びアウターリード
ボンデイングが220℃程度の温度で、一回の熱加
工プロセスで出来たもので、第１０図例と同様、
極めて容易に短絡不良の無い半導体装置が得られ
た。 In the example in Figure 11, die bonding and outer lead bonding were made in a single heat processing process at a temperature of about 220°C, and as in the example in Figure 10,
A semiconductor device free from short-circuit defects was extremely easily obtained.
第１２図は、セラミツクICパツケージに封入
した本発明のさらに他の実施例半導体装置断面図
である。 FIG. 12 is a sectional view of a semiconductor device according to still another embodiment of the present invention sealed in a ceramic IC package.
同図において、１８はアルミナセラミツクベー
ス、１９はモリブデンマンガンメタライズ配線で
端子部にはニツケルメツキ、金メツキを施こした
もの、２０はセラミツクリング、２１はガラス封
止部、２２は封止セラミツクキヤツプ、２３は鉄
ニツケルコバルト合金リード、２４は銀ペースト
を示している。 In the figure, 18 is an alumina ceramic base, 19 is molybdenum manganese metallized wiring with nickel plating and gold plating on the terminal part, 20 is a ceramic ring, 21 is a glass sealing part, 22 is a sealing ceramic cap, 23 indicates an iron-nickel-cobalt alloy lead, and 24 indicates a silver paste.
本半導体装置は、第４図半導体装置をリード成
形することなく、超音波熱圧着ボンデイングした
もので、アウターリードボンデイング時に、リー
ド位置ずれを生じることなく製造することが出来
た。 This semiconductor device was obtained by performing ultrasonic thermocompression bonding on the semiconductor device shown in FIG. 4 without forming leads, and was able to be manufactured without causing lead positional deviation during outer lead bonding.
本発明の別の実施例を示すと、フイルムキヤリ
ヤー半導体装置を、第１３図に示すように破線部
２５に沿つて、フイルムキヤリヤーのフイルム部
を切除すると、第１４図の如き中間支持片２６と
リード先端支持片２７を有する半導体装置を得て
該支持片２６と２７の間でアウターリードボンデ
イングすれば、更に安定した半導体装置が得られ
た。 In another embodiment of the present invention, when a film carrier semiconductor device is cut out along a broken line 25 as shown in FIG. 13, an intermediate support piece as shown in FIG. 14 is formed. By obtaining a semiconductor device having a lead tip support piece 26 and a lead tip support piece 27 and performing outer lead bonding between the support pieces 26 and 27, a more stable semiconductor device was obtained.
第１５図は本発明の半導体装置のさらに別の実
施例を示す平面図で、20ピンのリードを有する集
積回路３０で、絶縁支持枠２８とリード群２の端
部が絶縁支持片で保持されている。このようにリ
ード群が多ピンになればなる程、リード間隔や、
リード巾が小さくなるので、リードの曲りは重大
になることはいうまでもないことである。 FIG. 15 is a plan view showing still another embodiment of the semiconductor device of the present invention, which is an integrated circuit 30 having 20 pin leads, in which the insulating support frame 28 and the ends of the lead group 2 are held by insulating support pieces. ing. In this way, the more pins a lead group has, the more the lead spacing,
Needless to say, as the lead width becomes smaller, bending of the lead becomes more serious.
従つて、本発明は多数ピンのフイルムキヤリヤ
ー等のギヤングボンド用集積回路や、リード間隔
や、リード巾の小さい半導体装置には、特に効果
的に短絡不良を防止できるが、従来のリード間隔
の広いものでも適用できることは明らかである。 Therefore, the present invention can particularly effectively prevent short-circuit failures in large-bond integrated circuits such as multi-pin film carriers, and semiconductor devices with small lead spacing and lead width. It is clear that it can also be applied to
第１図はフイルムキヤリヤー半導体装置を示す
平面図であり、第２図及び第３図は従来の半導体
装置を示す平面図である。第４図乃至第１２図は
本発明の実施例を示す半導体装置の断面図であ
り、第１３図〜第１５図は本発明の実施例を示す
半導体装置の平面図である。このうち、第４図，
第５図，第６図，第７図の組と、第４図，第８
図，第１０図の組と、第４図，第９図，第１１図
の組と、第１２と、第１３図，第１４図と、第１
５図は、各々本発明の実施例を説明するための平
面図もしくは断面図である。
尚、図において、１……フイルムキヤリヤー、
２……リード、３，３０……半導体素子、４４…
…送り孔、５……貫通孔、６，２８……支持枠、
７，１１，１２，２６，２７，２９……支持片、
１０……ペースト、８，１５……基板、９，１
６，１９……配線、１３，２４……ダイボンド接
着剤、１４……アウターリードボンデイング部、
１７……半田、１８，２０，２１，２２，２３…
…パツケージ、２５……切断線部。
FIG. 1 is a plan view showing a film carrier semiconductor device, and FIGS. 2 and 3 are plan views showing a conventional semiconductor device. 4 to 12 are cross-sectional views of a semiconductor device showing an embodiment of the present invention, and FIGS. 13 to 15 are plan views of a semiconductor device showing an embodiment of the present invention. Of these, Figure 4,
A set of figures 5, 6, and 7, and figures 4 and 8.
10, 4, 9, and 11, 12, 13, 14, and 1.
FIG. 5 is a plan view or a sectional view for explaining an embodiment of the present invention, respectively. In addition, in the figure, 1... film carrier,
2... Lead, 3, 30... Semiconductor element, 44...
...Feeding hole, 5...Through hole, 6, 28...Support frame,
7, 11, 12, 26, 27, 29... support piece,
10...Paste, 8,15...Substrate, 9,1
6, 19... Wiring, 13, 24... Die bond adhesive, 14... Outer lead bonding part,
17... solder, 18, 20, 21, 22, 23...
...Package, 25... Cutting line section.
Claims (1)
めのインナーリードを多数備えた半導体装置にお
いて、一端部が前記半導体素子の電極に接続され
たがいに平行に同一方向に延在する複数のインナ
ーリードの他端部は絶縁支持片によりたがいに支
持連結され、該インナーリードは該他端部よりも
前記一端部側の所定個所において前記外部配線に
ボンデイングされていることを特徴とする半導体
装置。 ２ 半導体素子の電極と外部配線とを接続するた
めのインナーリードを多数備えた半導体装置にお
いて、一端部が前記半導体素子の電極に接続され
たがいに平行に同一方向に延在する複数のインナ
ーリードの他端部は絶縁支持片によりたがいに支
持連結され、該インナーリードは該他端部におい
て前記外部配線にボンデイングされていることを
特徴とする半導体装置。[Scope of Claims] 1. A semiconductor device including a large number of inner leads for connecting electrodes of a semiconductor element and external wiring, one end of which extends in the same direction parallel to the electrodes of the semiconductor element connected to the other. The other ends of the plurality of inner leads are supported and connected to each other by insulating support pieces, and the inner leads are bonded to the external wiring at a predetermined location closer to the one end than the other end. semiconductor devices. 2. In a semiconductor device equipped with a large number of inner leads for connecting electrodes of a semiconductor element and external wiring, a plurality of inner leads whose one end is connected to the electrode of the semiconductor element and which extend in the same direction in parallel to the A semiconductor device, wherein the other ends are supported and connected to each other by an insulating support piece, and the inner lead is bonded to the external wiring at the other end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16594479A JPS5688347A (en) | 1979-12-20 | 1979-12-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16594479A JPS5688347A (en) | 1979-12-20 | 1979-12-20 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5688347A JPS5688347A (en) | 1981-07-17 |
| JPS6343897B2 true JPS6343897B2 (en) | 1988-09-01 |
Family
ID=15821977
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16594479A Granted JPS5688347A (en) | 1979-12-20 | 1979-12-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5688347A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6050932A (en) * | 1983-08-31 | 1985-03-22 | Oki Electric Ind Co Ltd | Mounting method for semiconductor chip |
| JPH0394435A (en) * | 1989-09-06 | 1991-04-19 | Toshiba Corp | Semiconductor device |
| US11508799B2 (en) * | 2018-03-28 | 2022-11-22 | Sharp Kabushiki Kaisha | Display device comprising frame region surrounding display region |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5339866A (en) * | 1976-09-24 | 1978-04-12 | Fujitsu Ltd | Packaging method of semiconductor device |
-
1979
- 1979-12-20 JP JP16594479A patent/JPS5688347A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5339866A (en) * | 1976-09-24 | 1978-04-12 | Fujitsu Ltd | Packaging method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5688347A (en) | 1981-07-17 |
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