JPS6343321A - Dry etching method - Google Patents
Dry etching methodInfo
- Publication number
- JPS6343321A JPS6343321A JP18712486A JP18712486A JPS6343321A JP S6343321 A JPS6343321 A JP S6343321A JP 18712486 A JP18712486 A JP 18712486A JP 18712486 A JP18712486 A JP 18712486A JP S6343321 A JPS6343321 A JP S6343321A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- groove
- energy
- etchant
- depth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 18
- 238000001312 dry etching Methods 0.000 title claims description 8
- 238000005530 etching Methods 0.000 claims abstract description 47
- 238000001020 plasma etching Methods 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000000203 mixture Substances 0.000 claims abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 238000003486 chemical etching Methods 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 229910003910 SiCl4 Inorganic materials 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 24
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001035 drying Methods 0.000 description 3
- 239000007864 aqueous solution Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 241000935935 Empodium Species 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004969 ion scattering spectroscopy Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007420 reactivation Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明の高密度・高精度に1μm以下の線幅の非常に垂
直性の良い溝を半導体基板に形成するドライエツチング
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a dry etching method for forming highly vertical grooves with a line width of 1 μm or less in a semiconductor substrate with high density and precision.
従来の技術
半導体集積回路は近年特に高密度化に進んでおリ、素子
間分離やキャパシタに半導体基板表面に形成された深い
(3μm以上)溝を利用するという試みがなされている
。これら素子間トレンチ分シ1やトレンチキャパシタは
トレンチエツチング工程後に埋め込み工程が必要となる
為、溝形状が逆テーパー状になったりすると埋め込み工
程でトレンチ内に空洞ができ長期信頼性等に問題がでて
くる。BACKGROUND ART Semiconductor integrated circuits have become particularly dense in recent years, and attempts have been made to utilize deep grooves (3 μm or more) formed on the surface of a semiconductor substrate for element isolation and capacitors. These inter-element trench divisions 1 and trench capacitors require a burying process after the trench etching process, so if the groove shape becomes inversely tapered, a cavity may be created in the trench during the burying process, causing problems in long-term reliability, etc. It's coming.
またテーパーを順方向にかけすぎると171t11以下
の線幅の溝では溝深さに大きな制限がでてくる。Furthermore, if the taper is applied too much in the forward direction, there will be a large limit to the groove depth for grooves with a line width of 171t11 or less.
以上のような点から溝形状は側面の垂直性が非常に重要
であり、それが制御できるかどうかがポイントとなって
いる。From the above points, the perpendicularity of the side surfaces of the groove shape is very important, and the key point is whether this can be controlled.
現在、トレンチエツチングの主流はR,I 、E(リテ
クティプイオンエソテング)であるが、RIEで形成す
るトレンチが、溝@1μm以下、溝深さ3μm以上程度
のものとなると、エッチャント((イオン)の入射角度
・イオンの溝内での散乱・エツチング生成物の蒸発・溝
内に発生する電界の一影響などが、溝がまだ浅い時点で
のエツチングと溝が深くなったときとで変化し、溝上部
から底部まで垂直にエツチングを行なうのが非常に難し
くなる。Currently, the mainstream of trench etching is R, I, E (retective ion etching), but when the trench formed by RIE has a groove @ 1 μm or less and a groove depth of 3 μm or more, it is necessary to use etchant ((ion etching). ), the scattering of ions within the groove, the evaporation of etching products, and the influence of the electric field generated within the groove, etc., change between etching when the groove is still shallow and when the groove is deep. , it becomes very difficult to etch vertically from the top to the bottom of the groove.
このような理由から、良好な(垂直な)トレンチ形状を
出す為に側面へのデポ物を利用する試みが数多くなされ
ている。これらは、M、5ato andY0人rit
a ” Energy Distr’1buti
on zndDirectionality of
工on in Reactiveion Etch ”
1984ドライプロセス ンンポジウム(Dry P
rocess Symposium)V−4p1o9〜
1149M、 5ato et、al ” T!、t
ched 5hapeControl of Sin
gle Crystallin 5iliconin
Reactive ion Etching Con
tainingChlorin ” 1985 ドラ
イプロセスシンポジウム(Dry Process S
ymposium)1V−4p1o2〜107に示され
ている。For these reasons, many attempts have been made to utilize deposits on the sides to produce a good (vertical) trench shape. These are M, 5ato and Y0 peoplerit
a ”Energy Distr'1buti
on znd Directionality of
Reactivation Etch”
1984 Dry Process Empodium (Dry P
rocess Symposium) V-4p1o9~
1149M, 5ato et, al” T!, t
ched 5hapeControl of Sin
gle crystallin 5iliconin
Reactive ion Etching Con
stainingChlorin” 1985 Dry Process Symposium (Dry Process S
ymposium) 1V-4p1o2-107.
発明が解決しようとする問題点
前述した側面へのデポ物は良好な形状を得る為にはある
程度は許さなければならないが、デポ物の厚みが溝幅と
同じオーダーになったり(例えば1μmの溝幅のトレン
チで0.1〜0.2μmのデポ物が唯積)すると、同時
に違う溝幅のトレンチを形成しようとする場合全く異な
るトレンチ形状になってしまう。また、これらのデポ物
をトレンチ形成後除去する為にば02プラズマやフッ酸
水溶液を用いたウェットエソチエ程が必要と々るが、例
えばフッ酸水溶液を用いたウェットエッチ工程を追加す
ると5i02 の目減りや形状の変化が発生し、イオン
注入工程などに問題が生じプロセスに制限がでてくる場
合が多い。Problems to be Solved by the Invention Although the deposits on the side surfaces described above must be allowed to some extent in order to obtain a good shape, the thickness of the deposits may be on the same order as the groove width (for example, if the thickness of the deposits is on the same order as the groove width) If a deposit of 0.1 to 0.2 μm is accumulated in a trench with a width of 0.1 to 0.2 μm, the shape of the trench will be completely different if trenches with different groove widths are formed at the same time. In addition, in order to remove these deposits after trench formation, a wet etching process using 02 plasma or a hydrofluoric acid aqueous solution is required, but if a wet etching process using a hydrofluoric acid aqueous solution is added, for example, 5i02 This often leads to wear and tear and changes in shape, causing problems in the ion implantation process and limiting the process.
このデポ物を利用しなければいけないという背景には、
前述したように溝が浅い時点と溝が深くなってゆく時点
での最適エツチング条件が異なるにもかかわらず、同条
件でエツチングを行なおうとすることがある。The reason why we have to use this deposit is that
As described above, even though the optimum etching conditions are different between the time when the groove is shallow and the time when the groove is deep, etching may be performed under the same conditions.
問題点を解決する為の手段
本発明はデポ物の唯積を最小限に抑えながら良好なトレ
ンチ形状を得るために、溝が深まるにつれRIE等では
真空度を良くするあるいはパワーを上げるなどにより、
イオンのエネルギーを高くし溝の深さに応じたその時点
での最適エツチング条件でエツチングを行なおうとする
ものである。Means for Solving the Problems In order to obtain a good trench shape while minimizing the accumulation of deposits, the present invention improves the degree of vacuum or increases the power in RIE etc. as the groove deepens.
The purpose is to increase the energy of the ions and perform etching under the optimum etching conditions at that point in time depending on the depth of the groove.
作用
一般にRIE等でイオンのエネルギーを高くする方向に
エツチング条件を変化させてゆくと、イオンの半導体基
板に対する垂直方向の速度成分は水平方向に対して大き
くなってゆく傾向をとる。Generally speaking, when etching conditions are changed in the direction of increasing the energy of ions in RIE or the like, the velocity component of the ions in the vertical direction relative to the semiconductor substrate tends to increase relative to the horizontal direction.
またエツチングを化学的エツチングと物理的エツチング
に単純に分類すると、イオンのエネルギーが大きくなる
程、物理的エツチングの要素が大きくなりエツチングは
異方性を持つ方向に変化してゆく。しかし、物理的エン
チングはイオンの物理的な衝撃によりエツチングを促進
させるのであるから、耐エツチングマスクと半導体基板
とのエツチング選択性は悪くなり、結果としてマスク(
Sin、、、レジスト等)からのエツチング生成物の量
が多くなり溝内への再付着の割合が増すことになる。Further, if etching is simply classified into chemical etching and physical etching, as the energy of the ions increases, the element of physical etching increases and the etching changes in the direction of becoming anisotropic. However, since physical etching promotes etching by physical bombardment of ions, the etching selectivity between the etching-resistant mask and the semiconductor substrate deteriorates, and as a result, the mask (
The amount of etching products from (Sin, .
後述するように溝深さが深くなってもイオンのエネルギ
ーを小さいままにするとイオンの方向性が溝の影響(イ
オンの側面での反射・溝内にかかる電界等)を受けやす
くなり、また溝が深くなるにつt溝内でのイオンの散乱
などによりイオンのエネルギーが消費され、溝がふくら
んだり、ゆが、んだりという現象が起きてしまう。また
、最初からイオンのエネルギーを太きくしてしまうと溝
のゆがみなどはなくなるが、耐エツチングマスクから溝
へのデポ物が多くなり、デポ物の除去が困難となったり
溝形状がV字形になったりという問題点が出てくる。As will be explained later, if the ion energy remains low even when the groove depth becomes deep, the directionality of the ions will be easily influenced by the groove (reflection from the side of the ion, electric field applied within the groove, etc.), and the groove As the T-groove becomes deeper, ion energy is consumed due to ion scattering within the T-groove, causing the groove to swell, become distorted, or become distorted. In addition, if the ion energy is increased from the beginning, the distortion of the grooves will disappear, but more deposits will be deposited into the grooves from the etching-resistant mask, making it difficult to remove the deposits or causing the grooves to become V-shaped. Problems arise.
本発明では溝の浅い時点ではイオンのエネルギーを小さ
くして化学的エツチングの割合を大きくしエツチング生
成物の再付着を抑制し、溝深さが深くなるにつれイオン
のエネルギーを太きくして物理的エツチングの割合を増
加させ、側壁デポ物やイオン二坏ルギー自体を溝深さに
合わせて最適化し、良好な形状を得るものである。In the present invention, when the groove is shallow, the ion energy is reduced to increase the chemical etching rate to suppress redeposition of etching products, and as the groove becomes deeper, the ion energy is increased to perform physical etching. By increasing the proportion of the grooves and optimizing the side wall deposits and the ion beam itself according to the groove depth, a good shape can be obtained.
実施例
第1図は本発明の一実施例によるドレンチエ・ノ図は第
1図のエツチングを行今う・際に使用したそれぞれのエ
ツチング条件で、エツチング条件を変化させずにエツチ
ングしたときの溝形状を示したものである。Embodiment FIG. 1 shows the trench groove according to an embodiment of the present invention. The diagram shows the grooves etched under the respective etching conditions used in the etching shown in FIG. 1 without changing the etching conditions. This shows the shape.
ここでは半導体基板として比抵抗6〜1oΩ・cmのP
型ンリコン基板1を、財エツチングマスクとして171
m厚のンリコン酸化嘆2を用い、反応性イオンエッチ(
RIE)でエツチングを行ないSi溝3を形成した。エ
ツチング条件と1〜ではSi溝を形成する代表的なガス
条件の一つとして知られている51CII4.C7!2
.SF6の混合ガスを使用した。Here, as a semiconductor substrate, P with a specific resistance of 6 to 1 oΩ・cm is used.
The mold recon board 1 is used as a material etching mask 171
Reactive ion etching (
Etching was performed using RIE) to form Si grooves 3. Etching conditions 1 to 51CII4.1 are known as one of the typical gas conditions for forming Si grooves. C7!2
.. A mixed gas of SF6 was used.
RIEでのイオンの平均エネルギーはV、。が大きくな
る程大きくなるという関係があり1.通常ガス条件(ガ
ス種・構成比・流量)を固定した場合、真空度を良くす
るあるいはRFパフ−を大きくすることによりvDcは
大きくなり、したがってイオンエネルギーも大きくなる
傾向にある。第2図(a)。The average energy of ions in RIE is V. There is a relationship that the larger the value, the larger the value becomes.1. Normally, when gas conditions (gas type, composition ratio, flow rate) are fixed, vDc tends to increase by improving the degree of vacuum or increasing the RF puff, and therefore the ion energy also tends to increase. Figure 2(a).
(t)) 、 (C)のエツチングを行なった条件はそ
れぞれ(&)sick4: 2osccm 、 cp2
: 10105c 、 SF6: 12 secm9p
IL 65Qw、(b)sic14:2osccm、
c12:1osccm。The conditions for etching (t)) and (C) were (&)sick4: 2osccm and cp2, respectively.
: 10105c, SF6: 12 secm9p
IL 65Qw, (b) sic14:2osccm,
c12:1osccm.
SF6: 12SCCm 6p& 、 6tsow、
(c) 5i(5/i4: 20SCCm 。SF6: 12SCCm 6p&, 6tsow,
(c) 5i (5/i4: 20SCCm.
C12:10105c SF6:12SCCm、6p
a、600Wである。ガス条件は(a) 、 (b)
、 (C)同じに設定しであるが(b)条件は(a)条
件より真空度が良くイオンのエネルギーが大きい条件と
なっており、(C)条件は(1))条件よりRFパワー
が大きくイオンのエネルギーが大きい条件である。ちな
みにイオンエネルギーの測定は行なっていないが、vD
oについては(2L) 、 (b) 。C12:10105c SF6:12SCCm, 6p
a, 600W. Gas conditions are (a) and (b)
, (C) are set the same, but condition (b) has a better vacuum and higher ion energy than condition (a), and condition (C) has a higher RF power than condition (1)). This is a condition where the energy of the ions is large. By the way, I have not measured the ion energy, but vD
For o, (2L), (b).
(C)条件においてそれぞれ60,60,80Vが得ら
れている。”pcが比較的低いのはこれがマグネトロン
を用いたRIE装置でのデータである為で、通常は(2
L) 、 (b) I (C)条件でそれぞしV、、は
25Q。Under the condition (C), 60, 60, and 80 V were obtained, respectively. ``The reason why pc is relatively low is because this is data from an RIE device using a magnetron, and normally it is (2
L) , (b) I (C) Under the condition, each V, , is 25Q.
300.350W程度である。第2図に示すようにイオ
ンのエネルギーが大きくなるにつれて側壁デポ物4(第
2図Cに示す)は増え、溝が狭くなってゆくことがわか
る。またイオンのエネルギーがこの3条件の中では中間
なものにあたる(b)において、溝の上部と溝の下部で
の溝側壁の傾きが異なり、溝の上部と下部でのエツチン
グの状態が異なっていることがわかる。It is about 300.350W. As shown in FIG. 2, it can be seen that as the ion energy increases, the number of side wall deposits 4 (shown in FIG. 2C) increases and the groove becomes narrower. Furthermore, in (b), where the ion energy is intermediate among these three conditions, the slope of the groove sidewalls at the top and bottom of the groove is different, and the etching state is different at the top and bottom of the groove. I understand that.
これらの現象はイオンエネルギーそのものまたイオンエ
ネルギーに対応するデポ物の変化により起こる訳である
が、本発明では第1図に示すように、まずイオンのエネ
ルギーが小さな(a)条件で一定時間(30S150
)エツチングし、その後ひき続き(b)条件でまた一定
時間(120sec )エツチングし、さらにひき続き
イオンのエネルギーが大きな(c1条件で150860
エツチングを行ない溝深ざに対応するエツチング条件の
最適化により良好な形状を得た。ガス条件を変えること
によってイオンエネルギーを変化させることももちろん
できるが、量産を考えた場合、ガス種を変えるというこ
とは、装置へのガス配管の複雑化・ガス雰囲気の変化に
よるエツチングの低信頼性・ガス条件を切り換えること
によるスループットの低下などの問題点があり、同一ガ
ス条件にすることが望ましい。These phenomena occur due to changes in the ion energy itself or deposits corresponding to the ion energy, but in the present invention, as shown in FIG.
) etching, and then continued etching for a certain period of time (120 sec) under condition (b), and then continued etching under condition (b) for a certain period of time (120 sec), and then continued etching under condition (b), where the ion energy was large (150,860 sec under condition c1).
A good shape was obtained by etching and optimizing the etching conditions corresponding to the groove depth. Of course, it is possible to change the ion energy by changing the gas conditions, but when considering mass production, changing the gas type will complicate the gas piping to the equipment and reduce etching reliability due to changes in the gas atmosphere. - There are problems such as a decrease in throughput due to switching gas conditions, so it is desirable to use the same gas conditions.
またここではRIEに本発明を適用した一実施例につい
て述べたが、ECR(エレクトロン・すNクロトロン・
レゾナンス)を利用したプラズマエツチングにお°ハて
も同様なことが言える。In addition, although an example in which the present invention is applied to RIE has been described here, ECR (electron, carbon chromotron,
The same thing can be said about plasma etching using resonance.
発明の詳細
な説明した発明により、清福が171m以下の溝形成に
おいてその形状を容易にコンI・ロールすることが可能
になった。今後半導体集積回路がますます高密度化して
ゆく中で素子間分離やトレンチキャパシタなどさまざま
な用途に用いられる溝形成技術として極めて工業的価値
の高いものである。DETAILED DESCRIPTION OF THE INVENTION The invention described above has made it possible for Seifuku to easily control and roll the shape of grooves of 171 m or less. As semiconductor integrated circuits become increasingly denser in the future, this trench formation technology is of extremely high industrial value and is used for a variety of applications such as isolation between elements and trench capacitors.
第1図は本発明の一実施例方法により形成された溝の断
面図、第2図は溝形成技術におけるエツチング条件を変
えた場合に形成された溝の断面図である。
1・・・・・・ンリコン酸化膜、2・・・・・・ンリコ
ン基板、3・・・・・・溝。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名1−
−−ミノリコン1之1ヒ叉艷
第2図
(久)
第2図FIG. 1 is a cross-sectional view of a groove formed by a method according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a groove formed when etching conditions in the groove forming technique are changed. 1... Silicon oxide film, 2... Silicon substrate, 3... Groove. Name of agent: Patent attorney Toshio Nakao and 1 other person1-
--Minoricon 1 No. 1 Hikari Diagram 2 (Ku) Diagram 2
Claims (6)
てプラズマエッチングを行ない溝形成を行なう際に、エ
ッチャントのエネルギーが溝の深さが深くなる程高くな
るようにエッチング条件を変化させるようにしたドライ
エッチング方法。(1) Dry etching in which the etching conditions are changed so that the energy of the etchant increases as the depth of the groove increases when plasma etching is performed on a semiconductor substrate using an etching-resistant mask as a mask to form a groove. Method.
またエッチャントのエネルギーがより高くなる別の一定
条件で、ある時間エッチングを行なうという工程を繰り
返すことにより、エッチャントのエネルギーを溝の深さ
が深くなる程高くするようにした特許請求の範囲第1項
記載のドライエッチング方法。(2) By repeating the process of etching under certain conditions for a certain period of time, and then etching again for a certain period of time under another certain condition where the etchant energy is higher, the etchant energy can be used to increase the depth of the groove. The dry etching method according to claim 1, wherein the etching height is increased as the depth increases.
電圧を高めるようにした特許請求の範囲第1項記載のド
ライエッチング方法。(3) The dry etching method according to claim 1, wherein reactive ion etching is used to increase the cathode drop voltage.
にエッチャントのエネルギーが高くなる方向へ変化させ
ることにより、エッチャントのエネルギーを溝の深さが
深くなる程高くするようにした特許請求の範囲第1項記
載のドライエッチング方法。(4) A patent claim in which the energy of the etchant increases as the depth of the groove increases by gradually changing the gas composition ratio, gas flow rate, pressure, power, etc. in a direction that increases the energy of the etchant. The dry etching method according to scope 1.
、あるいはRFパワーを大きくしていくことによって、
エッチャントのエネルギーを高くするようにした特許請
求の範囲第1項記載のドライエッチング方法。(5) By increasing the degree of vacuum or increasing the RF power as etching conditions,
The dry etching method according to claim 1, wherein the energy of the etchant is increased.
許請求の範囲第5項記載のドライエッチング方法。(6) The dry etching method according to claim 5, wherein the gas composition ratio and gas flow rate are kept constant.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61187124A JP2502536B2 (en) | 1986-08-08 | 1986-08-08 | Pattern formation method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61187124A JP2502536B2 (en) | 1986-08-08 | 1986-08-08 | Pattern formation method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6343321A true JPS6343321A (en) | 1988-02-24 |
JP2502536B2 JP2502536B2 (en) | 1996-05-29 |
Family
ID=16200532
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61187124A Expired - Lifetime JP2502536B2 (en) | 1986-08-08 | 1986-08-08 | Pattern formation method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2502536B2 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0822582A2 (en) * | 1996-08-01 | 1998-02-04 | Surface Technology Systems Limited | Method of surface treatment of semiconductor substrates |
WO1999010922A1 (en) * | 1997-08-21 | 1999-03-04 | Robert Bosch Gmbh | Method for anisotropic etching of silicon |
WO2002025714A1 (en) * | 2000-09-20 | 2002-03-28 | Infineon Technologies Sc300 Gmbh & Co. Kg | A process for dry-etching a semiconductor wafer surface |
FR2834382A1 (en) * | 2002-01-03 | 2003-07-04 | Cit Alcatel | METHOD AND DEVICE FOR ANISOTROPIC ETCHING OF HIGH APPEARANCE SILICON |
WO2005071721A1 (en) * | 2004-01-26 | 2005-08-04 | Oxford Instruments Plasma Technology Limited | Plasma etching process |
US7214580B2 (en) | 2003-09-09 | 2007-05-08 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
JP2009239054A (en) * | 2008-03-27 | 2009-10-15 | Sumitomo Precision Prod Co Ltd | Manufacturing method, manufacturing device and manufacturing program of silicon structure |
JP2013138052A (en) * | 2011-12-28 | 2013-07-11 | Hitachi High-Technologies Corp | Plasma etching method |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62276829A (en) * | 1986-05-26 | 1987-12-01 | Hitachi Micro Comput Eng Ltd | Method and apparatus for etching |
-
1986
- 1986-08-08 JP JP61187124A patent/JP2502536B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62276829A (en) * | 1986-05-26 | 1987-12-01 | Hitachi Micro Comput Eng Ltd | Method and apparatus for etching |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0822582A2 (en) * | 1996-08-01 | 1998-02-04 | Surface Technology Systems Limited | Method of surface treatment of semiconductor substrates |
EP0822582A3 (en) * | 1996-08-01 | 1998-05-13 | Surface Technology Systems Limited | Method of surface treatment of semiconductor substrates |
WO1999010922A1 (en) * | 1997-08-21 | 1999-03-04 | Robert Bosch Gmbh | Method for anisotropic etching of silicon |
US6284148B1 (en) | 1997-08-21 | 2001-09-04 | Robert Bosch Gmbh | Method for anisotropic etching of silicon |
WO2002025714A1 (en) * | 2000-09-20 | 2002-03-28 | Infineon Technologies Sc300 Gmbh & Co. Kg | A process for dry-etching a semiconductor wafer surface |
WO2003060975A1 (en) * | 2002-01-03 | 2003-07-24 | Alcatel | Method and device for anisotropic etching of high aspect ratio |
FR2834382A1 (en) * | 2002-01-03 | 2003-07-04 | Cit Alcatel | METHOD AND DEVICE FOR ANISOTROPIC ETCHING OF HIGH APPEARANCE SILICON |
US7214580B2 (en) | 2003-09-09 | 2007-05-08 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US7462531B2 (en) | 2003-09-09 | 2008-12-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US7968399B2 (en) | 2003-09-09 | 2011-06-28 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
WO2005071721A1 (en) * | 2004-01-26 | 2005-08-04 | Oxford Instruments Plasma Technology Limited | Plasma etching process |
JP2009239054A (en) * | 2008-03-27 | 2009-10-15 | Sumitomo Precision Prod Co Ltd | Manufacturing method, manufacturing device and manufacturing program of silicon structure |
JP2013138052A (en) * | 2011-12-28 | 2013-07-11 | Hitachi High-Technologies Corp | Plasma etching method |
Also Published As
Publication number | Publication date |
---|---|
JP2502536B2 (en) | 1996-05-29 |
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