JPS6343246U - - Google Patents
Info
- Publication number
- JPS6343246U JPS6343246U JP13377586U JP13377586U JPS6343246U JP S6343246 U JPS6343246 U JP S6343246U JP 13377586 U JP13377586 U JP 13377586U JP 13377586 U JP13377586 U JP 13377586U JP S6343246 U JPS6343246 U JP S6343246U
- Authority
- JP
- Japan
- Prior art keywords
- data
- circuit
- processor
- bit
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 7
- 230000004048 modification Effects 0.000 claims description 2
- 238000012986 modification Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Image Input (AREA)
Description
第1図は本考案の構成を示すブロツク図、第2
図は本考案に係るデータ変更回路の一例を示す回
路図、第3図はメモリのアクセス処理系全体の構
成例を示すブロツク図である。
1…プロセツサ、2(1),2(2),…,2(h)
…1ビツト構成メモリ、3…メモリ、4(1),4(
2),…,4(h)…アクセス禁止回路、5(1),
5(2),…,5(h)…ビツトデータ設定回路。
Figure 1 is a block diagram showing the configuration of the present invention, Figure 2 is a block diagram showing the configuration of the present invention.
The figure is a circuit diagram showing an example of a data modification circuit according to the present invention, and FIG. 3 is a block diagram showing an example of the configuration of the entire memory access processing system. 1...Processor, 2(1), 2(2),..., 2(h)
...1 bit configuration memory, 3...memory, 4(1), 4(
2),...,4(h)...Access prohibited circuit, 5(1),
5(2),...,5(h)...Bit data setting circuit.
Claims (1)
ス可能な1ビツト構成メモリを複数備えてなるメ
モリに蓄えられたデータをプロセツサからの指令
に基づいて書換えるデータ変更回路であつて、上
記各1ビツト構成メモリ毎に、所定の指令信号に
基づいてプロセツサからのライトアクセスを禁止
するアクセス禁止回路と、書込みビツトデータを
設定するビツトデータ設定回路とを備えたことを
特徴とするメモリのデータ変更回路。 A data modification circuit that rewrites data stored in a memory comprising a plurality of independently accessible 1-bit configuration memories based on instructions from a processor, the data changing circuit rewriting each of the 1-bit configuration memories based on instructions from the processor. 1. A data change circuit for a memory, comprising: an access prohibition circuit that prohibits write access from a processor based on a predetermined command signal; and a bit data setting circuit that sets write bit data.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13377586U JPS6343246U (en) | 1986-09-02 | 1986-09-02 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13377586U JPS6343246U (en) | 1986-09-02 | 1986-09-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6343246U true JPS6343246U (en) | 1988-03-23 |
Family
ID=31034398
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13377586U Pending JPS6343246U (en) | 1986-09-02 | 1986-09-02 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6343246U (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57141087A (en) * | 1981-02-25 | 1982-09-01 | Fujitsu Ltd | Write system for storage device |
JPS58125284A (en) * | 1982-01-20 | 1983-07-26 | Hitachi Ltd | Memory access method |
JPS59213083A (en) * | 1983-05-18 | 1984-12-01 | Sanyo Electric Co Ltd | Memory writing method |
JPS607676A (en) * | 1983-06-25 | 1985-01-16 | Fujitsu Ltd | Memory writing circuit |
-
1986
- 1986-09-02 JP JP13377586U patent/JPS6343246U/ja active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57141087A (en) * | 1981-02-25 | 1982-09-01 | Fujitsu Ltd | Write system for storage device |
JPS58125284A (en) * | 1982-01-20 | 1983-07-26 | Hitachi Ltd | Memory access method |
JPS59213083A (en) * | 1983-05-18 | 1984-12-01 | Sanyo Electric Co Ltd | Memory writing method |
JPS607676A (en) * | 1983-06-25 | 1985-01-16 | Fujitsu Ltd | Memory writing circuit |
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