JPS6338334U - - Google Patents
Info
- Publication number
- JPS6338334U JPS6338334U JP13095286U JP13095286U JPS6338334U JP S6338334 U JPS6338334 U JP S6338334U JP 13095286 U JP13095286 U JP 13095286U JP 13095286 U JP13095286 U JP 13095286U JP S6338334 U JPS6338334 U JP S6338334U
- Authority
- JP
- Japan
- Prior art keywords
- recess
- integrated circuit
- conductive pattern
- circuit chip
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 2
- 239000003292 glue Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Die Bonding (AREA)
Description
第１図は本考案の一実施例を示した正面図、第
２図は第１図の構成に集積回路チツプを固定した
状態を示した断面図、第３〜５図はそれぞれ従来
のプリント基板の製造工程を示した正面図、第６
図は第５図の―線断面図である。
１……基板、２……導電パターン、３……凹部
、４……切り溝、５……集積回路チツプ、６……
接着剤。
Fig. 1 is a front view showing an embodiment of the present invention, Fig. 2 is a sectional view showing a state in which an integrated circuit chip is fixed to the structure shown in Fig. 1, and Figs. 3 to 5 are respectively conventional printed circuit boards. 6th front view showing the manufacturing process of
The figure is a sectional view taken along the line -- in FIG. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Conductive pattern, 3... Recess, 4... Cut groove, 5... Integrated circuit chip, 6...
glue.
Claims (1)
着固定し、上記凹部周辺に上記集積回路チツプと
ダイボンデイングされる導電パターンを形成して
あり、この導電パターンの上記凹部周辺に位置す
る部分をカツトしたことを特徴とするプリント基
板。 An integrated circuit chip is adhesively fixed in a recess formed on a substrate, a conductive pattern is formed around the recess to be die-bonded to the integrated circuit chip, and a portion of the conductive pattern located around the recess is cut. A printed circuit board characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13095286U JPS6338334U (en) | 1986-08-27 | 1986-08-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13095286U JPS6338334U (en) | 1986-08-27 | 1986-08-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6338334U true JPS6338334U (en) | 1988-03-11 |
Family
ID=31028945
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13095286U Pending JPS6338334U (en) | 1986-08-27 | 1986-08-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6338334U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01283883A (en) * | 1988-05-10 | 1989-11-15 | Matsushita Electric Ind Co Ltd | Light emitting diode and forming method for its electrode |
| DE112017002421T5 (en) | 2016-05-12 | 2019-01-24 | Mitsubishi Electric Corporation | SEMICONDUCTOR UNIT AND METHOD FOR PRODUCING A SEMICONDUCTOR UNIT |
-
1986
- 1986-08-27 JP JP13095286U patent/JPS6338334U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01283883A (en) * | 1988-05-10 | 1989-11-15 | Matsushita Electric Ind Co Ltd | Light emitting diode and forming method for its electrode |
| DE112017002421T5 (en) | 2016-05-12 | 2019-01-24 | Mitsubishi Electric Corporation | SEMICONDUCTOR UNIT AND METHOD FOR PRODUCING A SEMICONDUCTOR UNIT |
| US10741413B2 (en) | 2016-05-12 | 2020-08-11 | Mitsubishi Electric Corporation | Semiconductor device and method for manufacturing semiconductor device |