JPS6338316U - - Google Patents
Info
- Publication number
- JPS6338316U JPS6338316U JP13187086U JP13187086U JPS6338316U JP S6338316 U JPS6338316 U JP S6338316U JP 13187086 U JP13187086 U JP 13187086U JP 13187086 U JP13187086 U JP 13187086U JP S6338316 U JPS6338316 U JP S6338316U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- pressure
- core tube
- present
- reducing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 claims 1
- 239000012495 reaction gas Substances 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000010926 purge Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Description
第1図は、本考案装置の基本的な概要図、第2
図は、従来の減圧化学気相成長装置概要図、第3
図は従来装置で製造されたデバイス断面図、第4
図a〜第4図fは、本考案装置にてのウエーハの
入出炉方法概念図、第5図は、本考案装置の改良
タイプの概要図、第6図は、本考案装置の他のウ
エーハローデイング方法への応用概要図、第7図
は、本考案の不純物拡散炉への応用概要図である
。
1……炉芯管、2……半導体基板(ウエーハ)
、3……半導体基板ローデイング治具、4……反
応ガス注入ノズル、5……反応性ガス、6……半
導体基板P+拡散層、7……多結晶シリコン、8
……酸化ケイ素、9……パージ用不活性ガス、1
0……しきり(バルブ)、11……真空ポンプ、
12……予備室、13……真空ポンプ、14……
パージ用不活性ガス、15……予備室加熱用ヒー
ターコイル、16……炉芯管加熱用ヒーターコイ
ル、17……エアー駆動バルブ、18……ボート
移動用治具、19……O―リング、20……予備
室フタ、21……別タイプボート移動用治具、2
2……酸化ケイ素、23……半導体基板、24…
…減圧を示す。
Figure 1 is a basic schematic diagram of the device of the present invention;
The figure is a schematic diagram of a conventional low-pressure chemical vapor deposition apparatus,
The figure is a cross-sectional view of a device manufactured using conventional equipment.
Figures a to 4f are conceptual diagrams of wafer loading and unloading methods in the apparatus of the present invention, Figure 5 is a schematic diagram of an improved type of the apparatus of the present invention, and Figure 6 is a conceptual diagram of the method of loading and unloading wafers in the apparatus of the present invention. FIG. 7 is a schematic diagram of the application of the present invention to an impurity diffusion furnace. 1...Furnace core tube, 2...Semiconductor substrate (wafer)
, 3... Semiconductor substrate loading jig, 4... Reactive gas injection nozzle, 5... Reactive gas, 6... Semiconductor substrate P + diffusion layer, 7... Polycrystalline silicon, 8
...Silicon oxide, 9 ...Inert gas for purging, 1
0... Shikiri (valve), 11... Vacuum pump,
12...Preliminary room, 13...Vacuum pump, 14...
Inert gas for purging, 15...Heater coil for heating the preliminary chamber, 16...Heater coil for heating the furnace core tube, 17...Air drive valve, 18...Jig for moving the boat, 19...O-ring, 20... Spare room lid, 21... Jig for moving another type of boat, 2
2...Silicon oxide, 23...Semiconductor substrate, 24...
...Indicates reduced pressure.
Claims (1)
挿入し、さらに内部を減圧し、かつその中に反応
ガスを注入することにより薄膜を形成する、減圧
化学気相成長装置において、炉芯管の入口部に開
閉可能なしきりを介して、減圧機構を持つた予備
室を有することを特徴とする半導体製造装置。 In a low-pressure chemical vapor deposition apparatus that forms a thin film by inserting a semiconductor substrate into a furnace core tube that has a temperature control mechanism, reducing the pressure inside it, and injecting a reaction gas into it, 1. A semiconductor manufacturing device comprising a preliminary chamber having a pressure reducing mechanism at an entrance portion thereof through an openable/closable barrier.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13187086U JPS6338316U (en) | 1986-08-27 | 1986-08-27 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13187086U JPS6338316U (en) | 1986-08-27 | 1986-08-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6338316U true JPS6338316U (en) | 1988-03-11 |
Family
ID=31030723
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13187086U Pending JPS6338316U (en) | 1986-08-27 | 1986-08-27 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6338316U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5825225B2 (en) * | 1979-06-19 | 1983-05-26 | 大阪瓦斯株式会社 | Sound wave propagation time measurement method and position locating method |
-
1986
- 1986-08-27 JP JP13187086U patent/JPS6338316U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5825225B2 (en) * | 1979-06-19 | 1983-05-26 | 大阪瓦斯株式会社 | Sound wave propagation time measurement method and position locating method |
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