JPS6336143B2 - - Google Patents
Info
- Publication number
- JPS6336143B2 JPS6336143B2 JP54161542A JP16154279A JPS6336143B2 JP S6336143 B2 JPS6336143 B2 JP S6336143B2 JP 54161542 A JP54161542 A JP 54161542A JP 16154279 A JP16154279 A JP 16154279A JP S6336143 B2 JPS6336143 B2 JP S6336143B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- oxide film
- gate
- cell plate
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 claims description 5
- 238000003860 storage Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000000151 deposition Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910007991 Si-N Inorganic materials 0.000 description 1
- 229910006294 Si—N Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置、特にMOS半導体記憶装
置の製造法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, particularly a MOS semiconductor memory device.
１トランジスタ型ダイナミツクMOS半導体記
憶装置は、第１図に示すようにSi半導体基板１に
おいてフイルド酸化膜２により囲まれたアクテイ
ブ領域表面にゲート絶縁膜（SiO2膜）３を介し
てセルプレートと称するポリSi第１ゲート４が形
成され、この第１ゲートの上に絶縁膜５を介して
転送部となる第２ゲート６が形成されてその一部
がゲート絶縁膜３上に延在し、第２ゲートの形成
されないゲート絶縁膜下の半導体基板表面に基板
と異なる導電型の不純物導入層７がデータ線とし
て形成されたセル構造を有し、上記セルプレート
下を蓄積容量部とし、これに対し転送部（アクテ
イブMOSFET）を介してデータの書き込み読み
出しを行なうようになつている。 In a one-transistor type dynamic MOS semiconductor memory device, as shown in FIG. 1, a gate insulating film (SiO 2 film) 3 is formed on the surface of an active region surrounded by a field oxide film 2 in a Si semiconductor substrate 1, called a cell plate. A poly-Si first gate 4 is formed, and a second gate 6 serving as a transfer section is formed on this first gate via an insulating film 5, a part of which extends over the gate insulating film 3. It has a cell structure in which an impurity-introduced layer 7 of a conductivity type different from that of the substrate is formed as a data line on the surface of the semiconductor substrate under the gate insulating film where no two gates are formed, and the area under the cell plate is used as a storage capacitor part, and Data is written and read via a transfer section (active MOSFET).
このようなMOS半導体記憶装置においてメモ
リセルのセルプレートにVcc（＋12V又は＋5V等）
を加えて在来用いているが、Vccを変動させて特
性マージンをテストするVccバンプ特性がわるく、
メモリの内容を保証できないという問題がある。
しかし、メモリセルにおいては必ずしもVcc接続
しなければならないという理由はなく、むしろ
Vss（OV）をセルプレートに加える技術が望まし
いとがわかつてきた。ところでVssを接続する場
合にはダイナミツクメモリセルの蓄積容量部の条
件としてはセルプレート下のSi基板（Ｐ型基板）
の表面部Ａに基体と反対の導電型の層、すなわち
n+層を設けてコンデンサの機能を持たせる必要
がある。 In such a MOS semiconductor memory device, V cc (+12V or +5V, etc.) is applied to the cell plate of the memory cell.
However, the V cc bump characteristics, which test the characteristic margin by varying V cc , are poor.
There is a problem that the contents of memory cannot be guaranteed.
However, there is no reason why memory cells must be connected to V cc ; rather,
Techniques for adding V ss (OV) to the cell plate have proven desirable. By the way, when connecting Vss , the storage capacitor part of the dynamic memory cell must be connected to a Si substrate (P-type substrate) under the cell plate.
A layer of conductivity type opposite to that of the substrate is formed on the surface part A of the substrate, i.e.
It is necessary to provide an n + layer to function as a capacitor.
ダイナミツクMOSメモリセルを製造する場合
の基本的なプロセスは、(1)Si基板に選択酸化によ
るフイルド絶縁膜の形成、(2)熱酸化によるゲート
絶縁膜の形成、(3)ポリSi堆積・ホトレジスト処理
による第１ゲート（セルプレート）形成、(4)
CVO（気相化学堆積法）によるSiO2膜形成、(5)ポ
リSi堆積、ホトレジスト処理による第２ゲート形
成、(6)第２ゲートをマスクとして自己整合的に
n+拡散によるデータ線の形成の各工程を有する
ものであるが、セルプレート下のSi基板表面にn+
層を形成するためにはそのためにホトレジスト
膜・マスク工程を加えなければならず、これに伴
なう前後工程のマスク位置合せは甚だ厄介であ
り、工程数も増えてのぞましくない。 The basic process for manufacturing dynamic MOS memory cells is (1) formation of a field insulating film on a Si substrate by selective oxidation, (2) formation of a gate insulating film by thermal oxidation, and (3) poly-Si deposition/photoresist. First gate (cell plate) formation by processing, (4)
SiO 2 film formation by CVO (chemical vapor deposition), (5) poly-Si deposition, second gate formation by photoresist treatment, (6) self-alignment using the second gate as a mask.
This method includes each step of forming data lines by n + diffusion, but the n +
In order to form a layer, it is necessary to add a photoresist film/mask process, and the associated mask positioning in the previous and subsequent processes is extremely troublesome, and the number of processes increases, which is undesirable.
本発明は上記した問題を解決するためになされ
たもので、その目的とするところは、特にマスク
工程をふやすことなくセルプレート下にn+層を
形成できるMOS半導体装置の製造法の提供にあ
る。 The present invention has been made to solve the above-mentioned problems, and its purpose is to provide a method for manufacturing a MOS semiconductor device that can form an n + layer under a cell plate without increasing the number of mask steps. .
上記目的を達成するための本発明の要旨は、第
１導電型の半導体領域の一主面の表面部に第２導
電型の不純物を導入し、該第２導電型の不純物導
入領域上に第１の絶縁膜を介して第１の導電体層
を選択的に形成する工程と、前記第１の導電体層
が被覆されなかつた前記一主面の前記第２導電型
不純物導入領域を酸化して酸化膜を形成し、該酸
化膜をエツチ除去することによつて前記第１の導
電体層が被覆されなかつた前記第２導電型不純物
導入領域を取除く工程と、前記酸化膜が除去され
た前記一主面に第２の絶縁膜を介して第２の導電
体層を形成する工程とを有することを特徴とする
半導体装置の製造法にある。 The gist of the present invention for achieving the above object is to introduce impurities of a second conductivity type into the surface portion of one main surface of a semiconductor region of a first conductivity type, and to introduce impurities into the impurity-introduced region of the second conductivity type. selectively forming a first conductive layer through one insulating film; and oxidizing the second conductivity type impurity-introduced region of the one main surface that is not covered with the first conductive layer. forming an oxide film, and removing the second conductivity type impurity-introduced region that is not covered with the first conductor layer by etching the oxide film; and removing the oxide film. forming a second conductor layer on the one main surface via a second insulating film.
また、本発明は、特に、１トランジスタ型ダイ
ナミツクMOS半導体記憶装置に適した半導体装
置の製造法を提供するために、上記第１の導電体
層は記憶装置の蓄積容量部のセルプレートとして
形成され、一方、上記第２の導電体層は記憶装置
のトランジスタ部のゲートとして形成されること
を特徴とする。 Further, the present invention particularly provides a method for manufacturing a semiconductor device suitable for a one-transistor type dynamic MOS semiconductor memory device, in which the first conductor layer is formed as a cell plate of a storage capacitor portion of the memory device. On the other hand, the second conductive layer is formed as a gate of a transistor section of a memory device.
第２図ａ〜ｇは本発明による１トランジスタ型
ダイナミツクMOSメモリのメモリセル製造プロ
セスの例を工程順に示し、以下各工程に従つて説
明する。 FIGS. 2a to 2g show an example of a memory cell manufacturing process for a one-transistor type dynamic MOS memory according to the present invention in the order of steps, and each step will be explained below.
(a) Ｐ型Si基板１の一主面に例えばSi−Ｎ膜をマ
スクに選択酸化を行なつてフイルド酸化膜２を
形成し、その後マスクを取除きアクテイブ領域
のSi基板表面に熱酸化によるゲート酸化膜
（SiO2）３を形成する。(a) A field oxide film 2 is formed on one main surface of the P-type Si substrate 1 by selective oxidation using, for example, a Si-N film as a mask, and then the mask is removed and the surface of the Si substrate in the active area is oxidized by thermal oxidation. A gate oxide film (SiO 2 ) 3 is formed.
(b) フイルド酸化膜２をマスクにしてゲート酸化
膜３を通してAs（ヒ素）又はＰ（リン）等のド
ナをイオン打込み又はデポジシヨン−拡散手段
によりSi表面に導入し、n+層８を形成する。こ
のn+層はなるべく浅く設ける必要がある。（な
おn+不純物導入は選択酸化工程後、セルプレ
ート電極形成後に行なつてもよい）
(c) 熱分解法又は還元法等により気相からSi化合
物を全面に堆積してポリSi層４をある程度厚く
形成し、その後ホトレジスト処理によつてポリ
Siの不要部を除去しセルプレート（第１ポリSi
ゲート）４を形成する。このポリSiゲートには
適当な不純物をドープすることにより導体化す
る。(b) Using the field oxide film 2 as a mask, a donor such as As (arsenic) or P (phosphorous) is introduced into the Si surface through the gate oxide film 3 by ion implantation or deposition-diffusion means to form the n + layer 8. . This n + layer needs to be provided as shallowly as possible. (Introduction of the n + impurity may be performed after the selective oxidation process and after the formation of the cell plate electrode.) (c) A poly-Si layer 4 is formed by depositing a Si compound from the gas phase over the entire surface using a thermal decomposition method or a reduction method. It is formed to a certain degree of thickness, and then the polyester is formed using photoresist processing.
Remove the unnecessary part of Si and remove the cell plate (first poly-Si
Gate) 4 is formed. This poly-Si gate is doped with an appropriate impurity to make it conductive.
(d) 通常の高温酸化（1000〜1100℃）工程でセル
プレート表面及び目あき部（セルプレートのな
い部分）のSi表面を酸化して第２の酸化膜
（SiO2膜）９，１０を形成する。この酸化によ
つて目あき部の表面に導入されているn+層部
分も酸化される。(d) A second oxide film (SiO 2 film) 9, 10 is formed by oxidizing the cell plate surface and the Si surface of the opening (the part without the cell plate) using a normal high temperature oxidation process (1000 to 1100°C). Form. As a result of this oxidation, the n + layer portion introduced onto the surface of the perforated portion is also oxidized.
(e) SiO2を侵しSiを侵しにくいエツチ液、例え
ばフツ素系エツチ液を用いてポリSiゲートの表
面及び目あき部の表面の酸化膜を同時にエツチ
除去する。(e) Using an etchant that attacks SiO 2 but hardly attacks Si, such as a fluorine-based etchant, the oxide film on the surface of the poly-Si gate and the surface of the opening are simultaneously etched away.
(f) 通常に熱酸化法によりセルプレート表面に新
たに酸化膜５ａを形成するとともに目あき部の
Si基板表面に酸化膜（第２ゲート酸化膜）５ｂ
を形成する。(f) Normally, a new oxide film 5a is formed on the cell plate surface using a thermal oxidation method, and the openings are
Oxide film (second gate oxide film) 5b on the surface of the Si substrate
form.
(g) 気相より全面にポリSi層６を析出し、次いで
ホトレジスト処理により第２層ゲート６を形成
する。この後第２層ゲートをマスクにしてドナ
をSi基板表面に拡散し、n+層７からなるデータ
線を形成する。(g) A poly-Si layer 6 is deposited on the entire surface from a gas phase, and then a second layer gate 6 is formed by photoresist treatment. Thereafter, using the second layer gate as a mask, a donor is diffused onto the surface of the Si substrate to form a data line consisting of the n + layer 7.
以上実施例によれば下記理由で前記目的が達成
できる。 According to the embodiments described above, the above object can be achieved for the following reasons.
前記工程(d)(e)によつてセルプレート以外の部分
におけるn+層が除去され、特にそのためにマス
クを用いることなく選択的にn+層の導入ができ、
結果としてセルプレートにVssを接続して用いる
ことが可能となつた。 In steps (d) and (e), the n + layer in the portion other than the cell plate is removed, and in particular, the n + layer can be selectively introduced without using a mask,
As a result, it became possible to connect Vss to the cell plate.
このようなVssプレート化によりVccバンプ対策
が可能となりノイズ等の発生を防止できる。 By using such a V ss plate, it is possible to take measures against V cc bumps and prevent the generation of noise.
本発明は前記実施例に限定されず、これ以外の
種々の形態の実施がなされうる。 The present invention is not limited to the embodiments described above, and may be implemented in various other forms.
例えば第３図ａに示すようにゲート酸化膜の下
にn+層及びp+層を導入し、第２図のｂ〜ｇ工程
を経ることにより、第３図ｂに示すようにセルプ
レートの下にn+・p+層を形成すると、外部より
のα線によるチヤージの防止手段として有効であ
る。 For example, by introducing an n + layer and a p + layer under the gate oxide film as shown in Fig. 3a, and going through steps b to g in Fig. 2, the cell plate is formed as shown in Fig. 3b. Forming an n + /p + layer underneath is effective as a means to prevent charging by external alpha rays.
本発明はｐチヤネルのMOS装置の場合にも同
様に適用できる。 The present invention is similarly applicable to p-channel MOS devices.
第１図はセルプレートにVccを接続する場合の
ダイナミツクMOSメモリのセルの形態を示す断
面図である。第２図ａ〜ｇは本発明によるダイナ
ミツクMOSメモリのメモリセルの製造プロセス
の実施例を工程順に示す断面図である。第３図
ａ，ｂは本発明によるメモリセルの他の実施形態
を示す一部工程の断面図である。
１……Si基板、２……フイルド酸化膜、３……
ゲート絶縁膜、４……ポリSi第１ゲート（セルプ
レート）、５……絶縁膜、６……第２ポリSiゲー
ト、７……n+層（データ線）、８……n+層、９…
…酸化膜、１０……p+層。
FIG. 1 is a sectional view showing the form of a dynamic MOS memory cell when Vcc is connected to the cell plate. FIGS. 2a to 2g are cross-sectional views sequentially showing an embodiment of a process for manufacturing a memory cell of a dynamic MOS memory according to the present invention. FIGS. 3a and 3b are cross-sectional views showing some steps of another embodiment of a memory cell according to the present invention. 1...Si substrate, 2...Field oxide film, 3...
Gate insulating film, 4... poly-Si first gate (cell plate), 5... insulating film, 6... second poly-Si gate, 7... n + layer (data line), 8... n + layer, 9...
...Oxide film, 10...p + layer.
Claims (1)
第２導電型の不純物を導入し、該第２導電型の不
純物導入領域上に第１の絶縁膜を介して第１の導
電体層を選択的に形成する工程と、前記第１の導
電体層が被覆されなかつた前記一主面の前記第２
導電型不純物導入領域を酸化して酸化膜を形成
し、該酸化膜をエツチ除去することによつて前記
第１の導電体層が被覆されなかつた前記第２導電
型不純物導入領域を取除く工程と、前記酸化膜が
除去された前記一主面に第２の絶縁膜を介して第
２の導電体層を形成する工程とを有することを特
徴とする半導体装置の製造法。 ２ 前記第１の導電体層は１トランジスタ型ダイ
ナミツクMOS半導体記憶装置の蓄積容量部のセ
ルプレートとして形成し、第２の導電体層はその
トランジスタ部のゲートとして形成するものであ
ることを特徴とする特許請求の範囲第１項記載の
半導体装置の製造法。[Claims] 1. A second conductivity type impurity is introduced into a surface portion of one principal surface of a first conductivity type semiconductor region, and a first insulating film is interposed over the second conductivity type impurity introduced region. a step of selectively forming a first conductor layer on the first conductor layer;
oxidizing the conductive type impurity introduced region to form an oxide film, and removing the second conductive type impurity introduced region that is not covered with the first conductive layer by etching away the oxide film; and forming a second conductor layer on the one main surface from which the oxide film has been removed, with a second insulating film interposed therebetween. 2. The first conductive layer is formed as a cell plate of a storage capacitor section of a one-transistor type dynamic MOS semiconductor memory device, and the second conductive layer is formed as a gate of the transistor section. A method for manufacturing a semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16154279A JPS5685853A (en) | 1979-12-14 | 1979-12-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16154279A JPS5685853A (en) | 1979-12-14 | 1979-12-14 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5685853A JPS5685853A (en) | 1981-07-13 |
| JPS6336143B2 true JPS6336143B2 (en) | 1988-07-19 |
Family
ID=15737074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16154279A Granted JPS5685853A (en) | 1979-12-14 | 1979-12-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5685853A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59121866A (en) * | 1982-12-28 | 1984-07-14 | Oki Electric Ind Co Ltd | Semiconductor memory element |
| US4826779A (en) * | 1986-10-24 | 1989-05-02 | Teledyne Industries, Inc. | Integrated capacitor and method of fabricating same |
-
1979
- 1979-12-14 JP JP16154279A patent/JPS5685853A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5685853A (en) | 1981-07-13 |
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