JPS6334658B2 - - Google Patents
Info
- Publication number
- JPS6334658B2 JPS6334658B2 JP54005142A JP514279A JPS6334658B2 JP S6334658 B2 JPS6334658 B2 JP S6334658B2 JP 54005142 A JP54005142 A JP 54005142A JP 514279 A JP514279 A JP 514279A JP S6334658 B2 JPS6334658 B2 JP S6334658B2
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- circuit
- pulse
- transistor
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004804 winding Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 5
- 230000000295 complement effect Effects 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/20—Repeater circuits; Relay circuits
- H04L25/22—Repeaters for converting two wires to four wires; Repeaters for converting single current to double current
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Logic Circuits (AREA)
- Dc Digital Transmission (AREA)
Description
【発明の詳細な説明】
本発明は有線のデイジタル中継器等に用いる３
値パルス発生回路に関する。有線のデイジタル中
継方式における伝送路符号形式はいわゆるバイポ
ーラ符号（AMI符号）を始めとして圧倒的に３
値符号が多い。[Detailed Description of the Invention] The present invention provides three
This invention relates to a value pulse generation circuit. There are overwhelmingly three transmission path code formats in wired digital relay systems, including the so-called bipolar code (AMI code).
There are many value signs.
第１図と第２図は従来の３値パルス発生回路の
例である。 FIGS. 1 and 2 are examples of conventional ternary pulse generating circuits.
第１図において、参照数字１は正極性出力に対
応するパルス入力端子、参照数字２は負極性出力
に対応するパルス入力端子、参照数字３は３値パ
ルスの出力端子、参照数字４は基準電圧端子、参
照数字５及び６は電源電圧端子、参照数字７，
８，９、はトランジスタ、参照数字１０は定電流
回路、参照数字１１は出力トランスである。 In Figure 1, reference numeral 1 is a pulse input terminal corresponding to positive polarity output, reference numeral 2 is a pulse input terminal corresponding to negative polarity output, reference numeral 3 is an output terminal for ternary pulse, and reference numeral 4 is a reference voltage. Terminals, reference numerals 5 and 6 are power supply voltage terminals, reference numeral 7,
8 and 9 are transistors, reference numeral 10 is a constant current circuit, and reference numeral 11 is an output transformer.
第１図の回路はトランジスタ３個で構成できる
ため素子数は少ないが前記入力端子１および２の
駆動源としてCML（Current Mode Logic）を使
うような周波数領域では、CMLの論理振幅が約
0.8Vと小さいために基準電圧端子４に固定の基
準電圧を与えている場合には、トランジスタのス
イツチング速度が遅くなり３値出力パルスの立上
り時間が悪いという欠点がある。 The circuit in Figure 1 can be configured with three transistors, so the number of elements is small, but in the frequency domain where CML (Current Mode Logic) is used as the drive source for input terminals 1 and 2, the logic amplitude of CML is approximately
If a fixed reference voltage is applied to the reference voltage terminal 4 because it is as small as 0.8V, there is a drawback that the switching speed of the transistor is slow and the rise time of the ternary output pulse is poor.
第２図において、参照数字１，２，３，５およ
び５，６は第１図の同一番号に対応し、参照数字
７，８はゲート、参照数字９〜１２はトランジス
タ、参照数字１３と１４は定電流回路、参照数字
１５は出力トランスである。 In FIG. 2, reference numbers 1, 2, 3, 5 and 5, 6 correspond to the same numbers in FIG. 1, reference numbers 7 and 8 are gates, reference numbers 9 to 12 are transistors, reference numbers 13 and 14 is a constant current circuit, and reference numeral 15 is an output transformer.
第２図においては電流切替回路を形成するトラ
ンジスタ９と１０及び１１と１２はそれぞれゲー
ト７と８により相補的に駆動されているために出
力波形は秀れているがトランジスタが４個必要で
あり、また、４本のコレクタをトランスに接続す
る場合に配線長が長くなる結果、出力波形をやや
劣化させるという欠点をもつている。 In FIG. 2, transistors 9 and 10 and transistors 11 and 12 forming the current switching circuit are driven complementary by gates 7 and 8, respectively, so the output waveform is excellent, but four transistors are required. Moreover, when four collectors are connected to a transformer, the wiring length becomes long, resulting in a slight deterioration of the output waveform.
本発明の目的は第１図の回路のもつ素子数の少
ないという特徴と第２図の回路のもつ電流切替回
路の相補的駆動という特徴をあわせ持つ３値パル
ス発生回路を提供することにある。 An object of the present invention is to provide a ternary pulse generating circuit which has both the feature of the circuit of FIG. 1, which has a small number of elements, and the feature of the circuit of FIG. 2, which has the feature of complementary driving of the current switching circuit.
次に図面を参照して本発明を詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.
第３図は本発明の一実施例を示し、参照数字１
〜３，５〜１１はそれぞれ第１図の同一番号に対
応する。第１図では端子４に固定の基準電圧を与
えているのに対し、第３図の端子４にはパルスが
加えられる。 FIG. 3 shows an embodiment of the invention, with reference numeral 1
-3, 5-11 correspond to the same numbers in FIG. 1, respectively. In FIG. 1, a fixed reference voltage is applied to the terminal 4, whereas in FIG. 3, a pulse is applied to the terminal 4.
第４図に第３図の回路の波形例を示す。波形
１，２，３および４の波形はそれぞれ第３図の構
成要素１，２，４、および３の波形例を示す。波
形３に示すように、第３図の端子４′には波形１
と２とNOR信号が加えられている。このように
することにより、トランジスタ７〜９で構成され
る電流切替回路は相補的に駆動されることにな
り、第１図の回路で２倍の論理振幅で電流切替回
路を駆動したのと同等の効果を生み出力波形の立
上り時間を大幅に改善することになる。また、ト
ランジスタが３個のためトランスとの接続も最短
距離で配線が可能であり、不要なインダクタンス
による波形の劣化を生じない。 FIG. 4 shows an example of waveforms for the circuit of FIG. 3. Waveforms 1, 2, 3 and 4 represent example waveforms of components 1, 2, 4 and 3 of FIG. 3, respectively. As shown in waveform 3, waveform 1 is applied to terminal 4' in FIG.
and 2 and a NOR signal are added. By doing this, the current switching circuit composed of transistors 7 to 9 will be driven in a complementary manner, which is equivalent to driving the current switching circuit with twice the logic amplitude in the circuit shown in Figure 1. This results in a significant improvement in the rise time of the force waveform. Furthermore, since there are three transistors, connection to the transformer can be made with the shortest wiring distance, and waveform deterioration due to unnecessary inductance does not occur.
第５図はユニポーラ信号をバイポーラ信号へ変
換する回路に本発明を適用した例を示す。 FIG. 5 shows an example in which the present invention is applied to a circuit that converts a unipolar signal into a bipolar signal.
第５図において、参照数字２１はデータ入力端
子、参照数字２２はクロツク入力端子、参照数字
２３は出力端子、参照数字２４〜２７はゲート、
参照数字２８はフリツプフロツプ、参照数字２９
〜３１はトランジスタ、参照数字３２〜３３は電
源電圧端子、参照数字３４は定電流回路である。 In FIG. 5, reference numeral 21 is a data input terminal, reference numeral 22 is a clock input terminal, reference numeral 23 is an output terminal, reference numerals 24 to 27 are gates,
Reference numeral 28 is a flip-flop, reference numeral 29
-31 are transistors, reference numbers 32-33 are power supply voltage terminals, and reference number 34 is a constant current circuit.
第５図の動作を第６図のタイムチヤートで示
す。 The operation of FIG. 5 is shown in the time chart of FIG. 6.
第６図において波形１〜８はそれぞれ第５図の
端子２１および２２，Ａ，Ｂ，Ｃ，Ｄ，Ｅおよび
端子２３の波形を示している。波形５，６と７か
ら明らかなようにトランジスタ２９，３０および
３１のベースは相補的に駆動されている。 In FIG. 6, waveforms 1 to 8 indicate the waveforms of terminals 21 and 22, A, B, C, D, E, and terminal 23 of FIG. 5, respectively. As is clear from waveforms 5, 6 and 7, the bases of transistors 29, 30 and 31 are driven complementary.
以上説明したように、本発明によれば少ない素
子数で立上りの速い３値パルスを得ることができ
る。 As explained above, according to the present invention, a ternary pulse with a fast rise can be obtained with a small number of elements.
なお図中CML（Current Mode Logic）に必要
な終端抵抗は省略している。 Note that the terminating resistor required for CML (Current Mode Logic) is omitted in the figure.
第１図と第２図は従来の回路例を示す図、第３
図は一本発明の実施例を示す図、第４図１〜４は
第３図の動作波形を示す図、第５図は本発明の応
用例を示す図および第６図１〜８は第５図の動作
波形図である。
第３図および第５図において、１，２，３，
４，４′，５，６，２１，２２，２３，３２，３
３は端子、７，８，９，２９，３０，３１はトラ
ンジスタ、２８はフリツプフロツプ、２４〜２７
はゲート、１０，３４は定電流回路である。
Figures 1 and 2 are diagrams showing examples of conventional circuits;
4 is a diagram showing an embodiment of the present invention, FIG. 4 is a diagram showing the operation waveforms of FIG. 3, FIG. 5 is a diagram showing an application example of the present invention, and FIG. 5 is an operation waveform diagram of FIG. 5. FIG. In Figures 3 and 5, 1, 2, 3,
4, 4', 5, 6, 21, 22, 23, 32, 3
3 is a terminal, 7, 8, 9, 29, 30, 31 is a transistor, 28 is a flip-flop, 24 to 27
is a gate, and 10 and 34 are constant current circuits.
Claims (1)
生する回路において、電流切替回路を構成する３
個のトランジスタの第１のトランジスタのベース
に正極性出力に対応するパルスを、第２のトラン
ジスタのベースに負極性出力に対応するパルス
を、第３のトランジスタのベースに前記第１と第
２のトランジスタのベース印加信号のNORパル
スを加え、前記第１と第２のトランジスタのコレ
クタにそれぞれ出力トランスの正相１次巻線と逆
相１次巻線を接続し、前記３個のトランジスタの
エミツタを定電流回路に共通に接続したことを特
徴とする３値パルス発生回路。1 In a circuit that generates three-value pulses of 0 level, positive polarity, and negative polarity, 3 that constitutes a current switching circuit
A pulse corresponding to a positive polarity output is applied to the base of the first transistor of the transistors, a pulse corresponding to a negative polarity output is applied to the base of the second transistor, and a pulse corresponding to the negative polarity output is applied to the base of the third transistor. A NOR pulse of the signal applied to the base of the transistor is applied, the positive phase primary winding and negative phase primary winding of the output transformer are connected to the collectors of the first and second transistors, respectively, and the emitters of the three transistors are connected. A three-value pulse generation circuit characterized in that the two are commonly connected to a constant current circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP514279A JPS5597763A (en) | 1979-01-19 | 1979-01-19 | Ternary pulse generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP514279A JPS5597763A (en) | 1979-01-19 | 1979-01-19 | Ternary pulse generating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5597763A JPS5597763A (en) | 1980-07-25 |
| JPS6334658B2 true JPS6334658B2 (en) | 1988-07-12 |
Family
ID=11603044
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP514279A Granted JPS5597763A (en) | 1979-01-19 | 1979-01-19 | Ternary pulse generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5597763A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57192156A (en) * | 1981-05-22 | 1982-11-26 | Fujitsu Ltd | Pulse outputting circuit |
| JPS5836051A (en) * | 1981-08-27 | 1983-03-02 | Fujitsu Ltd | Pulse output circuit |
| US4606046A (en) * | 1983-12-27 | 1986-08-12 | At&T Bell Laboratories | Converter/line driver circuit for a line repeater |
-
1979
- 1979-01-19 JP JP514279A patent/JPS5597763A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5597763A (en) | 1980-07-25 |
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