JPS6333300B2 - - Google Patents
Info
- Publication number
- JPS6333300B2 JPS6333300B2 JP14549380A JP14549380A JPS6333300B2 JP S6333300 B2 JPS6333300 B2 JP S6333300B2 JP 14549380 A JP14549380 A JP 14549380A JP 14549380 A JP14549380 A JP 14549380A JP S6333300 B2 JPS6333300 B2 JP S6333300B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- dielectric
- substrate
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000012535 impurity Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
この発明は集積回路構造の半導体装置に関し、
特にその基板電位の供給手段を改良したものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having an integrated circuit structure;
In particular, the means for supplying the substrate potential has been improved.
従来のこの種の半導体装置の構成断面を第１図
に示してある。この第１図において、１はｐ形半
導体基板、２はn+形埋込み領域、３はこれらの
上に成長されたn-形エピタキシヤル層、４ａ，
４ｂは誘電体領域に接する半導体界面の導電形反
転を防止するために、層３を貫いて基板１に達す
るように形成されたp+形領域、５は領域４ｂに
連なるp+形領域、６，７および８はそれぞれn+
形コレクタ領域、n+形エミツク領域およびp+形
ベース領域、９，１０および１１はこれらの各電
極であつて、トランジスタを構成しており、また
１２は領域５に設けられて基板１に電位を供給す
るための電極、１３ａ，１３ｂはトランジスタの
周囲を囲んで同一領域として連なり、層３中に深
く形成された酸化シリコンなどの誘電体領域であ
り、この構成にあつて基板１への電位は、領域１
２からp+形領域５および４ｂを介して供給する
ようになつている。なお１４は主表面を覆う誘電
体層である。 A cross section of a conventional semiconductor device of this type is shown in FIG. In FIG. 1, 1 is a p-type semiconductor substrate, 2 is an n + type buried region, 3 is an n - type epitaxial layer grown thereon, 4a,
4b is a p + type region formed to penetrate through layer 3 and reach substrate 1 in order to prevent conductivity type reversal at the semiconductor interface in contact with the dielectric region; 5 is p + type region continuous with region 4b; 6 , 7 and 8 are each n +
The electrodes 9, 10 and 11 of the collector region, n + type emitter region and p + type base region constitute a transistor, and 12 is provided in the region 5 to apply a potential to the substrate 1. The electrodes 13a and 13b for supplying the potential of is area 1
2 through p + type regions 5 and 4b. Note that 14 is a dielectric layer covering the main surface.
このように従来装置では、基板１への電位供給
のために、主表面にまで拡張されたp+形領域５
を形成する必要があるばかりか、このp+形領域
５とトランジスタp+形ベース領域８とが接触し
て電気的に短絡される惧れがあり、さらにこれに
よつてトランジスタの微細化に限界を生ずるなど
の欠点があつた。 In this way, in the conventional device, in order to supply potential to the substrate 1, the p + type region 5 extended to the main surface
Not only is it necessary to form a p + -type region 5 and the transistor p + -type base region 8 , there is a risk of electrical short-circuiting due to contact, and this also limits the miniaturization of transistors. There were drawbacks such as the occurrence of
この発明は従来のこのような欠点に鑑み、誘電
体分離による集積回路構造において、主表面側よ
り基板に電位を供給するための電極装置を提供し
ようとするものであり、以下、この発明の一実施
例につき、第２図を参照して詳細に説明する。 In view of these conventional drawbacks, the present invention seeks to provide an electrode device for supplying a potential to a substrate from the main surface side in an integrated circuit structure using dielectric separation. An embodiment will be described in detail with reference to FIG.
第２図実施例において前記第１図従来例と同一
符号は同一または相当部分を示しており、また１
５は前記誘電体領域１３ｂに電位を与えるための
電極、１６はこれによつて形成されるn-形エピ
タキシヤル層３中でのｐ形半導体領域、１７は基
板１に電位を供給するための電極である。 In the embodiment shown in FIG. 2, the same reference numerals as in the conventional example shown in FIG. 1 indicate the same or corresponding parts, and 1
5 is an electrode for supplying a potential to the dielectric region 13b; 16 is a p-type semiconductor region in the n - type epitaxial layer 3 formed thereby; 17 is an electrode for supplying a potential to the substrate 1; It is an electrode.
しかしてこの実施例構造は、不純物濃度が101.5
１／cm3のｐ形半導体基板１にn+形埋込み領域２
を形成し、かつこれらの上に不純物濃度が５×
10151／cm3のn-形エピタキシヤル層３を1.6μｍの
厚さにを形成した上で、エツチングなどにより主
表面上から基板１に達する溝を切り、その後、拡
散またはイオン注入により不純物濃度が10141／
cm3のp+形の薄い層４ａ，４ｂを底部中心に形成
させる。本実施例では、このp+形領域４ａ，４
ｂの底部はn-形エピタキシヤル層３の下面から
0.5μｍ程度下方まで達するものとする。ついで溝
内に誘電体領域１３ａ，１３ｂおよび誘電体層１
４を形成する。誘電体領域１３ａ，１３ｂは、
n-形エピタキシヤル層３の表面からn-形エピタ
キシヤル層３の厚みと同程度の深さ（1.6μｍ）ま
で、最上部において約9μｍの幅で、素子領域を
囲むように形成されている。つまり、上から見た
場合、幅9μｍの帯状の誘電体領域が素子領域を
とり巻いている形で、誘電体領域１３ａと１３ｂ
とは相互に連結している。なお、誘電体領域１３
ａ，１３ｂは、n-形エピタキシヤル層３の表面
から下部に行くほど、その幅が狭くなつており、
そのまわりをp+形領域４ａ，４ｂが囲むように
構成されている。その結果、p+形領域４ａ，４
ｂの最上部は、n-形エピタキシヤル層３の表面
から約0.2μｍの深さに位置している。その後、n+
形コレクタ、エミツク領域６，７およびp+形ベ
ース領域８を形成させる。p+形ベース領域８は、
深さを0.4μｍとし、誘電体領域１３ｂから5.0μｍ
の間隙をおいて形成する。最後に各電極９，１
０，１１および１５，１７を形成する。電極１５
は、幅が約4.0μｍの帯状で、第２図において紙面
にほぼ垂直方向に延在する。電極１７は、電極１
５に対し、約2.0μｍの間隙をおいてほぼ平行に延
在し、その幅は約3.0μｍであるものとする。 However, in the example structure of the lever, the impurity concentration is 10 1.5
1/cm 3 p-type semiconductor substrate 1 with n + type buried region 2
are formed, and an impurity concentration of 5× is formed on these.
After forming an n - type epitaxial layer 3 of 10 15 1/cm 3 to a thickness of 1.6 μm, a groove is cut from the main surface to the substrate 1 by etching or the like, and then impurities are added by diffusion or ion implantation. The concentration is 10 14 1/
A p + type thin layer 4a, 4b of cm 3 is formed at the center of the bottom. In this embodiment, these p + type regions 4a, 4
The bottom of b is from the bottom surface of the n -type epitaxial layer 3.
It shall reach down to about 0.5 μm. Next, dielectric regions 13a, 13b and dielectric layer 1 are formed in the groove.
form 4. The dielectric regions 13a and 13b are
It is formed from the surface of the n -type epitaxial layer 3 to a depth (1.6 μm) similar to the thickness of the n -type epitaxial layer 3, with a width of about 9 μm at the top, so as to surround the element region. . That is, when viewed from above, a band-shaped dielectric region with a width of 9 μm surrounds the element region, and dielectric regions 13a and 13b are formed.
are interconnected. Note that the dielectric region 13
The widths of a and 13b become narrower from the surface of the n - type epitaxial layer 3 toward the bottom.
It is configured such that p + -shaped regions 4a and 4b surround it. As a result, p + shaped regions 4a, 4
The top of b is located at a depth of approximately 0.2 μm from the surface of the n - type epitaxial layer 3. Then n +
A type collector, an emitter region 6, 7 and a p + type base region 8 are formed. The p + type base region 8 is
The depth is 0.4 μm, and the distance is 5.0 μm from the dielectric region 13b.
Form with a gap of . Finally, each electrode 9,1
0,11 and 15,17 are formed. Electrode 15
has a band shape with a width of about 4.0 μm, and extends in a direction substantially perpendicular to the plane of the paper in FIG. Electrode 17 is electrode 1
5, it extends approximately parallel to the gap of approximately 2.0 μm, and its width is approximately 3.0 μm.
そしてこの実施例構成において、基板１への電
位は次のようにして与えられる。すなわち、電極
１５にn-形エピタキシヤル層３の電位よりも低
い電位を与えると、誘電体領域４ｂ付近の層３の
導電形がｐ形に反転して領域１６となり、この反
転した領域１６とp+形領域４ｂを介して電極１
７と基板１との間に導電性が確保され、電極１７
から基板１に電位を供給することができるもので
ある。例えば、n-形エピタキシヤル層３の電位
（すなわち電極９に与えられる電圧）が約5Vのと
きに、電極１５に−5Vの電圧を印加した状態で、
電極１７に0Vの電圧を印加することにより、基
板１の電位を0Vとすることができた。 In the configuration of this embodiment, the potential to the substrate 1 is applied as follows. That is, when a potential lower than the potential of the n - type epitaxial layer 3 is applied to the electrode 15, the conductivity type of the layer 3 near the dielectric region 4b is inverted to p-type and becomes a region 16, and this inverted region 16 and Electrode 1 via p + type region 4b
Conductivity is ensured between the electrode 17 and the substrate 1, and the electrode 17
It is possible to supply a potential to the substrate 1 from the source. For example, when the potential of the n -type epitaxial layer 3 (that is, the voltage applied to the electrode 9) is about 5V, with a voltage of -5V applied to the electrode 15,
By applying a voltage of 0V to the electrode 17, the potential of the substrate 1 could be set to 0V.
以上詳述したようにこの発明によれば、誘電体
領域への電位供給によりその周囲に形成される反
転領域を通して主表面側から基板電位を供給する
ようにしたから、基板を絶縁物上に固定したり、
チツプを主表面側で容器に固定したりする場合に
あつても基板電位の供給が可能になると共に、こ
の構造は従来の製造工程に新たな工程を付加する
ことなく、基板中に本来分離して構成されるべき
素子構造の一部を利用するために工程の簡略化を
図ることができ、さらに反転領域は誘電体領域の
付近に存在し、拡散されて広がらないために、同
一分離領域内に形成されるトランジスタのベース
領域と接触する危険性が少なくて、全体の微細化
ができるなどの特長を有するものである。 As detailed above, according to the present invention, since the substrate potential is supplied from the main surface side through the inversion region formed around the dielectric region by supplying the potential to the dielectric region, the substrate is fixed on the insulator. or
In addition to making it possible to supply a substrate potential even when the chip is fixed to a container on the main surface side, this structure does not require adding any new steps to the conventional manufacturing process, and allows the chip to be separated into the substrate. The process can be simplified by using a part of the device structure that should be constructed with This feature has the advantage that there is little risk of contact with the base region of the transistor formed in the substrate, and the entire structure can be miniaturized.
第１図は従来例による半導体装置の構成を示す
断面図、第２図はこの発明の一実施例による半導
体装置の構成を示す断面図である。
１……ｐ形半導体基板、２……n+形埋込み領
域、３……n-形エピタキシヤル層、４ａ，４ｂ
……p+形領域、６，７，８……n+形コレクタ、
n+形エミツタ、p+形ベースの各層、９，１０，
１１，１２，１５，１７……電極、１３ａ，１３
ｂ……誘電体領域、１６……ｐ形反転領域。
FIG. 1 is a sectional view showing the structure of a conventional semiconductor device, and FIG. 2 is a sectional view showing the structure of a semiconductor device according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...p-type semiconductor substrate, 2...n + type buried region, 3...n - type epitaxial layer, 4a, 4b
...p + shape area, 6, 7, 8...n + shape collector,
n + type emitter, p + type base layers, 9, 10,
11, 12, 15, 17... electrode, 13a, 13
b...dielectric region, 16...p-type inversion region.
Claims (1)
置において、第１導電形の半導体基板とその主表
面上の電極との間に、誘電体に与えられる電位に
より、この誘電体周囲の第２導電形の領域に形成
される第１導電形の反転領域を介して電気的導通
を得られるようにしたことを特徴とする半導体装
置。1. In a semiconductor device having an integrated circuit structure separated by a dielectric, a potential applied to the dielectric between a semiconductor substrate of a first conductivity type and an electrode on its main surface causes a second conductivity around the dielectric to increase. 1. A semiconductor device characterized in that electrical continuity can be obtained through an inverted region of a first conductivity type formed in a region of a shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14549380A JPS5769758A (en) | 1980-10-16 | 1980-10-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14549380A JPS5769758A (en) | 1980-10-16 | 1980-10-16 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5769758A JPS5769758A (en) | 1982-04-28 |
| JPS6333300B2 true JPS6333300B2 (en) | 1988-07-05 |
Family
ID=15386529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14549380A Granted JPS5769758A (en) | 1980-10-16 | 1980-10-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5769758A (en) |
-
1980
- 1980-10-16 JP JP14549380A patent/JPS5769758A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5769758A (en) | 1982-04-28 |
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