JPS63314644A - Data processor - Google Patents

Data processor

Info

Publication number
JPS63314644A
JPS63314644A JP15058787A JP15058787A JPS63314644A JP S63314644 A JPS63314644 A JP S63314644A JP 15058787 A JP15058787 A JP 15058787A JP 15058787 A JP15058787 A JP 15058787A JP S63314644 A JPS63314644 A JP S63314644A
Authority
JP
Japan
Prior art keywords
instruction
loop
queue
instruction queue
instructions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15058787A
Other languages
Japanese (ja)
Inventor
Yutaka Fujii
裕 藤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP15058787A priority Critical patent/JPS63314644A/en
Publication of JPS63314644A publication Critical patent/JPS63314644A/en
Pending legal-status Critical Current

Links

Landscapes

  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To shorten the reading time of a loop instruction and to carry out the loop instruction at a high speed with use of the repetitive execution characteristics of the loop instruction, by performing the automatic switch between an instruction queue and a loop instruction queue and at the same time extracting the instruction codes stored in both queues. CONSTITUTION:Each loop instruction is registered into a loop instruction queue 3-1. The automatic switch is carried out between an instruction queue 2 and the queue 3-1 and at the same time the instruction codes are extracted out of both queues so that the reading cycle is omitted for instructions stored in a loop. Thus it is possible to omit an action to read repetitively the loop instructions out of a memory and to shorten the reading time of the loop instructions. Then the loop instruction is carried out at a high speed with use of the repetitive execution characteristics of the loop instruction.

Description

【発明の詳細な説明】 技術分野 本発明はデータ処理装置に関し、特に先行する命令を読
出して格納する命令キューを有するデータ処理装置の命
令先行読出し制御に関する。
TECHNICAL FIELD The present invention relates to a data processing device, and more particularly to instruction advance read control for a data processing device having an instruction queue for reading and storing preceding instructions.

従来技術 従来、データ処理装置においては、先行して読出された
命令が順次命令キューの中に格納されるように命令先行
読出し制御がなされていた。
BACKGROUND OF THE INVENTION Conventionally, in data processing apparatuses, instruction advance reading control has been performed such that instructions read in advance are sequentially stored in an instruction queue.

このような従来のデータ処理装置では、ループを構成し
ている命令群に関しても毎回読出しを実行し、他の命令
と同様に命令キューに格納しており、この命令が制御に
したがって順次命令デコードおよび命令実行部へ送出さ
れるため、この命令先行読出し制御では、ループの性質
である繰返し実行の特性を利用しての高速実行が実現で
きないという欠点がある。
In such conventional data processing devices, a group of instructions forming a loop is read every time and stored in an instruction queue like other instructions, and these instructions are sequentially decoded and decoded according to control. Since the instruction is sent to the instruction execution unit, this instruction pre-read control has the disadvantage that high-speed execution cannot be realized by utilizing the repeated execution characteristic of a loop.

発明の目的 本発明は上記のような従来のものの欠点を除去すべくな
されたもので、ループ命令の読出し時間を削減すること
ができ、ループ命令の繰返し実行の特性を利用してのル
ープ命令の高速実行を実現することができるデータ処理
装置の提供を目的とする。
OBJECTS OF THE INVENTION The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional method.The present invention is capable of reducing the read time of loop instructions, and is capable of reducing the read time of loop instructions by utilizing the characteristic of repeated execution of loop instructions. The purpose of the present invention is to provide a data processing device that can realize high-speed execution.

発明の構成 本発明によるデータ処理装2は、先行する命令を読出し
て格納する命令キューを有するデータ処理装置であって
、ループを構成する命令群を格納するループ命令キュー
と、前記先行する命令に付加された付加情報が前記命令
群の前記ループ命令キューへの格納命令であることを検
出する検出手段とを設け、前記検出手段の検出結果に応
じて前記命令群を前記ループ命令キューに格納するよう
にしたことを特徴とする。
Structure of the Invention A data processing device 2 according to the present invention is a data processing device having an instruction queue for reading and storing a preceding instruction, and a loop instruction queue for storing a group of instructions constituting a loop; and a detection means for detecting that the added additional information is an instruction to store the instruction group in the loop instruction queue, and stores the instruction group in the loop instruction queue according to the detection result of the detection means. It is characterized by the following.

実施例 次に、本発明の一実施例について図面を参照して説明す
る。
Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例を示すブロック図である。図
において、本発明の一実施例によるデータ処理装置は、
システムバス11の内容を一時的に収容するプリフェッ
チ命令レジスタ1と、通常の命令キュー2と、複数のル
ープ命令キュー3−i(i=1.2.・・・・・・、n
)と、各命令キューへのセット指示や情報生成を行う先
行命令デコーダ4と、各命令キュー格納部からの出力を
選択して内部バス12に送出する命令キュー出力制御回
路5とにより構成されている。
FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, a data processing device according to an embodiment of the present invention is
A prefetch instruction register 1 that temporarily stores the contents of the system bus 11, a normal instruction queue 2, and a plurality of loop instruction queues 3-i (i=1.2..., n
), a preceding instruction decoder 4 that instructs each instruction queue to set and generates information, and an instruction queue output control circuit 5 that selects the output from each instruction queue storage section and sends it to the internal bus 12. There is.

ブリフェッチ命令レジスタ1に先行して読出された命令
がセットされると、その命令の]−ドが先行命令デコー
ダ4で判断される。
When the previously read instruction is set in the brief fetch instruction register 1, the preceding instruction decoder 4 determines the ]-code of that instruction.

このコードがループ命令キュー登録命令、すなわち、ル
ープ命令の先頭に設けられ、かつループ命令を構成する
命令群をループ命令キュー3−iに登録させるための命
令であれば、指定されたループ命令キュー3−iに指定
された語数分(ループを構成するステップ数)を収容す
るとともに、命令キュー2に格納されたループ命令直前
の命令に付加された付加情報として、次に実行されるべ
きループ命令が格納されたループ命令キュー3−iの番
号を書込んでおく。
If this code is a loop instruction queue registration instruction, that is, an instruction provided at the beginning of a loop instruction and for registering a group of instructions constituting the loop instruction in the loop instruction queue 3-i, the specified loop instruction queue 3-i contains the number of words (the number of steps constituting the loop) specified in i, and the loop instruction to be executed next as additional information added to the instruction immediately before the loop instruction stored in instruction queue 2. The number of the loop instruction queue 3-i in which the is stored is written.

通常の命令キュー2は次々に先行して読出された命令が
格納され、その内容が更新されていくが、ループ命令キ
ュー3−iはループ命令キュー登録命令を実行しないか
ぎり更新されない。このループ命令キュー登録命令によ
りループ命令キュー3−iには複数のループ命令が登録
される。
A normal instruction queue 2 stores instructions read out one after another and its contents are updated, but a loop instruction queue 3-i is not updated unless a loop instruction queue registration instruction is executed. A plurality of loop instructions are registered in the loop instruction queue 3-i by this loop instruction queue registration instruction.

命令の解釈および実行のために各命令キューから命令コ
ードを取出す場合には、通常、命令キュー2側から取出
されているが、命令キュー2内の命令実行順序情報部(
図示せず)で次の命令取出しがループ命令キュー3−i
側からの取出しと指定されれば、その指定されたときに
付加情報として書込まれた番号のループ命令キュー3−
iからループ命令を取出して、このループ命令を実行し
ていく。
When an instruction code is taken out from each instruction queue for instruction interpretation and execution, it is usually taken out from the instruction queue 2 side, but the instruction execution order information part (
(not shown), the next instruction is fetched from the loop instruction queue 3-i.
If fetching from the side is specified, the loop instruction queue 3- of the number written as additional information at the time of the specification is specified.
A loop instruction is extracted from i and this loop instruction is executed.

ループ命令を実行していくことにより、ループ命令キュ
ー3−iにループ命令が登録されるときに予めセットさ
れたループ終了フラグが検出されると、命令コードの取
出しは命令キュー2側からの取出しに戻るようになって
いる。
By executing loop instructions, if a preset loop end flag is detected when the loop instruction is registered in the loop instruction queue 3-i, the instruction code is extracted from the instruction queue 2 side. It is now back to .

また、ループ命令キュー3−iに登録された各ループ命
令は、更新されないかぎり何度でも使用することができ
る。
Furthermore, each loop instruction registered in the loop instruction queue 3-i can be used any number of times as long as it is not updated.

このように、各ループ命令をループ命令キュー3−iに
夫々登録し、命令キュー2とループ命令キュー3−iと
を自動的に切換えながらこれらに格納された命令コード
を取出すようにして、ループ内の命令の読出しサイクル
を省略することにより、図示せぬメモリから繰返し読出
しを行うという動作を不要にし、ループ命令の読出し時
間を削減することができる。これにより、ループ命令の
繰返し実行の特性を利用してのループ命令の高速実行を
実現することができる。
In this way, each loop instruction is registered in the loop instruction queue 3-i, and the instruction code stored in the instruction queue 2 and the loop instruction queue 3-i is retrieved while automatically switching between the instruction queue 2 and the loop instruction queue 3-i. By omitting the read cycle of the instructions in the loop, the operation of repeatedly reading from a memory (not shown) becomes unnecessary, and the read time of the loop instructions can be reduced. This makes it possible to realize high-speed execution of loop instructions by utilizing the characteristic of repeated execution of loop instructions.

発明の詳細 な説明したように本発明によれば、ループを構成する命
令群を格納するループ命令キューを設けて、命令キュー
とループ命令キューとを自動的に切換えながらこれ・ら
に格納された命令コードを取出すようにすることによっ
て、ループ命令の読出し時間を削減することができ、ル
ープ命令の繰返し実行の特性を利用してのループ命令の
高速実行を実現することができるという効果がある。
According to the present invention, as described in detail, a loop instruction queue is provided for storing a group of instructions constituting a loop, and the instructions are stored in the instruction queue and the loop instruction queue while being automatically switched between the instruction queue and the loop instruction queue. By extracting the instruction code, the time required to read the loop instruction can be reduced, and the loop instruction can be executed at high speed by taking advantage of the repeated execution characteristics of the loop instruction.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の構成を示すブロック図であ
る。 主要部分の符号の説明 1・・・・・・ブリフェッチ命令レジスタ2・・・・・
・命令キュー
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Explanation of codes of main parts 1...Briefetch instruction register 2...
・Instruction queue

Claims (1)

【特許請求の範囲】[Claims] 先行する命令を読出して格納する命令キューを有するデ
ータ処理装置であつて、ループを構成する命令群を格納
するループ命令キューと、前記先行する命令に付加され
た付加情報が前記命令群の前記ループ命令キューへの格
納命令であることを検出する検出手段とを設け、前記検
出手段の検出結果に応じて前記命令群を前記ループ命令
キューに格納するようにしたことを特徴とするデータ処
理装置。
A data processing device having an instruction queue for reading and storing preceding instructions, the loop instruction queue storing a group of instructions constituting a loop, and a loop instruction queue for storing a group of instructions forming a loop, and a loop instruction queue for storing a group of instructions constituting a loop; 1. A data processing apparatus, comprising: a detection means for detecting that the instruction is an instruction to be stored in an instruction queue, and the instruction group is stored in the loop instruction queue according to a detection result of the detection means.
JP15058787A 1987-06-17 1987-06-17 Data processor Pending JPS63314644A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15058787A JPS63314644A (en) 1987-06-17 1987-06-17 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15058787A JPS63314644A (en) 1987-06-17 1987-06-17 Data processor

Publications (1)

Publication Number Publication Date
JPS63314644A true JPS63314644A (en) 1988-12-22

Family

ID=15500145

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15058787A Pending JPS63314644A (en) 1987-06-17 1987-06-17 Data processor

Country Status (1)

Country Link
JP (1) JPS63314644A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006057084A1 (en) * 2004-11-25 2006-06-01 Matsushita Electric Industrial Co., Ltd. Command supply device
JP2014002736A (en) * 2012-06-15 2014-01-09 Apple Inc Loop buffer packing
US9471322B2 (en) 2014-02-12 2016-10-18 Apple Inc. Early loop buffer mode entry upon number of mispredictions of exit condition exceeding threshold
US9557999B2 (en) 2012-06-15 2017-01-31 Apple Inc. Loop buffer learning

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006057084A1 (en) * 2004-11-25 2006-06-01 Matsushita Electric Industrial Co., Ltd. Command supply device
US7822949B2 (en) 2004-11-25 2010-10-26 Panasonic Corporation Command supply device that supplies a command read out from a main memory to a central processing unit
JP2014002736A (en) * 2012-06-15 2014-01-09 Apple Inc Loop buffer packing
US9557999B2 (en) 2012-06-15 2017-01-31 Apple Inc. Loop buffer learning
US9753733B2 (en) 2012-06-15 2017-09-05 Apple Inc. Methods, apparatus, and processors for packing multiple iterations of loop in a loop buffer
US9471322B2 (en) 2014-02-12 2016-10-18 Apple Inc. Early loop buffer mode entry upon number of mispredictions of exit condition exceeding threshold

Similar Documents

Publication Publication Date Title
FI90804C (en) Controller for a data processor comprising an interrupt service utilizing redirection of advance search of instructions
KR920006275B1 (en) Data processing apparatus
US6684319B1 (en) System for efficient operation of a very long instruction word digital signal processor
JPH0682320B2 (en) Data processing device
JPS63314644A (en) Data processor
JPH11345121A (en) Instruction extracting device for program control unit and method thereof
JPS6236258B2 (en)
JPH04205448A (en) Information processor
JP2771373B2 (en) Instruction prefetch device
JP2518029B2 (en) I / O control method
JPS6232507B2 (en)
JPS60250438A (en) Information processor
JPS61289429A (en) Arithmetic processing unit
JP2766114B2 (en) Instruction prefetch device
JPH02100740A (en) Block loading operation system for cache memory unit
JPH05173785A (en) Instruction prefetching device
JPS62288974A (en) Vector processor
JPH04255995A (en) Instruction cache
JPH0439733A (en) Advance control system
JPS62114036A (en) Branch on counting control system
JPH0553798A (en) Information processor
JPH0342721A (en) Information processor
JPS60134939A (en) Data processor
JPH0752402B2 (en) Data processing device
JPS62114035A (en) Branch on counting control system