JPS63310136A - Complementary mis master slice logic integrated circuit - Google Patents

Complementary mis master slice logic integrated circuit

Info

Publication number
JPS63310136A
JPS63310136A JP62146652A JP14665287A JPS63310136A JP S63310136 A JPS63310136 A JP S63310136A JP 62146652 A JP62146652 A JP 62146652A JP 14665287 A JP14665287 A JP 14665287A JP S63310136 A JPS63310136 A JP S63310136A
Authority
JP
Japan
Prior art keywords
functional
wiring
region
cell
cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62146652A
Other languages
Japanese (ja)
Other versions
JP2742052B2 (en
Inventor
Hideki Fukuda
秀樹 福田
Masami Urano
正美 浦野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP62146652A priority Critical patent/JP2742052B2/en
Publication of JPS63310136A publication Critical patent/JPS63310136A/en
Application granted granted Critical
Publication of JP2742052B2 publication Critical patent/JP2742052B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To realize a high-speed operation by securing the flexibility during a designing operation without lowering an integration density and by securing the drive capacity of a transistor by a method wherein a wiring operation inside a functional cell or a functional macrocell and between these cells is executed by using a region of the active transistor. CONSTITUTION:A region C of an active transistor coexists without separating wiring regions A inside a functional cell or a functional macrocell constituting logic from a wiring region B between functional cells or functional macrocells. Thereby, a wiring part inside the functional cell or the functional macrocell and the wiring part between the functional cells or the functional macrocells can be installed in such a way that they coexists in the region of the active transistor by making a wiring part of a VDD power supply wiring part 10 or a ground wiring part 11 as a boundary line. If the active transistor constituting the region C is added and connected in parallel whenever necessary, the region C can be expanded. By this setup, an integration density can be enhanced; the drive capacity of the active transistor can be increased; a high-speed operation of a function of an LSI is achieved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、開発に要する期間が短く、少量多品種のＬＳ
Ｉ開発に適した相補型ＭＩＳ）ランジスタを用いたマス
タスライスＬＳＩの内、特に多機能な論理回路の構成要
素である機能マクロの搭載に適した相補型ＭＩＳマスタ
スライス論理集積回路の構成に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention requires a short period of time for development, and is suitable for the production of LS in small quantities and a wide variety of products.
Among master slice LSIs using transistors (complementary MIS suitable for I development), this article relates to the configuration of complementary MIS master slice logic integrated circuits that are especially suitable for mounting functional macros, which are components of multifunctional logic circuits. be.

〔従来の技術〕[Conventional technology]

従来の相補型ＭＩＳトランジスタを用いたマスタスライ
スＬＳＩの構成ではたとえば、第９図あるいは第１０図
に示したように２人カゲートあるいは３人カゲートの構
成に適した基本パタンセル（ベーシックパタンセル）４
を第１１図あるいは第１２図に示したようにＬＳＩチッ
プ全体にわたって規則正しく配列したものを下地バタン
として用いた。第１１図の構成は予め、基本パタンセル
４を配列したアクティブなトランジスタ領域とＬＳＩ機
能を実現するに必要な専用の配線領域７とを下地バタン
として設けておく構成である。６はＩ１０セルの枠を示
す。−力筒１２図の構成は基本パタンセル４を予め、敷
き詰めておき、その内、ＬＳＩ機能の品種展開時に必要
な量の基本パタンセルを選択して使用する構成である。In the configuration of a master slice LSI using conventional complementary MIS transistors, for example, as shown in FIG. 9 or 10, a basic pattern cell (basic pattern cell) 4 suitable for a two-person gate or three-person gate configuration is used.
As shown in FIG. 11 or 12, those arranged regularly over the entire LSI chip were used as the base batten. In the configuration shown in FIG. 11, an active transistor area in which basic pattern cells 4 are arranged and a dedicated wiring area 7 necessary for realizing the LSI function are provided in advance as a base layer. 6 indicates the frame of the I10 cell. - Power tube 12 The configuration shown in FIG. 12 is such that basic pattern cells 4 are laid out in advance, and from among them, the required amount of basic pattern cells are selected and used when developing types of LSI functions.

第１１図、第１２図の構成を含めこれら相補型ＭＩＳマ
スタスライスにおいては下地バタンまでの工程まで製造
したものをあらかじめ用意しておき、品種展開の必要が
生じた時に、上記基本セルを構成するトランジスタ間を
接続する配線工程を行ない、必要なＬＳＩ機能を実現し
ていた。通常のａ雑さを有する論理機能をＬＳＩで実現
する場合、チップ面積の６０〜７０％程度は、上記トラ
ンジスタ間を１１図に示したように配線に必要な領域を
基本パタンセル間に設けたり、あるいは第１２図の例の
ように未使用の基本パタンセル上を、上記配線を通すた
めに使用する構成が用いられていた。These complementary MIS master slices, including the configurations shown in Figures 11 and 12, are manufactured up to the base batting process and are prepared in advance, and when the need for product development arises, the above basic cells can be configured. The necessary LSI functions were achieved by performing a wiring process to connect transistors. When realizing a logic function with normal complexity using an LSI, about 60 to 70% of the chip area is allocated between the above transistors by providing the areas necessary for wiring between the basic pattern cells as shown in Figure 11. Alternatively, as in the example shown in FIG. 12, a configuration has been used in which an unused basic pattern cell is used to pass the wiring.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の相補型ＭＩＳＩ−ランジスタを用いたマスタスラ
イスＬＳＩの構成では、チップ当りの搭載ゲート規模を
大きくしようとすると、たとえば第１１図の構成例では
配線領域として予め用意してお（領域を十分に確保でき
ないため、設計の融通性が損なわれたり、第１２図の構
成例では基本セルを構成するトランジスタをできるだけ
小形にする必要があるため、比較的小形のＭＩＳ）ラン
ジスタが長い配ｙＡ（重い負荷）を駆動する構成となり
やすく、一般に配線負荷依存性が大きい傾向を有するＭ
ＩＳ）ランジスタの場合にはゲート当りの遅延時間が大
きくなる要因となっていた。このように、従来の相補型
ＭＩＳマスタスライスの構成では高集積化と設計時の融
通性の向上、あるいは高集積化と高速化の両立が図りに
くい欠点を有していた。In the configuration of a master slice LSI using conventional complementary MISI transistors, when attempting to increase the scale of mounted gates per chip, for example, in the configuration example shown in FIG. In the configuration example shown in Figure 12, it is necessary to make the transistors constituting the basic cell as small as possible. ), and generally has a tendency to have a large wiring load dependence.
IS) In the case of transistors, this is a factor that increases the delay time per gate. As described above, the conventional complementary MIS master slice configuration has the drawback that it is difficult to achieve both high integration and flexibility during design, or high integration and high speed.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は従来の問題点を解決し、相補型ＭＩＳマスタス
ライスの集積度を低下させずに設計時の融通性を確保し
、かつトランジスタの駆動能力を確保して高速化が可能
な構成の相補型Ｍｉｓマスタスライス論理集積回路を提
供することを目的とし、複数の第１のゲート群が横切る
Ｐ型拡散領域と、複数の第２のゲート群が横切るＮ型拡
散領域とを有する基本パタンセルを具備し、単数または
複数の前記基本パタンセルにより機能マクロを形成し、
前記Ｐ型拡散領域の一部および前記Ｎ型拡散領域の一部
を前記機能マクロ内の配線領域とし、前記Ｐ型拡散領域
の残部および前記Ｎ型拡散領域の残部を前記機能マクロ
間の配線領域として配線を行う構成を備えたことを特徴
とする。The present invention solves the problems of the conventional MIS master slice, and provides a complementary MIS master slice with a complementary configuration that ensures flexibility during design without reducing the degree of integration, and that ensures high-speed driving capability of transistors. The present invention aims to provide a type Mis master slice logic integrated circuit, and includes a basic pattern cell having a P-type diffusion region traversed by a plurality of first gate groups and an N-type diffusion region traversed by a plurality of second gate groups. and forming a functional macro by one or more of the basic pattern cells,
A part of the P-type diffusion region and a part of the N-type diffusion region are used as a wiring area within the functional macro, and the remaining part of the P-type diffusion area and the remaining part of the N-type diffusion area are used as a wiring area between the functional macros. It is characterized by having a configuration in which wiring is performed as follows.

〔作　用〕[For production]

従来の相補型マスタスライスにおいては、機能セルある
いは論理を構成する機能マクロ内の配線領域Ａと機能セ
ルあるいは機能マクロ間の配線領域Ｂが分離され、上記
配線領域Ｂに、基本パタンセル間に設けた配線領域、あ
るいは未使用の基本バタンの領域をあてる構成であった
。これに対し本発明においては上記配線領域Ａと配線領
域Ｂを分離することなく、上記機能セルあるいは機能マ
クロを構成する基本パタンセルの領域、即ちアクティブ
なトランジスタの領域Ｃに共存させ、必要に応じて領域
Ｃを構成するアクティブなトランジスタを並列に追加接
続することによって領域Ｃを拡大できる構成であり、こ
の点に従来の構成との間に差異がある。以下図面にもと
づき実施例について説明する。In the conventional complementary master slice, a wiring area A within a functional macro constituting a functional cell or logic and a wiring area B between functional cells or functional macros are separated, and in the wiring area B, a pattern is provided between basic pattern cells. It was configured to use the wiring area or the unused basic button area. On the other hand, in the present invention, the wiring area A and the wiring area B are not separated, but are made to coexist in the area of the basic pattern cell constituting the functional cell or functional macro, that is, the area C of the active transistor. This is a configuration in which the area C can be expanded by additionally connecting active transistors forming the area C in parallel, and this point is different from the conventional configuration. Examples will be described below based on the drawings.

（実施例〕 本発明の実施例として、その基本パタンセルの構成例を
第１図に示す。破線内が基本パタンセルの基本単位であ
る。１はＰ型Ｍｉｓ）ランジスタ部分であり、２はＮ型
Ｍｉｓ）ランジスタ部分であり、３の斜線部分はポリシ
リコンゲートである。(Example) As an example of the present invention, an example of the configuration of a basic pattern cell is shown in FIG. Mis) is a transistor part, and the shaded part 3 is a polysilicon gate.

Ｎ基板への電源電圧あるいはＰ−ウェルへの接地電圧を
供給するＮ゛拡散領域８あるいはＰ゛拡散領域９をＭＩ
Ｓトランジスタの両側に配置してある。Ｐ型あるいはＮ
型ＭＩＳ）ランジスタの間に３本のポリシリコン配線５
を予め配置し、機能セル、あるいは機能マクロ内の配線
に用いる。本実施例では、基本パタンセル−個で入力数
４以下の基本ゲートを容易に構成することができる。５
の斜線部分はＰ型のＭＩＳ）ランジスタとＮ型のＭＩｓ
）ランジスタの間に配置されたポリシリコン配線であり
、４で示した破線は基本パタンセルの枠である。第１図
に示した基本パタンセルのチップ上での配列方法を第２
図に示す。第１図と同じ部分は同じ符号で示す。太い破
線内が基本パタンセルの基本単位である。The N' diffusion region 8 or the P' diffusion region 9, which supplies the power supply voltage to the N substrate or the ground voltage to the P-well, is connected to MI.
They are placed on both sides of the S transistor. P type or N
Type MIS) Three polysilicon wiring lines 5 between transistors
are placed in advance and used for wiring within functional cells or functional macros. In this embodiment, a basic gate having four or less inputs can be easily constructed using one basic pattern cell. 5
The shaded areas are P-type MIS) transistors and N-type MIs.
) This is a polysilicon wiring placed between the transistors, and the broken line indicated by 4 is the frame of the basic pattern cell. The second method of arranging the basic pattern cells shown in Figure 1 on a chip
As shown in the figure. The same parts as in FIG. 1 are designated by the same reference numerals. The area within the thick broken line is the basic unit of the basic pattern cell.

本発明の実施例をより具体化した例として、第１図に示
した基本パタンセルを用いて構成した４人力ＮＡＮＤゲ
ートのレイアウトの例を第３図に示す。第３図に対応す
る４人力ＮＡＮＤゲートの回路構成例を第４図に示す。As a more specific example of the embodiment of the present invention, FIG. 3 shows an example of the layout of a four-man power NAND gate constructed using the basic pattern cell shown in FIG. 1. FIG. 4 shows an example of the circuit configuration of a four-man power NAND gate corresponding to FIG. 3.

第３図でＯ印１２は一層目の金属配線１６と拡散領域１
．２あるいはポリシリコンゲート３との間を接続するコ
ンタクトを示し、◎印１３は一層目の金属配線１６と二
層目の金属配線との間（ポリシリコン配線５との間では
ない）を接続するスルーホールを示す。４人力ＮＡＮＤ
ゲートの機能を実現するための配線、すなわち機能マク
ロ内の配線はＢで示した領域内で行う、Ｐ型あるいはＮ
型Ｍｉｓ）ランジスタを構成する拡散領域の内、Ａの部
分は機能セル、あるいは機能マクロ間を接続するための
配線領域として使用する。図中、ａ、ｂ、ｃ、ｄは４人
力ＮＡＮＤゲートの入力端子、ｅで示したスルーホール
１３は４人力ＮＡＮＤゲートの出力端子であるが、この
ｅに接続される二層目の金属配線は図が繁雑になるので
省略した。第４図の端子ａ　−ｅは第３図の端子ａ　”
−ｅに対応する。In Fig. 3, the O mark 12 indicates the first layer metal wiring 16 and the diffusion region 1.
．． 2 or the polysilicon gate 3, and the ◎ mark 13 connects between the first-layer metal wiring 16 and the second-layer metal wiring (not with the polysilicon wiring 5). Shows a through hole. 4 person NAND
The wiring to realize the gate function, that is, the wiring within the functional macro, is done in the area indicated by B, and is P-type or N-type.
Of the diffusion regions constituting the type Mis) transistor, the portion A is used as a wiring region for connecting between functional cells or functional macros. In the figure, a, b, c, and d are the input terminals of the 4-person NAND gate, and the through hole 13 indicated by e is the output terminal of the 4-person NAND gate, and the second layer metal wiring is connected to this e. has been omitted because it would complicate the diagram. Terminals a - e in Figure 4 are terminals a'' in Figure 3.
-corresponds to e.

このように機能セルあるいは機能マクロ内の配と機能セ
ルあるいは機能マクロ間の配線をＶＤＤ電源配線ｌＯあ
るいはＧＮＤ接地配線１１の配線を境界線としてアクテ
ィブなトランジスタの領域に共存して設けることができ
る。より複雑な機能セルの例としてマスタスレーブ形フ
リップフロップ回路を構成したレイアウトの例を第５図
に示す。In this way, wiring within a functional cell or functional macro and wiring between functional cells or functional macros can be provided coexisting in the active transistor region using the VDD power supply wiring 10 or the GND ground wiring 11 as a boundary line. FIG. 5 shows an example of a layout in which a master-slave type flip-flop circuit is constructed as an example of a more complicated functional cell.

第３図と同じ符号は同じ部分を示す、第６図は第５図の
フリップフロップ回路の回路構成図の例である。FIG. 6 is an example of a circuit configuration diagram of the flip-flop circuit of FIG. 5, in which the same reference numerals as in FIG. 3 indicate the same parts.

第６図のフリップフロップの回路図に示す転送ゲートＴ
ＧＩ〜４を制御するクロック配線はポリシリコン配線５
と一層目の金属配線１６により、結線することによって
機能セル内の配線をＶＤＤ電源配線１０とＧＮＤ接地配
線１１とで囲まれた領域Ｂで行う構成である。第３図の
場合と同じようにスルーホールに接続される二層目の金
属配線は省略した。第５図のｆ、ｇ、ｈ、ｉのスルーホ
ールは第６図のｆ、ｇ、ｈ、ｉに対応している。Transfer gate T shown in the circuit diagram of the flip-flop in FIG.
The clock wiring that controls GI~4 is polysilicon wiring 5.
By connecting with the first layer metal wiring 16, wiring within the functional cell is performed in a region B surrounded by the VDD power supply wiring 10 and the GND ground wiring 11. As in the case of FIG. 3, the second layer of metal wiring connected to the through holes has been omitted. Through holes f, g, h, and i in FIG. 5 correspond to f, g, h, and i in FIG. 6.

より一般的な構成例として、３個の４人力ＮＡＮＤゲー
トを用いたデコーダ回路の例を第７図に、レイアウトの
例を第８図に示す。入力信号配線ｊ、に、ｌ、ｍ、ｎ、
ｏ、ｐの７本と出力信号配線のｑ、ｒ、ｓの３本は機能
セルあるいは機能マクロ間を接続する領域で配線する。As a more general configuration example, an example of a decoder circuit using three 4-person NAND gates is shown in FIG. 7, and an example layout is shown in FIG. 8. Input signal wiring j, l, m, n,
The seven wires o and p and the three output signal wires q, r and s are wired in a region connecting between functional cells or functional macros.

この場合、必要に応じて１５で示すように一層目の金属
配線を用いてＰ型Ｍｉｓ）ランジスタ１４を並列に追加
接続することによって、アクティブなトランジスタ領域
を増加し、配線領域の拡張を行う。一般に配線数が増え
る場合には構成ゲートの出力端子における負荷容量が大
きくなる傾向となる。したがって、アクティブなトラン
ジスタを並列に追加接続することによって、その駆動能
力を増大させ、ＬＳｔｉ１３能の速度的な劣化を防止す
ることができる。In this case, the active transistor area is increased and the wiring area is expanded by additionally connecting P-type Mis) transistors 14 in parallel using the first layer of metal wiring as shown by 15 as required. Generally, when the number of wiring lines increases, the load capacitance at the output terminal of the constituent gates tends to increase. Therefore, by additionally connecting active transistors in parallel, its driving capability can be increased and speed deterioration of the LSti 13 performance can be prevented.

〔発明の効果〕〔Effect of the invention〕

以上、説明したように本発明の相補型Ｍｉｓマスタスラ
イス論理集積回路はアクティブなトランジスタの領域を
用いて機能セルあるいは機能マクロ内、およびこれらの
間の配線を行う構成であり、トランジスタの領域上を機
能マクロ内に配線に使用せず、おいている領域を機能マ
ク口内配線領域として有効に使用できるので、集積度を
高めることができると同時に、配線量の増大に伴って、
アクティブなトランジスタの駆動能力を増大させること
ができ、部分的な速度の劣化を防止してＬＳＩ機能の高
速化を図れる利点がある。また従来の敷き詰め（チャネ
ルレス）型マスタスライスと同様に配線の量によって配
線領域を増減させることができ、バタンレイアウト設計
上の高い融通性もそこなうことがなく、常に１００％の
配線率を達成できる利点がある。また、従来の敷き詰め
型マスタスライスとの整合性がよ＜、機能セルライブラ
リ、自動ルータ等を大幅な変更がなく流用できる利点も
ある。As described above, the complementary Mis master slice logic integrated circuit of the present invention has a configuration in which wiring is performed within and between functional cells or functional macros using the active transistor area. The area that is not used for wiring within the functional macro can be effectively used as the internal wiring area of the functional macro, so it is possible to increase the degree of integration, and at the same time, as the amount of wiring increases,
This has the advantage of increasing the driving capability of active transistors, preventing partial speed deterioration, and increasing the speed of LSI functions. Also, like the conventional channel-less master slice, the wiring area can be increased or decreased depending on the amount of wiring, and the high flexibility of batten layout design is not compromised, and a 100% wiring rate can always be achieved. There are advantages. It also has the advantage of being highly compatible with the conventional spread-type master slice, and allowing functional cell libraries, automatic routers, etc. to be used without major changes.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例に適用する基本パタンセル、第
２図はその基本パタンセルのチップ上での配列方法を示
す図、第３図は本発明のより具体化した実施例として、
機能セルのひとつである４人力Ｎ　Ａ　Ｎ　Ｄゲートの
レイアウト例を示す図、第４図は第３図の回路図、第５
図は複数の基本パタンセルを用いて構成する機能セルの
実施例として、マスタスレーブ形フリップフロップ回路
のレイアウト例を示す図、第６図は第５図の回路図、第
７図は複数の機能セルを組合せた例として、３個の４人
力ＮＡＮＤゲートを用いたデコーダの回路図、第８図は
第７図のレイアウト例を示す図、第９図および第１０図
は従来の相補型ＭＩＳマスタスライスを構成する基本パ
タンセルの例として、それぞれ２人カゲートと３人カゲ
ートの場合を示す図、第１１図は、従来の相補型ＭＩＳ
マスタスライスのチップレイアウトの概要を示したもの
であり、専用の配線領域を予め用意した構成図、第１２
図は専用の配線領域を予め用意していない敷き詰め（チ
ャネルレス）の構成図である。 ｌ・・・Ｐ型ＭＩＳ）ランジスタ、２・・・Ｎ型Ｍ　Ｉ
　Ｓトランジスタ、３・・・ポリシリコンゲート、４・
・・基本パタンセル、５・・・ポリシリコン配線、６・
・・Ｉ１０セルの枠、７・・・専用の配線領域、８・・
・Ｐウェルへの接地電圧供給のための拡散領域、９・・
・Ｎ基板への電源電圧供給のための拡散領域、１０・・
・ＶＤＤ電源配線、１１・・・ＧＮＤ接地配線、１２・
・・拡散領域と一層目の金属配線とを接続するためのコ
ンタクトホール、１３・・・一層目の金属配線と二層目
の金属配線とを接続するためのスルーホール、１４・・
・アクティブなトランジスタの並列接続を行う領域、１
５・・・並列接続で追加するアクティブなＰ型ＭＩＳト
ランジスタ、１６・・・一層目の金属配線、ａ、ｂ、ｃ
、ｄ−４人力ＮＡＮＤゲートの入力端子、ｅ・・・４人
力ＮＡＮＤゲートの出力端子、ｆ。 と・・・マスタスレーブ型フリップフロップ回路の入力
端子、ｈ、ｉ・・・マスタスレーブ型フリップフロップ
回路の出力端子、ｊ、に、ｌ、ｍ、ｎ、ｏ。 ｐ・・・デコード回路の入力端子、ｑ、ｒ、ｓ・・・デ
コード回路の出力端子、Ａ・・・機能セルあるいは機能
マクロ間を接続するための配線領域、Ｂ・・・機能セル
あるいは機能マクロ内を接続するための配線領域 特許出願人　　　日本電信電話株式会社代理人　弁理士
　玉　蟲　久五部 （外２名） ａ　　　　ｂｃ　　　　ｄ ｂｃｄ 第　　３　　図 ＶＤＤ 尖 ＮＤ 本責明の実施例の機能セルの一例（４人力ＮＡＮＤゲー
ト）の回路図系　　４　　図 −一 の回路図 第　　７　　＠ 従来の相補型ＭＩＳマスタスライスを構成する基本パタ
ンセル例１第９図 従来の相補型ＭＩＳマスタスライスを構成する基本パタ
ンセル例２第１０図 従来の相補５Ｍｌ５マスタスライスのチップレイアウト
例１概要図第　　１１　　図FIG. 1 shows a basic pattern cell applied to an embodiment of the present invention, FIG. 2 shows a method of arranging the basic pattern cell on a chip, and FIG. 3 shows a more specific embodiment of the present invention.
A diagram showing an example of the layout of a four-man power NAND gate, which is one of the functional cells. Figure 4 is the circuit diagram of Figure 3, and Figure 5.
The figure shows a layout example of a master-slave type flip-flop circuit as an example of a functional cell configured using a plurality of basic pattern cells, FIG. 6 is a circuit diagram of FIG. 5, and FIG. As an example of a combination of the above, the circuit diagram of a decoder using three 4-person NAND gates is shown, FIG. 8 is a diagram showing an example of the layout of FIG. 7, and FIGS. 9 and 10 are a diagram of a conventional complementary MIS master slice. As an example of the basic pattern cell configuring the system, FIG.
This diagram shows an overview of the chip layout of the master slice, and is a configuration diagram with dedicated wiring areas prepared in advance.
The figure is a block diagram of a channel-less system in which a dedicated wiring area is not prepared in advance. l...P-type MIS) transistor, 2...N-type MIS)
S transistor, 3... polysilicon gate, 4...
・・Basic pattern cell, 5・Polysilicon wiring, 6・
...I10 cell frame, 7...Dedicated wiring area, 8...
・Diffusion region for supplying ground voltage to P-well, 9...
・Diffusion region for supplying power voltage to the N substrate, 10...
・VDD power supply wiring, 11...GND grounding wiring, 12.
...Contact hole for connecting the diffusion region and the first layer metal wiring, 13...Through hole for connecting the first layer metal wiring and the second layer metal wiring, 14...
・A region where active transistors are connected in parallel, 1
5... Active P-type MIS transistor added in parallel connection, 16... First layer metal wiring, a, b, c
, d-input terminal of 4-manpower NAND gate, e...output terminal of 4-manpower NAND gate, f. and...input terminals of the master-slave type flip-flop circuit, h, i...output terminals of the master-slave type flip-flop circuit, j, l, m, n, o. p...Input terminal of the decoding circuit, q, r, s...Output terminal of the decoding circuit, A...Wiring area for connecting between functional cells or functional macros, B...Functional cell or function Wiring area for connecting within macro Patent applicant Nippon Telegraph and Telephone Corporation Representative Patent attorney Tama Mushi Kugobe (2 others) a bc d bcd Figure 3 VDD Cu ND Functional cell of the embodiment of this liability Circuit diagram of an example (four-manpower NAND gate) 4 Figure-1 Circuit diagram No. 7 @ Basic pattern cell configuring a conventional complementary MIS master slice Example 1 Figure 9 Basics configuring a conventional complementary MIS master slice Pattern cell example 2 Figure 10 Chip layout example 1 of conventional complementary 5Ml5 master slice Schematic diagram Figure 11

Claims (1)

【特許請求の範囲】 複数の第１のゲート群が横切るＰ型拡散領域と、複数の
第２のゲート群が横切るＮ型拡散領域とを有する基本パ
タンセルを具備し、 単数または複数の前記基本パタンセルにより機能マクロ
を形成し、 前記Ｐ型拡散領域の一部および前記Ｎ型拡散領域の一部
を前記機能マクロ内の配線領域とし、前記Ｐ型拡散領域
の残部および前記Ｎ型拡散領域の残部を前記機能マクロ
間の配線領域として配線を行う構成を備えてなる ことを特徴とする相補型ＭＩＳマスタスライス論理集積
回路。[Scope of Claims] A basic pattern cell having a P-type diffusion region traversed by a plurality of first gate groups and an N-type diffusion region traversed by a plurality of second gate groups, one or more of the basic pattern cells forming a functional macro, using a part of the P-type diffusion region and a part of the N-type diffusion region as a wiring region in the functional macro, and using the remainder of the P-type diffusion region and the remainder of the N-type diffusion region as a wiring region. A complementary MIS master slice logic integrated circuit comprising a configuration in which wiring is performed as a wiring area between the functional macros.
JP62146652A 1987-06-12 1987-06-12 Complementary MIS master slice logic integrated circuit Expired - Fee Related JP2742052B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62146652A JP2742052B2 (en) 1987-06-12 1987-06-12 Complementary MIS master slice logic integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62146652A JP2742052B2 (en) 1987-06-12 1987-06-12 Complementary MIS master slice logic integrated circuit

Publications (2)

Publication Number Publication Date
JPS63310136A true JPS63310136A (en) 1988-12-19
JP2742052B2 JP2742052B2 (en) 1998-04-22

Family

ID=15412570

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62146652A Expired - Fee Related JP2742052B2 (en) 1987-06-12 1987-06-12 Complementary MIS master slice logic integrated circuit

Country Status (1)

Country Link
JP (1) JP2742052B2 (en)

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04287369A (en) * 1991-03-15 1992-10-12 Sharp Corp Manufacture of gate array and semiconductor integrated circuit device
JPH07153927A (en) * 1993-12-01 1995-06-16 Nec Corp Semiconductor integrated circuit
JPH0897387A (en) * 1994-09-29 1996-04-12 Nec Corp Semiconductor device
JP2001237317A (en) * 2000-02-22 2001-08-31 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device, its designing method, and computer-readable recording medium recording i/o cell library
JP2010219256A (en) * 2009-03-16 2010-09-30 Elpida Memory Inc Semiconductor device and arrangement method for compensation capacitor of semiconductor device
JP2011515841A (en) * 2008-03-13 2011-05-19 テラ イノヴェイションズ インコーポレイテッド Cross-coupled transistor layout in constrained gate level layout architecture
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8680626B2 (en) 2007-10-26 2014-03-25 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US8701071B2 (en) 2008-01-31 2014-04-15 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US8756551B2 (en) 2007-08-02 2014-06-17 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US8759985B2 (en) 2008-03-27 2014-06-24 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US8823062B2 (en) 2006-03-09 2014-09-02 Tela Innovations, Inc. Integrated circuit with offset line end spacings in linear gate electrode level
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8863063B2 (en) 2009-05-06 2014-10-14 Tela Innovations, Inc. Finfet transistor circuit
US8951916B2 (en) 2007-12-13 2015-02-10 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8966424B2 (en) 2007-03-07 2015-02-24 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US9754878B2 (en) 2006-03-09 2017-09-05 Tela Innovations, Inc. Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires
US11853673B2 (en) 2021-02-05 2023-12-26 Changxin Memory Technologies, Inc. Standard cell template and semiconductor structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6074549A (en) * 1983-09-30 1985-04-26 Fujitsu Ltd Semiconductor device
JPS62169445A (en) * 1986-01-22 1987-07-25 Nec Corp Semiconductor device
JPS62169445U (en) * 1986-04-18 1987-10-27

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6074549A (en) * 1983-09-30 1985-04-26 Fujitsu Ltd Semiconductor device
JPS62169445A (en) * 1986-01-22 1987-07-25 Nec Corp Semiconductor device
JPS62169445U (en) * 1986-04-18 1987-10-27

Cited By (93)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04287369A (en) * 1991-03-15 1992-10-12 Sharp Corp Manufacture of gate array and semiconductor integrated circuit device
JPH07153927A (en) * 1993-12-01 1995-06-16 Nec Corp Semiconductor integrated circuit
JPH0897387A (en) * 1994-09-29 1996-04-12 Nec Corp Semiconductor device
JP4629826B2 (en) * 2000-02-22 2011-02-09 パナソニック株式会社 Semiconductor integrated circuit device
JP2001237317A (en) * 2000-02-22 2001-08-31 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device, its designing method, and computer-readable recording medium recording i/o cell library
US9859277B2 (en) 2006-03-09 2018-01-02 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US8921897B2 (en) 2006-03-09 2014-12-30 Tela Innovations, Inc. Integrated circuit with gate electrode conductive structures having offset ends
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US10230377B2 (en) 2006-03-09 2019-03-12 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US9741719B2 (en) 2006-03-09 2017-08-22 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US10217763B2 (en) 2006-03-09 2019-02-26 Tela Innovations, Inc. Semiconductor chip having region including gate electrode features of rectangular shape on gate horizontal grid and first-metal structures of rectangular shape on at least eight first-metal gridlines of first-metal vertical grid
US10186523B2 (en) 2006-03-09 2019-01-22 Tela Innovations, Inc. Semiconductor chip having region including gate electrode features formed in part from rectangular layout shapes on gate horizontal grid and first-metal structures formed in part from rectangular layout shapes on at least eight first-metal gridlines of first-metal vertical grid
US10141335B2 (en) 2006-03-09 2018-11-27 Tela Innovations, Inc. Semiconductor CIP including region having rectangular-shaped gate structures and first metal structures
US9425145B2 (en) 2006-03-09 2016-08-23 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US10141334B2 (en) 2006-03-09 2018-11-27 Tela Innovations, Inc. Semiconductor chip including region having rectangular-shaped gate structures and first-metal structures
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US9917056B2 (en) 2006-03-09 2018-03-13 Tela Innovations, Inc. Coarse grid design methods and structures
US8952425B2 (en) 2006-03-09 2015-02-10 Tela Innovations, Inc. Integrated circuit including at least four linear-shaped conductive structures having extending portions of different length
US8946781B2 (en) 2006-03-09 2015-02-03 Tela Innovations, Inc. Integrated circuit including gate electrode conductive structures with different extension distances beyond contact
US8823062B2 (en) 2006-03-09 2014-09-02 Tela Innovations, Inc. Integrated circuit with offset line end spacings in linear gate electrode level
US9905576B2 (en) 2006-03-09 2018-02-27 Tela Innovations, Inc. Semiconductor chip including region having rectangular-shaped gate structures and first metal structures
US8921896B2 (en) 2006-03-09 2014-12-30 Tela Innovations, Inc. Integrated circuit including linear gate electrode structures having different extension distances beyond contact
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9425273B2 (en) 2006-03-09 2016-08-23 Tela Innovations, Inc. Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the same
US9754878B2 (en) 2006-03-09 2017-09-05 Tela Innovations, Inc. Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires
US9711495B2 (en) 2006-03-09 2017-07-18 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9240413B2 (en) 2006-03-09 2016-01-19 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US9425272B2 (en) 2006-03-09 2016-08-23 Tela Innovations, Inc. Semiconductor chip including integrated circuit including four transistors of first transistor type and four transistors of second transistor type with electrical connections between various transistors and methods for manufacturing the same
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US9673825B2 (en) 2006-03-09 2017-06-06 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US9589091B2 (en) 2006-03-09 2017-03-07 Tela Innovations, Inc. Scalable meta-data objects
US9633987B2 (en) 2007-03-05 2017-04-25 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US10074640B2 (en) 2007-03-05 2018-09-11 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8966424B2 (en) 2007-03-07 2015-02-24 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9910950B2 (en) 2007-03-07 2018-03-06 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9595515B2 (en) 2007-03-07 2017-03-14 Tela Innovations, Inc. Semiconductor chip including integrated circuit defined within dynamic array section
US9424387B2 (en) 2007-03-07 2016-08-23 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US8756551B2 (en) 2007-08-02 2014-06-17 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US8759882B2 (en) 2007-08-02 2014-06-24 Tela Innovations, Inc. Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos
US10734383B2 (en) 2007-10-26 2020-08-04 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US8680626B2 (en) 2007-10-26 2014-03-25 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US9818747B2 (en) 2007-12-13 2017-11-14 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US10461081B2 (en) 2007-12-13 2019-10-29 Tel Innovations, Inc. Super-self-aligned contacts and method for making the same
US9281371B2 (en) 2007-12-13 2016-03-08 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8951916B2 (en) 2007-12-13 2015-02-10 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9202779B2 (en) 2008-01-31 2015-12-01 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US8701071B2 (en) 2008-01-31 2014-04-15 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US9530734B2 (en) 2008-01-31 2016-12-27 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US8785979B2 (en) 2008-03-13 2014-07-22 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with two inside positioned gate contacts and two outside positioned gate contacts and electrical connection of cross-coupled transistors through same interconnect layer
US8853794B2 (en) 2008-03-13 2014-10-07 Tela Innovations, Inc. Integrated circuit within semiconductor chip including cross-coupled transistor configuration
US9208279B2 (en) 2008-03-13 2015-12-08 Tela Innovations, Inc. Semiconductor chip including digital logic circuit including linear-shaped conductive structures having electrical connection areas located within inner region between transistors of different type and associated methods
US10727252B2 (en) 2008-03-13 2020-07-28 Tela Innovations, Inc. Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same
US10658385B2 (en) 2008-03-13 2020-05-19 Tela Innovations, Inc. Cross-coupled transistor circuit defined on four gate electrode tracks
US10651200B2 (en) 2008-03-13 2020-05-12 Tela Innovations, Inc. Cross-coupled transistor circuit defined on three gate electrode tracks
US9117050B2 (en) 2008-03-13 2015-08-25 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications
US9081931B2 (en) 2008-03-13 2015-07-14 Tela Innovations, Inc. Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track and gate node connection through single interconnect layer
US8872283B2 (en) 2008-03-13 2014-10-28 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature
US8866197B2 (en) 2008-03-13 2014-10-21 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through another transistor forming gate level feature
JP2011515841A (en) * 2008-03-13 2011-05-19 テラ イノヴェイションズ インコーポレイテッド Cross-coupled transistor layout in constrained gate level layout architecture
US8669595B2 (en) 2008-03-13 2014-03-11 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position, alignment, and offset specifications
US8669594B2 (en) 2008-03-13 2014-03-11 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within at least twelve gate level feature layout channels
US10020321B2 (en) 2008-03-13 2018-07-10 Tela Innovations, Inc. Cross-coupled transistor circuit defined on two gate electrode tracks
US8853793B2 (en) 2008-03-13 2014-10-07 Tela Innovations, Inc. Integrated circuit including gate electrode level region including cross-coupled transistors having gate contacts located over inner portion of gate electrode level region and offset gate level feature line ends
US8847331B2 (en) 2008-03-13 2014-09-30 Tela Innovations, Inc. Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures
US8847329B2 (en) 2008-03-13 2014-09-30 Tela Innovations, Inc. Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner positioned gate contacts
US8680583B2 (en) 2008-03-13 2014-03-25 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within at least nine gate level feature layout channels
US8836045B2 (en) 2008-03-13 2014-09-16 Tela Innovations, Inc. Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track
US8835989B2 (en) 2008-03-13 2014-09-16 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate electrode placement specifications
JP2014158036A (en) * 2008-03-13 2014-08-28 Tela Innovations Inc Cross-coupled transistor layouts in restricted gate level layout architecture
US9213792B2 (en) 2008-03-13 2015-12-15 Tela Innovations, Inc. Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods
US8816402B2 (en) 2008-03-13 2014-08-26 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate level feature layout channel including single transistor
US8785978B2 (en) 2008-03-13 2014-07-22 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with electrical connection of cross-coupled transistors through same interconnect layer
US9871056B2 (en) 2008-03-13 2018-01-16 Tela Innovations, Inc. Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same
US8772839B2 (en) 2008-03-13 2014-07-08 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer
US8729643B2 (en) 2008-03-13 2014-05-20 Tela Innovations, Inc. Cross-coupled transistor circuit including offset inner gate contacts
US8735995B2 (en) 2008-03-13 2014-05-27 Tela Innovations, Inc. Cross-coupled transistor circuit defined on three gate electrode tracks with diffusion regions of common node on opposing sides of same gate electrode track
US9779200B2 (en) 2008-03-27 2017-10-03 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US8759985B2 (en) 2008-03-27 2014-06-24 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
JP2010219256A (en) * 2009-03-16 2010-09-30 Elpida Memory Inc Semiconductor device and arrangement method for compensation capacitor of semiconductor device
US8669605B2 (en) 2009-03-16 2014-03-11 Yoshiaki Shimizu Semiconductor device and arrangement method of compensation capacitor of semiconductor device
US10446536B2 (en) 2009-05-06 2019-10-15 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8863063B2 (en) 2009-05-06 2014-10-14 Tela Innovations, Inc. Finfet transistor circuit
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9530795B2 (en) 2009-10-13 2016-12-27 Tela Innovations, Inc. Methods for cell boundary encroachment and semiconductor devices implementing the same
US9269702B2 (en) 2009-10-13 2016-02-23 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US9704845B2 (en) 2010-11-12 2017-07-11 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US11853673B2 (en) 2021-02-05 2023-12-26 Changxin Memory Technologies, Inc. Standard cell template and semiconductor structure

Also Published As

Publication number Publication date
JP2742052B2 (en) 1998-04-22

Similar Documents

Publication Publication Date Title
JPS63310136A (en) Complementary mis master slice logic integrated circuit
CA2126479C (en) Symmetrical multi-layer metal logic array with continuous substrate taps and extension portions for increased gate density
JP4036688B2 (en) Standard cell library for automatic placement and routing and semiconductor integrated device
KR101690170B1 (en) Custom integrated circuit
US4602270A (en) Gate array with reduced isolation
EP0563973B1 (en) Master slice integrated circuit having a reduced chip size and a reduced power supply noise
JPH0247862B2 (en)
EP0189183B1 (en) Semiconducteur integrated circuit device
EP0119059B1 (en) Semiconductor integrated circuit with gate-array arrangement
US5206529A (en) Semiconductor integrated circuit device
JPH0831581B2 (en) Semiconductor device
JPH0252428B2 (en)
US5701021A (en) Cell architecture for mixed signal applications
JPH10173055A (en) Cell-based semiconductor device and standard cell
JPH023279A (en) Standard cell of complementary mis master slice lsi
JPS6290948A (en) Semiconductor integrated circuit device
US6483131B1 (en) High density and high speed cell array architecture
JPS63140A (en) Semiconductor integrated circuit device
JPH0475664B2 (en)
JPS60110137A (en) Semiconductor device
JPH02102571A (en) Semi-custom semiconductor integrated circuit
JPS59132144A (en) Manufacture of semiconductor integrated circuit device
JPS624343A (en) Master-slice-type semiconductor integrated circuit device
JPH0427159A (en) Semiconductor device
JPH0774252A (en) Semiconductor integrated circuit

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees