JPS63307271A - Sputtering device - Google Patents
Sputtering deviceInfo
- Publication number
- JPS63307271A JPS63307271A JP14307487A JP14307487A JPS63307271A JP S63307271 A JPS63307271 A JP S63307271A JP 14307487 A JP14307487 A JP 14307487A JP 14307487 A JP14307487 A JP 14307487A JP S63307271 A JPS63307271 A JP S63307271A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- film
- electrode
- potential
- target
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004544 sputter deposition Methods 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 82
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 15
- 238000010438 heat treatment Methods 0.000 claims abstract description 5
- 239000013077 target material Substances 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 9
- 239000010453 quartz Substances 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 238000010276 construction Methods 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000002245 particle Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000010849 ion bombardment Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 241000254032 Acrididae Species 0.000 description 1
- 241000609816 Pantholops hodgsonii Species 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001552 radio frequency sputter deposition Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
Landscapes
- Physical Vapour Deposition (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造装置に係り、特に半導体装置
に於ける配線膜を形成するためのスバッ。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device manufacturing apparatus, and particularly to a substrate for forming wiring films in semiconductor devices.
夕装置に関する。Regarding the evening equipment.
半導体装置の製造プロセスに於いて、特に配線。 In the manufacturing process of semiconductor devices, especially wiring.
膜の形成手法としては現在プレーナマグネトロン−１型
のスパッタ装置が主流を成している。元来、ス。Planar magnetron-1 type sputtering equipment is currently the mainstream method for forming films. Originally, Su.
バッタ法では第２図中段に示すごとく成膜粒子 ６２０
０がオオむね余弦則（ＣＯ８−ＬＡＷ）（７）分布２ｏ
２゜に従ってターゲット表面２０１から広い立体角に分
。In the grasshopper method, the film forming particles are 620 as shown in the middle row of Figure 2.
0 is the great cosine law (CO8-LAW) (7) Distribution 2o
2° from the target surface 201 to a wide solid angle.
布して飛び出しているので、基板へ飛来する成膜、、。Since the film is protruding from the cloth, the film is deposited onto the substrate.
粒子の入射角度はランダムである。この場合、約。The angle of incidence of particles is random. In this case, approx.
２μｍルールまでは、成膜粒子がランダムなことが基板
上に存在する凹凸（段差）部での成膜物の被覆特性（カ
バレッヂ）を満足させていた。Up to the 2 μm rule, the randomness of the deposited particles satisfied the coverage of the deposited material on the uneven (step) portions existing on the substrate.
ところがＶＬＳ Ｉの高集積化に伴い最小加工寸法が１
μｍ領域に突入すると成膜粒子がランダムなことが逆に
スルーホール３０２の段差の上端部３０３に於て成膜物
のオーバーハング２０４を形成し、これがスルーホール
開口部を狭くするというシャドウィング効果のためにス
ルーホール内部への成膜量が平担部２０５での成膜量に
比べて小さくなり力・バレツヂが悪くなる。さらにオー
バーハングが大。However, with the increasing integration of VLSI, the minimum processing size is 1
When entering the μm region, the randomness of the deposited particles conversely forms an overhang 204 of the deposited material at the upper end 303 of the step of the through hole 302, which causes a shadowing effect that narrows the opening of the through hole. Therefore, the amount of film deposited inside the through hole is smaller than the amount of film deposited on the flat portion 205, resulting in poor force and deflection. Furthermore, the overhang is large.
き（なるとスルーホール開口部を塞ぎスルーホー。When the through-hole opens, the through-hole is closed.
ル内部にボイドが残る。このため半導体の長期に。voids remain inside the tube. For this reason, in the long term of semiconductors.
亘る信頼性を向上する上でスルーホール内部の成膜量を
増加し、スルーホール内部を成膜材料で埋。In order to improve reliability over time, we increased the amount of film deposited inside the through hole and filled the inside of the through hole with a film forming material.
め込む成膜手法が必要となる。A film-forming method that incorporates this is required.
こうしたカバレツヂを向上させる手法としては、。Here are some ways to improve your coverage.
ＣＶＤ法やスルーホール自身をテーパー形状とす。The CVD method and the through hole itself are made into a tapered shape.
る等があるが、ＣＶＤ法ではＡＡ−Ｃｕ−８ｉ等の合金
７．。However, in the CVD method, alloys such as AA-Cu-8i 7. .
を組成をコントロールしながら成膜することが非。It is possible to form a film while controlling the composition.
常に困難であり、スルーホールのテーパー付ケバ。Always difficult and through-hole tapered fluff.
工程数が増加しプロセスが複雑になる等の問題があるた
めに現行の製造プロセスには適用が難しい。It is difficult to apply to current manufacturing processes because of problems such as an increase in the number of steps and a complicated process.
これに対してバイアススパッタ法はプロセスとの互換性
やこれまでの実績から有望視されている。On the other hand, the bias sputtering method is seen as promising due to its compatibility with the process and past results.
ところが、従来では層間絶縁膜の平担化を目的とし、基
板電極に高周波電力（ＲＦ電力）を投入する方法が主流
であり、この場合、基板電極の構造が複雑であったり、
カバレツヂを向上させるため、３ 。However, in the past, the mainstream method was to apply high frequency power (RF power) to the substrate electrode for the purpose of flattening the interlayer insulating film, but in this case, the structure of the substrate electrode was complicated,
3. To improve coverage.
にＲＦ電力を大きくするとデバイス特性を変動さ・せる
等の問題がある。そこでスルーホール内を成・膜材料で
埋め込むことができ、加えて簡便で且つ・デバイス特性
を変動させないスパッタ装置の開発・が望まれている。However, if the RF power is increased, there are problems such as fluctuations in device characteristics. Therefore, it is desired to develop a sputtering apparatus that can fill the inside of the through hole with a film material, is simple, and does not change the device characteristics.
なお、この種装置に関連するもうのとしては、例えば特
開昭５５−５８３７１号公報が挙。An example of a device related to this type of device is JP-A-55-58371.
げられる。can be lost.
上記従来技術ではスルーホール内部への成膜量。 In the above conventional technology, the amount of film deposited inside the through hole.
が少ないことが微小スルーホールを介した上下層、１、
配線の接続信頼性を不十分にしている問題があっ。1.
There is a problem with insufficient wiring connection reliability.
た。Ta.
本発明の目的は、簡便な構造の基板電極を具備。An object of the present invention is to provide a substrate electrode with a simple structure.
し、デバイス特性を変動させずにスルーホール内。inside the through-hole without changing the device characteristics.
部への成膜量を増大させうるスパッタ装置を提供１、す
ることにある。An object of the present invention is to provide a sputtering apparatus that can increase the amount of film deposited on a certain area.
上記目的は、スパッタ装置において、基板電極に直流電
力を印加し、該基板電極の近傍に電気的に絶縁する（フ
ロート電位）か、プラズマ電位よ・４ ・
り負の電位を印加したシールド板を設け、さらに・該基
板を加熱する手段を有することにより達成さ・れる。The above purpose is to apply direct current power to a substrate electrode in a sputtering device, and either to electrically insulate the substrate electrode (float potential) or to install a shield plate to which a potential more negative than the plasma potential is applied. This is achieved by providing and further having means for heating the substrate.
上記のスパッタ装置は、基板電極に直流電力を一印加す
るので基板電極をアース電位と絶縁させる・だけでよく
、電極構造が簡便である。In the above-mentioned sputtering apparatus, since one DC power is applied to the substrate electrode, it is only necessary to insulate the substrate electrode from the ground potential, and the electrode structure is simple.
しかし、第４図に示すように基板電極九印加す。However, as shown in FIG. 4, the substrate electrode 9 is applied.
る電圧（基板バイアス電圧であり、以下バイアス。voltage (substrate bias voltage, hereinafter referred to as bias).
電圧と略する）を負方向に太き（すると成膜した１、。Voltage (abbreviated as "voltage") increases in the negative direction (then the film is deposited 1).
膜中に放電空間中に導入するガス（通常Ａｒガスが。A gas (usually Ar gas) is introduced into the discharge space during the film.
一般的であるので以下Ａｒとする）の負イオンが吸、蔵
する。このＡｒ吸蔵量が０．５（ｗｔ％）を超えると膜
上。Because it is common, it absorbs and stores negative ions (hereinafter referred to as Ar). If the amount of Ar storage exceeds 0.5 (wt%), it will be on the film.
面にボイドやふくれが発生し、そうなると導電膜。Voids and bulges occur on the surface, which causes the conductive film.
とじて使用することができない。従って、バイア１−ス
ミ圧は−１５０（Ｖより負方向に大きくすることができ
ない。It cannot be closed and used. Therefore, the via 1-sumi pressure cannot be made greater than -150 (V) in the negative direction.
一方で直流電力により基板電極において放電な生ぜしめ
れば、基板電極に投入する電力〔基板電力とする〕は数
（Ｗ／ｄ）である。しかし放電電圧が数（ＫＶ）必要で
あり、上記バイアス電圧限界。On the other hand, if a discharge is caused in the substrate electrode by DC power, the power input to the substrate electrode (referred to as substrate power) is several (W/d). However, a discharge voltage of several kilovolts (KV) is required, which is the bias voltage limit mentioned above.
（−１５０（Ｖ’ｌ’］を越えており、使用することが
できな。(It exceeds -150 (V'l') and cannot be used.
い。stomach.
そこで、本発明では、基板電極は負の電位（バ。Therefore, in the present invention, the substrate electrode has a negative potential (bar).
イアスミ圧）を保持するのみとし、ターゲット電極によ
り発生する放電空間中の、基板及び基板電。The substrate and the substrate voltage in the discharge space generated by the target electrode.
極の近傍のプラズマ密度で決まる量のＡｒイオンを。The amount of Ar ions determined by the plasma density near the pole.
前記負電位で加速しイオシ衝撃を与えることによ。By accelerating at the negative potential and applying sulfur bombardment.
す、成膜材料をマイグレートさせて基板上のスルー。Migrate the film-forming material and deposit it on the substrate.
ホール内部へ埋め込むことを原理とする。従って、１．
１上記バイアス電圧限界〔例えば、−１５０（Ｖ）１の
範囲。The principle is to embed it inside the hole. Therefore, 1.
1 The above bias voltage limit [for example, -150 (V) 1 range.
内で、できるだけ深いバイアス電圧を印加し、最。Apply the bias voltage as deep as possible within the maximum range.
大阪の基板電力を投入する。Inject power from Osaka's circuit board.
また通常のスパッタ装置では、上記シールド板は真空処
理室内に固定するのでアース電位である。Further, in a normal sputtering apparatus, the shield plate is fixed in the vacuum processing chamber and is therefore at ground potential.
しかし上記シールド板がアース電位では基板電力は０．
７５ （Ｗ／ｆｆｌ ）程度しかとることができず、こ
れではスルーホールを埋め込むことはできない。そこで
上記シールド板を電気的に絶縁する（フロート電位）か
、プラズマ電位より負の電位とするこ２Ｃノ
とで基板電力の増加を図る。However, when the shield plate is at ground potential, the board power is 0.
75 (W/ffl), which makes it impossible to embed through holes. Therefore, the substrate power is increased by electrically insulating the shield plate (float potential) or by setting it to a potential more negative than the plasma potential.
即ち、上記シールド板がアース電位の時は該シー・ルド
板は放電のアノードの一部の働きをし、電子・が大量に
流れ込むので基板電極の近傍での電子音・度もそれに応
じて多（、逆にＡｒイオン密度は小さ−い。これに対し
て該シールド板を電気的に絶縁す・る（フロート電位）
か、プラズマ電位より負の電。That is, when the shield plate is at ground potential, the shield plate acts as a part of the anode for discharge, and a large amount of electrons flows in, so the electronic sound intensity near the substrate electrode increases accordingly. (On the contrary, the Ar ion density is small.In contrast, the shield plate is electrically insulated (float potential)
Or a charge more negative than the plasma potential.
位とすると、放電電流としての電子は上記アノ−。When it is assumed that the electrons as the discharge current are the above-mentioned anode.
ド及び真空処理室内壁を通ってアースに流れる。。It flows to ground through the ground and the inner wall of the vacuum processing chamber. .
従って、シールド板には放電中のＡｒイオンと電子とが
シールド板の電位をプラズマ電位（フロート。Therefore, the Ar ions and electrons in the discharge on the shield plate change the potential of the shield plate to a plasma potential (float).
電位）か、上記負の電位と等しくするよりに拡散。potential) or equal to the negative potential above.
してくるので、基板電極近傍に拡散してくるＡｒイ。As a result, Ar diffuses near the substrate electrode.
オン密度が相対的に増加することになる。例えば、。The on density will increase relatively. for example,.
シールド板の電位をフロート電位とすると、基板電力は
倍の１．５ （Ｗ／ｄ ）程度になる。If the potential of the shield plate is set to a float potential, the substrate power will be doubled to about 1.5 (W/d).
但し、Ａｒイオンによるイオン衝撃は堆積した膜の表面
数層のみの原子の運動をエキサイトするので、堆積した
膜のバルクとしての運動をエキサイトするために、膜の
温度な略３００℃に外部から加、７ 。However, since ion bombardment by Ar ions excites the motion of atoms in only a few layers on the surface of the deposited film, in order to excite the motion of the bulk of the deposited film, external application to the film temperature of approximately 300°C is necessary. , 7.
熱する必要がある。即ち、第２図下段に示すよう・に、
外部加熱１０９とイオン衝撃２１０とにより膜中・の原
子のモビリティを高め、イオン２１１の持つ運・動エネ
ルギーにより成膜材料を上記スルーホール・３０２内部
へマイグレート２１２させることで埋め込゛む。It needs to be heated. That is, as shown in the lower part of Figure 2,
The mobility of atoms in the film is increased by external heating 109 and ion bombardment 210, and the film-forming material is migrated 212 into the through-hole 302 by the kinetic energy of the ions 211, thereby embedding it.
以下に本発明の一実施例を図面により説明する。。 An embodiment of the present invention will be described below with reference to the drawings. .
第１図は、本発明によるスパッタ装置の一実施。FIG. 1 shows one implementation of a sputtering apparatus according to the present invention.
例の基本構成を示している。Ａｒガス導入口１０７と１
、。The basic configuration of the example is shown. Ar gas inlet 107 and 1
,.
排気口１０８とを有する真空処理室１０１内に距離５５
゜−隔てて静止対向するターゲット電極１０２と基板。A distance 55 is provided in the vacuum processing chamber 101 having an exhaust port 108.
The target electrode 102 and the substrate stand still and face each other with a distance between them.
電極１０５とを具備するプレーナマグネトロン型の。A planar magnetron type comprising an electrode 105.
スパッタ装置において、例えばターゲット電極１ｏ２゜
上にスパッタターゲットとして厚さ１０ （朋）の高純
一度Ａｌ板１０３（以下ターゲットとする）を固定し。In a sputtering apparatus, for example, a high purity Al plate 103 (hereinafter referred to as target) with a thickness of 10 mm is fixed as a sputter target on a target electrode 1o2.
一方の基板電極１０５上に配線膜を形成しようとする例
えば直径ｉ ｏ ｏ （ｍｍ）の成膜対象基板１０６（
以下基板とする）を固定し、Ａｒガス導入口１０７から
Ａｒガスを２００ｓｅｃｍ導入し、排気口１０８から所
望の排気・ ８ ・
を行って真空処理室１０１内を例えば０．５（Ｐａ）程
度の・雰囲気を保って、アノード１０４を接地し、ター
ゲラ・ト電極１０２に例えば８（ＫＷ）程度の直流電力
を直・流電源１１３により印加し、更に基板電極１０５
に ・−１２５（Ｖ）程度の直流バイアス電圧を直流定
電圧電源−１１２により印加し、ターゲット電極１０２
と基板電・極１０５との間の空間の基板電極１０５側′
に近接して・基板１０６に対応した位置に例えば開口径
１１５ （ｍｍ）の・開口１１０を有するシールド板１
００を配設し、該シー。For example, a film formation target substrate 106 (with a diameter of i o o (mm)) on which a wiring film is to be formed on one substrate electrode 105 (
(hereinafter referred to as a substrate) is fixed, Ar gas is introduced for 200 seconds from the Ar gas inlet 107, and the desired exhaust gas is performed from the exhaust port 108 to create a vacuum inside the vacuum processing chamber 101 at a pressure of, for example, about 0.5 (Pa). - While maintaining the atmosphere, the anode 104 is grounded, and DC power of, for example, about 8 (KW) is applied to the target electrode 102 by the DC power source 113, and then the substrate electrode 105 is
- Apply a DC bias voltage of about -125 (V) from a DC constant voltage power supply -112 to the target electrode 102.
and the substrate electrode 105 side of the space between the substrate electrode/electrode 105'
A shield plate 1 having an opening 110 with an opening diameter of 115 (mm), for example, at a position corresponding to the substrate 106 in proximity to the substrate 106.
00 and the sea.
ルド板１００は電気的に絶縁する（フロート電位）・か
、あるいは負の電位を印加することのできる直。The field plate 100 is either electrically insulating (float potential) or a direct current to which a negative potential can be applied.
流室電圧電源１１１を介して接地し、基板１０６の被。It is grounded through the flow chamber voltage power supply 111 and covered with the substrate 106.
成膜領域の反対側から石英ランプヒータ１０９（以下ヒ
ータとする）により該基板１０６を加熱しなか。The substrate 106 is not heated by a quartz lamp heater 109 (hereinafter referred to as a heater) from the opposite side of the film forming area.
らスパッタ成膜を行う。Perform sputtering film formation.
このようにしてスパッタ成膜を行うと基板１０６上では
ＡＪ膜の堆積と、堆積したＡｌ膜のマイグレーシ璽ンと
が同時に行われ、そのため第３図（ａｌ〜（ｃｌに示す
断面模式図のようにＡＡ膜３０１の堆積が進行し、先ず
第３図（ａｌに示すようにスルーホール３０２□の段差
部３０３に形成されている急峻なＡＪ膜３０１の・段差
３０４がなだらかに埋められ、その上に更にス・ルーホ
ール３０２を埋めるように堆積が進み、第３・図（ｂ）
次いで第３図（ｃ）に示すようにスルーホール３０２・
内にボイドを形成すること無しにＡｌ膜３０１を埋め込
むことができる（なお図中３０５は下層配線膜、・３０
６は層間絶縁膜である）。When sputtering film formation is performed in this manner, the deposition of the AJ film and the migration of the deposited Al film are performed simultaneously on the substrate 106. The deposition of the AA film 301 progresses, and first, as shown in FIG. The deposition further progresses to fill the through hole 302, as shown in Figure 3 (b).
Next, as shown in FIG. 3(c), the through hole 302.
It is possible to embed the Al film 301 without forming voids inside (in the figure, 305 is the lower wiring film, 30
6 is an interlayer insulating film).
次に、基板流入電流特性、 ｖｔｈシフト（Δｖｔｈ
＞・特性及び埋め込み性について説明する。Next, the substrate inflow current characteristics, vth shift (Δvth
＞・Explain the characteristics and embeddability.
第５図は、基板バイアス電圧を変化させた時の１．。FIG. 5 shows 1. when changing the substrate bias voltage. .
基板流入電流特性を示す。横軸はバイアス電圧間。This shows the substrate inflow current characteristics. The horizontal axis is the bias voltage.
で、縦軸は基板流入電流（３）で基板から流れだす方。The vertical axis is the substrate inflow current (3) that flows out of the substrate.
向の電流を正とする。（ターゲット印加電力は８、（Ｋ
Ｗ））。ｋイアスミ圧を負方向に増加させるこ。The current in the direction is positive. (Target applied power is 8, (K
W)). k Increase the Iasumi pressure in the negative direction.
とにより、基板流入電流は飽和傾向を示し、飽和電流値
が正方向であり、基板からアースに向けて電流が流れだ
していることから、基板に流れ込む荷電粒子は主にＡｒ
イオンである。Therefore, the current flowing into the substrate shows a saturation tendency, the saturation current value is in the positive direction, and the current starts flowing from the substrate toward the ground, so the charged particles flowing into the substrate are mainly Ar.
It is an ion.
例えばバイアス電圧が−１２５（■では、シールド板１
００の電位がアース電位の時の基板流入電流５０１が６
３０（ｍＡ） （０，７６（Ｗ／ｃＩｆｔ）、但し基板
電極面積をシー・ルド板の開口面積（１０４（ｍ））と
する）で、シールド・板の電位をフロート電位とする本
発明による基板・流入電流５００においては１２００（
ｍＡ） （１，４４（Ｗ／７）と・略２倍に増加する。For example, if the bias voltage is -125 (■, shield plate 1
When the potential of 00 is ground potential, the substrate inflow current 501 is 6
30 (mA) (0.76 (W/cIft), however, the substrate electrode area is the opening area of the shield plate (104 (m))), and the potential of the shield plate is a float potential according to the present invention. When the substrate/inflow current is 500, it is 1200 (
mA) (1,44 (W/7), which increases approximately twice as much.
次に、シールド板に負の電位を印加した場合の・基板流
入電流特性について示す。第６図は、例え・ばバイアス
電圧を−１２５（Ｖ）一定とし、シールド板１００・に
印加した負の電圧に対する基板流入電流特性を・示す。Next, the substrate inflow current characteristics when a negative potential is applied to the shield plate will be described. FIG. 6 shows, for example, the substrate inflow current characteristics with respect to the negative voltage applied to the shield plate 100, with the bias voltage constant at -125 (V).
シールド板をフロート電位（〜−２５Ｍ）とし。Set the shield plate to a float potential (~-25M).
た場合の基板流入電流６００は１２００（ｍＡ）であり
、−５０゜〜−２００（Ｖ）の範囲で負方向に増加して
も基板流入室。In this case, the substrate inflow current 600 is 1200 (mA), and even if it increases in the negative direction in the range of -50° to -200 (V), the substrate inflow current 600 is 1200 (mA).
流６０１は略１２５０（ｍＡ）でほぼ横ばいである。従
って、。The current 601 is approximately 1250 (mA) and is almost flat. Therefore,.
シールド板に負の大きな電位を印加するとシール。Seals when a large negative potential is applied to the shield plate.
ド板がスパッタされ異物を発するのと放電が不安定にな
るので、シールド板に印加する電位はフロート電位か、
それより数〜数１０関だけ負の電位である。The shield plate will sputter and emit foreign matter, and the discharge will become unstable.
The potential is several to several tens of functions more negative than that.
第７図に、基板電力が０．７６ （Ｗ／７）と１．４４
（Ｗ／ｄ）の条件において、スルーホール寸法カ１．０
〜、１．５μｍ（深さ１．１μｍ）のスルーホールに対
しＡｌ膜をス・バッタ成膜した場合の埋め込み性につい
て示す。・○は埋め込み、△はマイグレーション効果は
ある・が埋め込めず、×はボイドが形成することを示す
。・基板電力が０．７６（Ｗ／ｍ ）の場合は、スルー
ホール寸法が１．５μｍでは埋め込めるが、スルーホー
ル寸法が・小さくなるに従い埋め込み性が悪（なるのに
対し。Figure 7 shows that the board power is 0.76 (W/7) and 1.44.
Under the condition of (W/d), the through hole dimension is 1.0
The embedding property when an Al film is sputter-deposited into a 1.5 μm (depth 1.1 μm) through hole is shown below.・○ indicates embedding, △ indicates that there is a migration effect, ・ indicates that embedding is not possible, and × indicates that voids are formed. - When the substrate power is 0.76 (W/m2), a through-hole with a size of 1.5 μm can be filled, but as the through-hole size becomes smaller, the embeddability becomes worse.
て、本発明による基板電力が１．４４ （Ｗｌｃｔ＆
）の場合は、・スルーホール寸法が１．０〜１．５μｍ
においてスルーホー。Therefore, the substrate power according to the present invention is 1.44 (Wlct&
), the through hole size is 1.0 to 1.5 μm
Through-ho.
ル内を埋め込める。 １．
。You can embed the contents within the file. 1.
.
次に１本発明により（基板電力１．４４（Ｗ／ｍ） ）
、 。Next, according to the present invention (substrate power 1.44 (W/m))
, .
スルーホール寸法が１．５μｍ（深さ１．１μｒｎ）の
スルーホー。A through hole with a through hole dimension of 1.5 μm (depth 1.1 μrn).
ルを有するトランジスタにＡｌ膜をスパッタ成膜し。An Al film is sputtered onto a transistor having a gate electrode.
た場合のΔｖｔｈ特性について示す。The Δvth characteristics in the case of
第８図は、種々の実効ゲート長（Ｌｅｆｆ）に対するΔ
ｖｔｈ特性を示す。基板にＲＦ定電力 １．５（ＫＷ）
）を印加する従来型ＲＦスパッタ成膜の＃ｔｈ７０２
は、基板電力を印加しないスパッタ成膜のΔＶｔｈ ７
００フト量が略２桁大きいのに対し、本発明によるス・
１２・
バッタ成膜のΔＶｔｈ ７０１はｒｅｆｅｒｅｎｃｅと
略等しい特・性を示し、デバイス特性の変動が無い。FIG. 8 shows Δ for various effective gate lengths (Leff).
Indicates vth characteristics. RF constant power to the board 1.5 (KW)
) #th702 of conventional RF sputter deposition applying
is ΔVth of sputter film formation without applying substrate power 7
00ft is approximately two orders of magnitude larger, whereas the
12. ΔVth 701 of the batter film formation exhibits characteristics that are approximately the same as the reference, and there is no change in device characteristics.
本発明によれば、微小スルーホールへの段差部・復時性
の良好なスパッタ成膜が可能であり、半導体装置の多層
配線プロセスにおける微小スルーホー・ルを介したト下
層配線の接続信頼性を大幅に向上できる。According to the present invention, it is possible to form a film by sputtering with good reproducibility on stepped portions in minute through holes, and it is possible to improve the connection reliability of lower layer wiring through minute through holes in the multilayer interconnection process of semiconductor devices. It can be significantly improved.
第１図は本発明によるスパッタ装置の一実施例の基本構
成を示す断面模式図、第２図は本発明の。
基本原理を示す成膜断面模式図、第３図は第１図。
下段の成膜過程を示す模式図、第４図は第１図の。
基板バイアス電圧−アルゴン吸蔵量特性図、第５゜図は
第１図の基板バイナス電圧−基板流入電流特。
性図、第６図は第１図のシールド板電圧−基板流入電流
特性図、第７図は第１図の成膜埋込み性説明図、第８図
は第１図の成膜Δｖｔｈ特性図でちる。
１００・・・シールド板、１０１・・・真空容器、１０
２・・・ターゲット電極、１０３・・・ターゲット、１
０４・・・アノード、 １０５・・・基板電極、
１０６・・・基板、 １０７・・・Ａｒガス
導入口、 ・１０８・・・排気口、 １０９・
・・石英ランプヒータ、・１１０・・・開口、
１１１ 、１１２・・・直流定電圧電源、１１３・・・
直流電源。
１５゜
年 ＋ 図
妻」又バイアス電、圧−（Ｖ）
第 ５ 図
基板バイアス室’、Ｌ（Ｖ、）
も Ｚ （支）
ｏ −７ｏｂ −２００シー
兄に版の■ツ丑（Ｖつ
第 ７ 図
第８ 図
乙ｅＨ−９１宗〕FIG. 1 is a schematic cross-sectional view showing the basic configuration of an embodiment of a sputtering apparatus according to the present invention, and FIG. 2 is a schematic cross-sectional view showing the basic configuration of an embodiment of a sputtering apparatus according to the present invention. A schematic cross-sectional view of film formation showing the basic principle, FIG. 3 is similar to FIG. 1. The lower schematic diagram showing the film formation process, FIG. 4, is the same as FIG. 1. Figure 5 shows the substrate bias voltage vs. argon storage amount characteristic diagram of Figure 1. Figure 6 is the shield plate voltage vs. substrate inflow current characteristic diagram in Figure 1, Figure 7 is the film formation embedding property diagram in Figure 1, and Figure 8 is the film formation Δvth characteristic diagram in Figure 1. Chiru. 100... Shield plate, 101... Vacuum container, 10
2...Target electrode, 103...Target, 1
04... Anode, 105... Substrate electrode,
106... Substrate, 107... Ar gas inlet, 108... Exhaust port, 109...
...Quartz lamp heater, 110...Opening, 111, 112...DC constant voltage power supply, 113...
DC power supply. 15゜year + Figure 5 Bias voltage, voltage - (V) Fig. 5 Substrate bias chamber', L (V,) also Z (branch) o -7ob -200 Fig. 7 Fig. 8 EH-91 sect]
Claims (1)
ト電極と略対設する基板電極と、直流電力を前記基板電
極に印加する手段と、前記ターゲツト電極とターゲット
の浸食領域以外の前記ターゲットの外周部分とを覆いア
ース電位とするか又は正の電位とするアノードと、前記
基板電極に固定された成膜対象基板を加熱する手段と、
前記ターゲット電極と前記基板電極との間に位置し、該
基板電極側に近接して成膜時に前記成膜対象基板上の被
成膜部分が前記ターゲットに対して開口している開口部
を有するシールド板と、前記ターゲットに直流電力を直
流電源により印加してターゲット材料をスパッタし前記
成膜対象基板上に配線膜を成膜するスパッタ装置におい
て、 前記シールド板にフロート電位又は、プラズマ電位より
負の電位を印加する手段とを有するスパツタ装置。 ２、前記シールド板に電気的に絶縁する（フロート電位
）か、プラズマ電位より負の電位を印加することを特徴
とする特許請求の範囲第１項記載のスパツタ装置。 ３、前記シールド板は、成膜時に前記基板電極に固定さ
れた基板上の被成膜部が前記空間に向けて開口すること
を特徴とする特許請求の範囲第１項記載のスパツタ装置
。 ４、前記アノードに電気的に接地する（アース電位）か
、正の電位を印加することを特徴とする特許請求の範囲
第１項記載のスパッタ装置。 ５、少なくとも前記基板上に堆積した膜か、該基板が前
記基板電極に電気的に接続することを特徴とする特許請
求の範囲第１項記載のスパッタ装置。[Scope of Claims] 1. A target electrode for fixing a target, a substrate electrode substantially opposite to the target electrode, means for applying DC power to the substrate electrode, an anode that covers the outer periphery of the target and sets it to a ground potential or a positive potential, and means for heating a substrate to be film-formed fixed to the substrate electrode;
An opening is located between the target electrode and the substrate electrode, and is close to the substrate electrode, and has an opening in which a portion of the substrate to be film-formed on the film-forming target substrate is opened to the target during film formation. In a sputtering apparatus that sputters a target material by applying DC power to the shield plate and the target using a DC power source to form a wiring film on the substrate to be film-formed, the shield plate is provided with a float potential or a plasma potential that is more negative than and means for applying a potential of. 2. The sputtering apparatus according to claim 1, wherein the shield plate is electrically insulated (float potential) or a potential more negative than the plasma potential is applied. 3. The sputtering apparatus according to claim 1, wherein the shield plate has a film-formed portion on the substrate fixed to the substrate electrode opened toward the space during film formation. 4. The sputtering apparatus according to claim 1, wherein the anode is electrically grounded (earth potential) or a positive potential is applied. 5. The sputtering apparatus according to claim 1, wherein at least a film deposited on the substrate or the substrate is electrically connected to the substrate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14307487A JPS63307271A (en) | 1987-06-10 | 1987-06-10 | Sputtering device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14307487A JPS63307271A (en) | 1987-06-10 | 1987-06-10 | Sputtering device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63307271A true JPS63307271A (en) | 1988-12-14 |
Family
ID=15330311
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14307487A Pending JPS63307271A (en) | 1987-06-10 | 1987-06-10 | Sputtering device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63307271A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5202008A (en) * | 1990-03-02 | 1993-04-13 | Applied Materials, Inc. | Method for preparing a shield to reduce particles in a physical vapor deposition chamber |
| US5391275A (en) * | 1990-03-02 | 1995-02-21 | Applied Materials, Inc. | Method for preparing a shield to reduce particles in a physical vapor deposition chamber |
| JP2002220663A (en) * | 2001-01-29 | 2002-08-09 | Anelva Corp | Magnetron sputtering equipment |
-
1987
- 1987-06-10 JP JP14307487A patent/JPS63307271A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5202008A (en) * | 1990-03-02 | 1993-04-13 | Applied Materials, Inc. | Method for preparing a shield to reduce particles in a physical vapor deposition chamber |
| US5391275A (en) * | 1990-03-02 | 1995-02-21 | Applied Materials, Inc. | Method for preparing a shield to reduce particles in a physical vapor deposition chamber |
| JP2002220663A (en) * | 2001-01-29 | 2002-08-09 | Anelva Corp | Magnetron sputtering equipment |
| JP4623837B2 (en) * | 2001-01-29 | 2011-02-02 | キヤノンアネルバ株式会社 | Magnetron sputtering equipment |
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