JPS63304646A - Formation of superconductor thin film pattern - Google Patents
Formation of superconductor thin film patternInfo
- Publication number
- JPS63304646A JPS63304646A JP62139714A JP13971487A JPS63304646A JP S63304646 A JPS63304646 A JP S63304646A JP 62139714 A JP62139714 A JP 62139714A JP 13971487 A JP13971487 A JP 13971487A JP S63304646 A JPS63304646 A JP S63304646A
- Authority
- JP
- Japan
- Prior art keywords
- metal oxide
- oxide powder
- substrate
- film
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002887 superconductor Substances 0.000 title claims abstract description 28
- 239000010409 thin film Substances 0.000 title claims abstract description 25
- 230000015572 biosynthetic process Effects 0.000 title abstract description 5
- 239000010408 film Substances 0.000 claims abstract description 38
- 239000000843 powder Substances 0.000 claims abstract description 37
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 36
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000003960 organic solvent Substances 0.000 claims abstract description 8
- 238000001035 drying Methods 0.000 claims abstract 2
- 239000011248 coating agent Substances 0.000 abstract description 13
- 238000000576 coating method Methods 0.000 abstract description 13
- 239000004065 semiconductor Substances 0.000 abstract description 13
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 238000001459 lithography Methods 0.000 abstract description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 2
- 238000003672 processing method Methods 0.000 abstract 1
- 230000005669 field effect Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 238000005245 sintering Methods 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 4
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- JHIVVAPYMSGYDF-UHFFFAOYSA-N cyclohexanone Chemical compound O=C1CCCCC1 JHIVVAPYMSGYDF-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- AYJRCSIUFZENHW-UHFFFAOYSA-L barium carbonate Chemical compound [Ba+2].[O-]C([O-])=O AYJRCSIUFZENHW-UHFFFAOYSA-L 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- -1 organic acid salt Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Superconductors And Manufacturing Methods Therefor (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野コ
本発明は、超電導体薄膜の加工方法に係り、特に微細パ
ターンの形成に好適な高温超電導体薄膜パターンの形成
方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for processing a superconductor thin film, and particularly to a method for forming a high temperature superconductor thin film pattern suitable for forming fine patterns.
［従来の技術］
従来、焼結体から成る高温超電導体の薄膜を基板上に形
成する方法は、６２年４月２４日付日刊工業新聞に記載
されているように、蒸着法、スパッタ法、あるいは金属
有機酸塩を混合した有機溶媒の塗布とその焼結による方
法が試みられている。[Prior Art] Conventionally, methods for forming a thin film of a high-temperature superconductor made of a sintered body on a substrate include vapor deposition, sputtering, or Attempts have been made to apply an organic solvent mixed with a metal organic acid salt and sinter it.
さらに、上記の高温超電導体薄膜を所望の形状に加工す
るには、イオンスパッタエッチ法や王水を用いた湿式エ
ッチ法が用いられている。Furthermore, in order to process the above-mentioned high-temperature superconductor thin film into a desired shape, an ion sputter etching method or a wet etching method using aqua regia is used.
［発明が解決しようとする問題点］
上記の従来補相による焼結体から成る高温超電導体薄膜
パターンの形成方法は、パターン寸法の微細化あるいは
、通常の半導体プロセス技術との互換性の点について考
慮されておらず、高温超電導体薄膜を半導体集積回路へ
適用する上で問題となるものである。すなわち、上記の
高温超電導体薄膜を基板上の全面に形成した後に、所望
のパターン形成を行なう場合において、イオンスパッタ
エッチ法を用いた場合には、マスク材料とのエツチング
選択比が小さいためにマスク材料を厚くする必要があり
、さらに下地基板表面への損傷が大きい等の問題がある
。また、湿式法による場合には、焼結体のエツチング率
が低いために長時間を要すること、および、虚結体が粒
径１μｍ程度の多結晶体であることに起因して微細パタ
ーンの形成が困難であるという問題がある。[Problems to be Solved by the Invention] The method for forming a high-temperature superconductor thin film pattern made of a sintered body using conventional complementary methods described above has problems in terms of miniaturization of pattern dimensions and compatibility with normal semiconductor process technology. This has not been taken into consideration, and this poses a problem when applying high-temperature superconductor thin films to semiconductor integrated circuits. In other words, when forming the desired pattern after forming the high temperature superconductor thin film on the entire surface of the substrate, if ion sputter etching is used, the etching selectivity with respect to the mask material is small, so the mask is There are other problems, such as the need for thicker materials and greater damage to the surface of the underlying substrate. In addition, when using the wet method, the etching rate of the sintered body is low, so it takes a long time, and the imaginary body is a polycrystalline body with a grain size of about 1 μm, resulting in the formation of fine patterns. The problem is that it is difficult.
本発明の目的は、上記問題点を解消し、焼結体から成る
高温超電導体薄膜の微細パターンを容易に形成する方法
を提供し、半導体集積回路への高温超電導体薄膜の適用
を容易にすることにある。An object of the present invention is to solve the above-mentioned problems and provide a method for easily forming fine patterns of high-temperature superconductor thin films made of sintered bodies, thereby facilitating the application of high-temperature superconductor thin films to semiconductor integrated circuits. There is a particular thing.
［問題点を解決するための手段］
上記目的は、基板上へ金属酸化物の粉体を含有する有機
溶媒を塗布して、上記基板を乾燥させて金属酸化物粉体
膜を形成し、上記金属酸化物粉体膜を所望のパターン形
状に加工した後に焼結する工程とすることによって達成
される。[Means for Solving the Problems] The above object is to apply an organic solvent containing metal oxide powder onto a substrate, dry the substrate to form a metal oxide powder film, and This is achieved by processing the metal oxide powder film into a desired pattern shape and then sintering it.
［作用コ
すなわち、本発明の超電導体薄膜パターンの形成方法に
おいては、第１図（ａ）に示すように、基板１上の全面
に金属酸化物の粉体を含有する有機溶媒を所望の厚さに
塗布して金属酸化物粉体塗布膜２を形成後、第１図（ｂ
）に示すように、上記基板１を加熱して上記塗布膜中の
有機溶媒および水を蒸発させて緻密化し、金属酸化物粉
体膜３を形成した後、第１図（ｃ）に示したように、リ
ソグラフィ加工法によって所望のパターン形状を有する
金属酸化物粉体膜パターン４を形成し、その後、第１図
（ｄ）に示したように、上記基板１を高温に加熱して、
上記金属酸化物粉体膜パターン４を焼結させることによ
り、超電導体薄膜パターン５を形成する。[In other words, in the method for forming a superconductor thin film pattern of the present invention, as shown in FIG. After forming the metal oxide powder coating film 2 by applying the powder to the metal oxide powder, as shown in FIG.
), the substrate 1 is heated to evaporate and densify the organic solvent and water in the coating film to form a metal oxide powder film 3, and then the metal oxide powder film 3 is formed as shown in FIG. 1(c). As shown in FIG. 1(d), a metal oxide powder film pattern 4 having a desired pattern shape is formed by a lithography process, and then, as shown in FIG. 1(d), the substrate 1 is heated to a high temperature.
By sintering the metal oxide powder film pattern 4, a superconductor thin film pattern 5 is formed.
上記の工程において、金属酸化物粉体を含有する有機溶
媒を塗布する工程は、従来の半導体素子製造工程で膜の
塗布に用いられているものであり、また、上記金属酸化
物粉体塗布膜２を緻密するための加熱工程は、上記従来
のホトレジスト膜を硬化させるに用いられている加熱工
程と同様の温度範囲で十分であり、さらに、上記金属酸
化物粉体膜パターン４の形成工程は、通常の半導体素子
製造工程で用いられるホトリソグラフィ加工によれば最
小寸法０．３μｍ、電子線リソグラフィ加工法によれば
最小寸法０．１μｍ以下の微細なパターン寸法が実現で
きるものである。すなわち、上記の本発明の超電導体薄
膜パターンの形成方法においては、金属酸化物粉体膜を
高温度で焼結させる前に、パターン形成を行なうことと
することによって、基板上に所望のパターン寸法を有す
る超電導体薄膜パターンを容易に形成することが可能と
なった。In the above process, the process of applying an organic solvent containing metal oxide powder is the one used for coating a film in the conventional semiconductor device manufacturing process, The heating process for densifying the metal oxide powder film pattern 4 is sufficient in the same temperature range as the heating process used to harden the conventional photoresist film. A fine pattern with a minimum dimension of 0.3 .mu.m can be realized by photolithography used in a normal semiconductor device manufacturing process, and a minimum dimension of 0.1 .mu.m or less can be achieved by electron beam lithography. That is, in the method for forming a superconductor thin film pattern of the present invention described above, by forming the pattern before sintering the metal oxide powder film at high temperature, a desired pattern size can be formed on the substrate. It has now become possible to easily form a superconductor thin film pattern with
従って、本発明は、超電導体薄膜を半導体基板上に形成
し、半導体集積回路を構成する場合の技術的効果は非常
に大きい。Therefore, the present invention has a very large technical effect when forming a superconductor thin film on a semiconductor substrate to construct a semiconductor integrated circuit.
［実施例］
以下、本発明の一実施例を第２図により説明する。第２
図は、本発明を、および配線領域が超電導体から成る電
界効果トランジスタの製造に適用した場合の製造工程を
示しており、順を追って各工程ごとに説明する。[Example] Hereinafter, an example of the present invention will be described with reference to FIG. Second
The figure shows manufacturing steps when the present invention is applied to manufacturing a field effect transistor whose wiring region is made of a superconductor, and each step will be explained in order.
第２図（ａ）は、Ｐ型、（１００）面、抵抗率１０Ωｃ
ｍの（Ｓｉ）基板１上の、電界効果トランジスタの形成
されるべき領域に、乾燥酸素雰囲気中、１０００℃と、
２０分間の熱酸化法により、厚さ２０ｎｍのゲート酸化
膜６を形成した後、所定量のイツトリウム（Ｙ ２０３
） 、炭酸バリウム（ＢａＣＯ３）＋および酸化銅（
Ｃｕｂ）の粉体を混合したシクロヘキサノン（Ｃｓ Ｈ
１ｏ○）溶媒を回転塗布し、厚さ１μｍの金属酸化物粉
体塗布膜２を形成した状態を示している。Figure 2 (a) is P type, (100) plane, resistivity 10Ωc.
m (Si) substrate 1 in a region where a field effect transistor is to be formed at 1000° C. in a dry oxygen atmosphere,
After forming a gate oxide film 6 with a thickness of 20 nm by a thermal oxidation method for 20 minutes, a predetermined amount of yttrium (Y 203
), barium carbonate (BaCO3)+ and copper oxide (
Cyclohexanone (Cs H
1o○) Solvent is spin-coated to form a metal oxide powder coating film 2 with a thickness of 1 μm.
次に、第２図（ｂ）に示したように、上記金属酸化物粉
体塗布膜２を酸素雰囲気中で２００’ｌ：。Next, as shown in FIG. 2(b), the metal oxide powder coating film 2 was coated in an oxygen atmosphere for 200 minutes.
１０分間のベーキングを行った後、ホトリソグラフィ加
工と室温の王水による２０分間の湿式エツチングによっ
て、パターン寸法２μｍに加工し、酸素雰囲気中、９５
０℃、３時間の焼結を行って超電導ゲート７を形成し、
さらに、上記超電導ゲート７をマスクとして、加工エネ
ルギ３０ｋｅＶのヒ素（Ａ ｓ ）イオンを打込み量３
Ｘ １０１５ｃ ｍ−２打込んで高濃度不純物層８を
形成した。After baking for 10 minutes, a pattern size of 2 μm was processed by photolithography and wet etching with aqua regia at room temperature for 20 minutes, and then etched at 95°C in an oxygen atmosphere.
A superconducting gate 7 is formed by sintering at 0° C. for 3 hours,
Furthermore, using the superconducting gate 7 as a mask, arsenic (A s ) ions are implanted at a processing energy of 30 keV in an amount of 3.
A high concentration impurity layer 8 was formed by implanting X 1015 cm-2.
次に第２図（ｃ）に示したように、上記超電導ゲート７
の側壁部に気相化学成長法により堆積し、ドライエツチ
ングにより酸化膜９を形成した後、第２図（ａ）に示し
た金属酸化物粉体塗布膜２の形成と同様の手法により、
厚さ１μｍの金属酸化物粉体塗布膜２を形成した。さら
に、ホトリソグラフィ加工と王水による湿式エツチング
によって、第２図（ｄ）に示すように、金属酸化物粉体
膜パターン４を形成した。Next, as shown in FIG. 2(c), the superconducting gate 7
After forming an oxide film 9 on the side wall of the metal oxide powder by vapor phase chemical growth and dry etching, the metal oxide powder coating film 2 is formed using the same method as that of forming the metal oxide powder coating film 2 shown in FIG. 2(a).
A metal oxide powder coating film 2 having a thickness of 1 μm was formed. Furthermore, a metal oxide powder film pattern 4 was formed by photolithography and wet etching using aqua regia, as shown in FIG. 2(d).
さらに、第２図（ｅ）に示すように、上記金属酸化物粉
体パターン４を、酸素雰囲気中、８００°Ｃ９３時間の
焼結を行って超電導電極１０を形成した後、層間絶縁膜
１１を形成し、ホトリソグラフィ加工によりコンタクト
穴あけを行った。Further, as shown in FIG. 2(e), the metal oxide powder pattern 4 is sintered at 800° C. for 93 hours in an oxygen atmosphere to form a superconducting electrode 10, and then an interlayer insulating film 11 is formed. A contact hole was formed using photolithography.
最後に、第２図（ｆ）に示したように、第２図（ｂ）に
示した超電導ゲート７の形成と同様の手法、すなわち、
金属酸化物粉体塗布膜の形成とそのホトリソグラフィ加
工によるパターン形成、および、酸素雰囲気中、８００
℃、３時間の焼結によって、線幅２μｍの超電導配線１
２を形成し、電界効果トランジスタを完成した。Finally, as shown in FIG. 2(f), a method similar to that of forming the superconducting gate 7 shown in FIG. 2(b), that is,
Formation of a metal oxide powder coating film, pattern formation by photolithography processing, and 800°C in an oxygen atmosphere.
By sintering at ℃ for 3 hours, superconducting wiring 1 with a line width of 2 μm
2 was formed, and a field effect transistor was completed.
上記の製造工程で完成した電界効果トランジスタの電気
特性を測定したところ、室温（２３℃）において正常な
トランジスタ特性を示し、各超電導体パターンが断線す
ることなく形成されていることが確認できた。さらに、
上記トランジスタを液体窒素温度（７７Ｋ）に冷却した
ところ、各超電導体パターンが超電導状態にはいったた
め、室温で測定した結果に比較すると、配線抵抗は約１
／１０倍に減少し、トランジスタのスイッチング速度も
ほぼ１０倍に高速化することが分った。When the electrical characteristics of the field effect transistor completed through the above manufacturing process were measured, it was confirmed that it exhibited normal transistor characteristics at room temperature (23° C.), and that each superconductor pattern was formed without disconnection. moreover,
When the above transistor was cooled to liquid nitrogen temperature (77K), each superconductor pattern entered a superconducting state, so compared to the results measured at room temperature, the wiring resistance was approximately 1
It was found that the switching speed of the transistor was also increased by approximately 10 times.
以上の本実施例に述べたように、本発明によれば、焼結
体から成る高温超電導体薄膜の微細パターンの形成をシ
リコン基板上の電界効果トランジスタの製造工程中に容
易に導入することが可能となった。従って、本発明の超
電導体薄膜パターンの形成方法は、焼結体から成る高温
超電導体薄膜を半導体集積回路へ応用する上で、その技
術的効果が非常に高く、工業的に重要な技術となるもの
である。As described in the above embodiment, according to the present invention, it is possible to easily introduce the formation of a fine pattern of a high temperature superconductor thin film made of a sintered body into the manufacturing process of a field effect transistor on a silicon substrate. It has become possible. Therefore, the method for forming a superconductor thin film pattern of the present invention has a very high technical effect when applying a high temperature superconductor thin film made of a sintered body to a semiconductor integrated circuit, and is an industrially important technology. It is something.
尚、本実施例では、Ｓｉ基板上に電界効果トランジスタ
を製造する場合を例にとって述べたが、他の化合物半導
体基板、例えば、ガリウム・ヒ素（ＧａＡｓ）＋インジ
ウム・アンチモン（ＩｎＳｂ）。In this embodiment, a case has been described in which a field effect transistor is manufactured on a Si substrate, but other compound semiconductor substrates such as gallium arsenide (GaAs) + indium antimony (InSb) may be used.
インジウム・リン（ＩｎＰ）等へ応用する場合にも同様
の効果のあることは言うまでもない。また、本実施例で
の金属酸化物粉体塗布膜２の加工には Ｒ−
湿式エツチングを用いたが、例えば塩素あるいは弗素系
のを用いたドライエツチングも利用できる。It goes without saying that similar effects can be obtained when applied to indium phosphide (InP) and the like. Furthermore, although R-wet etching was used to process the metal oxide powder coating film 2 in this embodiment, dry etching using, for example, chlorine or fluorine may also be used.
［発明の効果］
本発明によれば、焼結体から成る高温超電導体薄膜の微
細パターンを半導体基板上に容易に形成できるため、上
記超電導体薄膜を半導体集積回路へ容易に応用すること
が可能となり、半導体集積回路の高性能化が実現できる
技術的効果がある。[Effects of the Invention] According to the present invention, a fine pattern of a high-temperature superconductor thin film made of a sintered body can be easily formed on a semiconductor substrate, so the superconductor thin film can be easily applied to a semiconductor integrated circuit. This has the technical effect of making it possible to improve the performance of semiconductor integrated circuits.
第１図（ａ）から第１図（ｄ）は、本発明の詳細な説明
するための工程を示す断面図であり、第２図（ａ）から
第２図（ｆ）は、本発明の一実施例を説明するための各
工程における素子断面図である。
１・基板、２・・金属酸化物粉体塗布膜、３・・金属酸
化物粉体膜、４・・・金属酸化物粉体膜パターン、５・
・超電導体薄膜パターン、６・・ゲート酸化膜、７・・
超電導ゲート、８ ・高濃度不純物層、９−酸化膜、１
０・・・超電導電極、１１・・・層間ＭＡＲ膜、１２・
・・超電導配線。
第 １ 図
茶 ２ ニFIG. 1(a) to FIG. 1(d) are cross-sectional views showing steps for explaining the present invention in detail, and FIG. 2(a) to FIG. FIG. 3 is a cross-sectional view of an element in each step for explaining an example. 1. Substrate, 2. Metal oxide powder coating film, 3. Metal oxide powder film, 4. Metal oxide powder film pattern, 5.
・Superconductor thin film pattern, 6... Gate oxide film, 7...
Superconducting gate, 8 ・High concentration impurity layer, 9-Oxide film, 1
0...Superconducting electrode, 11...Interlayer MAR film, 12.
...Superconducting wiring. 1st diagram 2 d
Claims (1)
塗布しする工程と、上記基板を乾燥して金属酸化物粉体
膜を形成する工程と、上記金属酸化物粉体膜を所望のパ
ターン形状に加工した後、焼損する工程とを含むことを
特徴とする超電導体薄膜パターンの形成方法。1. A step of applying an organic solvent mixed with metal oxide powder onto the substrate, a step of drying the substrate to form a metal oxide powder film, and a step of forming the metal oxide powder film on the substrate. 1. A method for forming a superconductor thin film pattern, the method comprising the step of processing into a desired pattern shape and then burning it out.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62139714A JPS63304646A (en) | 1987-06-05 | 1987-06-05 | Formation of superconductor thin film pattern |
| DE3810494A DE3810494C2 (en) | 1987-03-27 | 1988-03-28 | Integrated semiconductor circuit device with superconducting layer |
| US07/863,530 US5266815A (en) | 1987-03-27 | 1992-04-06 | Semiconductor integrated circuit device having superconductive layer and isolation member with nitride isolation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62139714A JPS63304646A (en) | 1987-06-05 | 1987-06-05 | Formation of superconductor thin film pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63304646A true JPS63304646A (en) | 1988-12-12 |
Family
ID=15251708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62139714A Pending JPS63304646A (en) | 1987-03-27 | 1987-06-05 | Formation of superconductor thin film pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63304646A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6419783A (en) * | 1987-06-26 | 1989-01-23 | Hewlett Packard Yokogawa | Manufacture of superconductor film |
| JPS6486578A (en) * | 1987-06-26 | 1989-03-31 | Nec Corp | Method for forming pattern |
| KR100878234B1 (en) * | 2002-07-08 | 2009-01-13 | 삼성전자주식회사 | A method of forming a reflection layer pattern and a method of fabricating TFT array panel by using the same |
-
1987
- 1987-06-05 JP JP62139714A patent/JPS63304646A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6419783A (en) * | 1987-06-26 | 1989-01-23 | Hewlett Packard Yokogawa | Manufacture of superconductor film |
| JPS6486578A (en) * | 1987-06-26 | 1989-03-31 | Nec Corp | Method for forming pattern |
| KR100878234B1 (en) * | 2002-07-08 | 2009-01-13 | 삼성전자주식회사 | A method of forming a reflection layer pattern and a method of fabricating TFT array panel by using the same |
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