JPS63301557A - Protective circuit of complementary mis integrated circuit - Google Patents
Protective circuit of complementary mis integrated circuitInfo
- Publication number
- JPS63301557A JPS63301557A JP62137487A JP13748787A JPS63301557A JP S63301557 A JPS63301557 A JP S63301557A JP 62137487 A JP62137487 A JP 62137487A JP 13748787 A JP13748787 A JP 13748787A JP S63301557 A JPS63301557 A JP S63301557A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- supply terminal
- gate
- mis transistor
- side power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000295 complement effect Effects 0.000 title claims description 13
- 230000001681 protective effect Effects 0.000 title abstract 7
- 239000000758 substrate Substances 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 230000001747 exhibiting effect Effects 0.000 description 2
- 230000006855 networking Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、ＣＭＯＳ回路等の相補型ＭＩＳ（ＭｅＬａｌ
Ｉｎ５ｕｌａｔｏｒ Ｓｅｍ１ｃｏｎｄｕｃｔｏｒ
）集積回路の保護回路に関し、特に、逆方向耐圧及びブ
レークダウン後の抵抗を小さくできるようにした保護回
路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to complementary MIS (MeLal) such as CMOS circuits.
In5ulator Sem1conductor
) The present invention relates to a protection circuit for integrated circuits, and particularly relates to a protection circuit that can reduce reverse breakdown voltage and resistance after breakdown.
［従来の技術］
従来、例えば静電気ストレスからの電源端子の保護及び
ネットワーク化を図るための保護回路は、第６図に示す
ように、チップ１の内部回路２の高電位側電源端子３と
低電位側電源端子４との間にＰＮ接合ダイオード５を逆
方向接続して構成するのが一般的であった。[Prior Art] Conventionally, for example, a protection circuit for protecting power supply terminals from static electricity stress and for networking has been constructed by connecting a high potential side power supply terminal 3 of an internal circuit 2 of a chip 1 to a low potential side power supply terminal 3 of an internal circuit 2 of a chip 1, as shown in FIG. Generally, a PN junction diode 5 was connected in a reverse direction between the power source terminal 4 on the potential side.
［発明が解決しようとする問題点］
しかしながら、上述した従来の保護手段では、ＰＮ接合
ダイオード５の逆方向耐圧が高いため、高電位電源端子
３を高電位とする高い電界が印加された場合には、保護
素子として十分に機能しないという欠点があった。しか
も、ＰＮ接合ダイオードは、ブレークダウン後の直列抵
抗が高いことからも保護能力が低いという欠点があった
。[Problems to be Solved by the Invention] However, in the conventional protection means described above, since the reverse breakdown voltage of the PN junction diode 5 is high, when a high electric field is applied that makes the high potential power supply terminal 3 a high potential, had the disadvantage that it did not function satisfactorily as a protection element. Furthermore, the PN junction diode has a drawback of low protection ability due to its high series resistance after breakdown.
本発明は、かかる問題点に鑑みてなされたものであって
、ＰＮ接合ダイオードに代り、逆方向耐圧が低く、ブレ
ークダウン後の直列抵抗も小さい相補型ＭＩＳ集積回路
の保護回路を提供することを目的とする。The present invention has been made in view of these problems, and it is an object of the present invention to provide a protection circuit for a complementary MIS integrated circuit that has a low reverse breakdown voltage and a low series resistance after breakdown, in place of a PN junction diode. purpose.
［問題点を解決するための手段］
本発明に係る相補型ＭＩＳ集積回路の保護回路は、保護
素子として前述のＰＮ接合ダイオードの代りに、Ｎチャ
ネルＭＩＳ）−ランジスタによるダイオードを主体とし
て構成されている。[Means for Solving the Problems] The protection circuit for a complementary MIS integrated circuit according to the present invention is mainly composed of a diode using an N-channel MIS transistor as a protection element instead of the above-mentioned PN junction diode. There is.
即ち、本発明の保護回路は、ドレインが高電位側電源端
子に接続され、ソース及びバックゲートが低電位側電源
端子に接続されたＮチャネルＭＩＳ ＋−ランジスタを
備えた第１の手段と、上記ＮチャネルＭＩＳトランジス
タのゲートを前記低電位側電源端子の電位と同電位に保
つための第２の手段とを有している。That is, the protection circuit of the present invention includes a first means including an N-channel MIS +- transistor whose drain is connected to a high potential side power supply terminal and whose source and back gate are connected to a low potential side power supply terminal; and second means for maintaining the gate of the N-channel MIS transistor at the same potential as the potential of the low potential side power supply terminal.
〔作用］
第２図は従来用いられていたＰＮ接合ダイオードと、本
発明で用いるＮチャネルＭＩＳトランジスタによるダイ
オード（以下、ＢＶＤＳＮダイオードと称す）の逆方向
電圧−電流特性である。通常、逆方向の耐圧はＰＮ接合
ダイオードのそれ（以下、Ｂ Ｖ Ｊと記す）とＢＶＤ
ＳＮダイオードのそれ（ＢＶＤＳ）とを比較すると、ド
レイン部ゲート近傍の電界集中のために、Ｂ Ｖ Ｄｓ
＜ Ｂ Ｖ Ｊなる関係が成立する。またＢＶＤＳＮダ
イオードは、逆方向ブレークダウン後、ドレインをコレ
クタ、ソースをエミッタ、バックゲートをベースとする
寄生ＮＰＮトランジスタがオンし、負性抵抗特性を示し
た後、極めて低インピーダンスの特性を示す。ダイオー
ドとしてのオン抵抗として見ると、同一面積でＢ■Ｄｓ
ＮダイオードがＰＮ接合ダイオードの１／１０〜１／２
０の抵抗値を示す。このため、ＢＶｏｓ、ダイオードは
、保護素子として要求される低インピーダンス及び低ク
ランプ電圧という点から、ＰＮ接合ダイオードに比して
はるかに優れた利点を有しており、保護能力を格段に向
上させることができる。また、保護回路のネットワーク
化という観点からいっても、電源間ダイオードの特性は
重要であり、上述の利点が集積回路の高信頼度化に大き
く帰与する。[Operation] FIG. 2 shows the reverse voltage-current characteristics of a conventionally used PN junction diode and a diode using an N-channel MIS transistor (hereinafter referred to as a BVDSN diode) used in the present invention. Normally, the reverse breakdown voltage is the same as that of a PN junction diode (hereinafter referred to as B V J) and BVD.
When compared with that of an SN diode (BVDS), due to the concentration of electric field near the gate of the drain part, the B V Ds
<B V J holds true. Further, in the BVDSN diode, after reverse breakdown, a parasitic NPN transistor having a drain as a collector, a source as an emitter, and a back gate as a base is turned on, exhibiting negative resistance characteristics, and then exhibiting extremely low impedance characteristics. In terms of on-resistance as a diode, B■Ds in the same area
N diode is 1/10 to 1/2 that of PN junction diode
It shows a resistance value of 0. For this reason, BVos and diodes have far superior advantages over PN junction diodes in terms of low impedance and low clamping voltage required as protection elements, and can significantly improve protection capabilities. Can be done. Also, from the viewpoint of networking protection circuits, the characteristics of the power supply diode are important, and the above-mentioned advantages greatly contribute to higher reliability of the integrated circuit.
［実施例］
次に本発明の実施例について、添付の図面を参照して説
明する。第１図は本発明の第１の実施例に係る保護回路
のブロック図である。保護回路１１はチップ１の内部回
路２の高電位側電源端子３と、低電位側電源端子４との
間に接続されている。この保護回路１１．は、ドレイン
が高電位側電源端子（Ｖｏｏ）３に接続され、ソース、
ゲート及びバックゲートが低電位側電源端子（Ｖｓｓ）
４に接続されたＮチャネルＭＩＳトランジスタ１２を有
する。この実施例においては、ＮチャネルＭＩＳトラン
ジスタ１２が第１の手段を構成し、同トランジスタ１２
のゲートと端子４との間の金属配線５が第２の手段を構
成している。[Example] Next, an example of the present invention will be described with reference to the attached drawings. FIG. 1 is a block diagram of a protection circuit according to a first embodiment of the present invention. The protection circuit 11 is connected between the high potential side power supply terminal 3 and the low potential side power supply terminal 4 of the internal circuit 2 of the chip 1 . This protection circuit 11. The drain is connected to the high potential side power supply terminal (Voo) 3, the source,
Gate and back gate are low potential side power supply terminals (Vss)
It has an N-channel MIS transistor 12 connected to 4. In this embodiment, an N-channel MIS transistor 12 constitutes the first means;
The metal wiring 5 between the gate and the terminal 4 constitutes the second means.
このような保護回路１１においては、第２図に示したよ
うに、逆方向電圧が低く、ブレークダウン後のインピー
ダンスが低いので、保護素子として良好に機能する。In such a protection circuit 11, as shown in FIG. 2, the reverse voltage is low and the impedance after breakdown is low, so that it functions well as a protection element.
第３図は本発明の第２の実施例を示す。第３図において
、第１図と同一物には同一符号を付して説明を省略する
。この実施例において、第２の手段としてトランジスタ
１２のゲートと低電位側電源端子４との間に接続された
抵抗体１３を用いることにより、静電気ストレス印加時
のゲート電界による破壊を防止している。抵抗体として
は、多結晶シリコン等の非接合型抵抗体、又は、ソース
・ドレイン拡散層、基板、若しくは反対導電型ウェル等
の接合型抵抗体を用いることができる。FIG. 3 shows a second embodiment of the invention. In FIG. 3, the same components as those in FIG. 1 are given the same reference numerals and their explanations will be omitted. In this embodiment, as a second means, a resistor 13 connected between the gate of the transistor 12 and the low potential side power supply terminal 4 is used to prevent breakdown due to the gate electric field when applying electrostatic stress. . As the resistor, a non-junction type resistor such as polycrystalline silicon, or a junction type resistor such as a source/drain diffusion layer, a substrate, or a well of an opposite conductivity type can be used.
第４図に第３の実施例を示す。この実施例は、Ｎチャネ
ルＭ■Ｓトランジスタ１２のゲート・を、同−電源系の
インバータ１４により、高インピーダンス化し、かつ、
インバータ１４の入力を前述の抵抗体１３により保護し
た例である。FIG. 4 shows a third embodiment. In this embodiment, the gate of the N-channel M■S transistor 12 is made high impedance by the inverter 14 of the same power supply system, and
This is an example in which the input of the inverter 14 is protected by the resistor 13 described above.
第５図は本発明の第４の実施例を示すブロック図である
。この実施例では、第４図に示す回路１１に対し、更に
ＰチャネルＭＩＳトランジスタ１５と、そのゲート保護
用インバータ１６と、抵抗体１７とを追加している。Ｐ
チャネルＭＩＳＩ〜ランジスタ１５は、ソース及びバッ
クゲーｈか高電位側電源端子３に接続され、ドレインが
低電位側電源端子４に接続されている。FIG. 5 is a block diagram showing a fourth embodiment of the present invention. In this embodiment, a P-channel MIS transistor 15, an inverter 16 for protecting its gate, and a resistor 17 are added to the circuit 11 shown in FIG. P
The source and back gate h of the channel MISI to the transistor 15 are connected to the high potential side power supply terminal 3, and the drain is connected to the low potential side power supply terminal 4.
この回路によれば、ＰチャネルＭ Ｉ Ｓ ？−ランジ
スタ１５によるダイオード（以下、ＢＶｏｓｐダイオー
ドと称す）が並列に入るため、逆方向のストレスが加わ
った場合、まず、ＢＶＤＳＮダイオード及びＢＶＤＳＰ
ダイオードのうちのいずれか逆方向耐圧が低い方でクラ
ンプが可能となる。また、Ｐ型基板の場合、Ｎ型ウェル
をベースとするＰＮＰ縦形トランジスタも保護素子とし
て動作をし、Ｎ型基板の場合、Ｐ型ウェルをベースとす
るＮＰＮ縦形トランジスタも保護素子として動作しうる
ため、保護能力が更に一層向上するという利点がある。According to this circuit, P channel M I S ? - Since the diode by the transistor 15 (hereinafter referred to as BVosp diode) is connected in parallel, when reverse stress is applied, the BVDSN diode and BVDSP
Clamping is possible with whichever of the diodes has a lower reverse breakdown voltage. In addition, in the case of a P-type substrate, a PNP vertical transistor based on an N-type well also operates as a protection element, and in the case of an N-type substrate, an NPN vertical transistor based on a P-type well can also operate as a protection element. This has the advantage that the protection ability is further improved.
［発明の効果］
以上説明したように、本発明によれば、電源間の保護素
子として、ＮチャネルＭＩＳトランジスタをダイオード
として使用することにより、低クランプ電圧及び低オン
抵抗の保護能力を有し、従来に比して信頼度が著しく向
上した相補型ＭＩＳ集積回路を得ることができる。[Effects of the Invention] As explained above, according to the present invention, by using an N-channel MIS transistor as a diode as a protection element between power supplies, it has a protection ability of low clamp voltage and low on-resistance. A complementary MIS integrated circuit with significantly improved reliability compared to the conventional one can be obtained.
第１図は本発明の第１の実施例を示すブロック図、第２
図は従来のＰＮ接合ダイオードと本発明で用いるＮチャ
ネルＭＩ Ｓトランジスタを用いたダイオードの逆方向
電圧−電流特性図、第３図乃至第５図は本発明の第２乃
至第４の実施例を夫々示すブロック図、第６図は従来の
保護手段を示すブロック図である。
１；チップ、２；内部回路、３；高電位側電源端子、４
；低電位側電源端子、５．ＰＮ接合ダイオード、１１．
保護回路、１２；ＮチャネルＭＩＳトランジスタ（ＢＶ
ＤＳＮダイオ−トン、１３゜１７、抵抗体、１４，１６
；インバータ、１５：ＰチャネルＭＩＳトランジスタ（
ＢＶＤＳＰダイオード）FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure shows reverse voltage-current characteristics of a conventional PN junction diode and a diode using an N-channel MIS transistor used in the present invention. FIG. 6 is a block diagram showing conventional protection means. 1; Chip, 2; Internal circuit, 3; High potential side power supply terminal, 4
;Low potential side power supply terminal, 5. PN junction diode, 11.
Protection circuit, 12; N-channel MIS transistor (BV
DSN dioton, 13゜17, resistor, 14, 16
; Inverter, 15: P-channel MIS transistor (
BVDSP diode)
Claims (8)
びバックゲートが低電位側電源端子に接続されたＮチャ
ネルＭＩＳトランジスタを備えた第１の手段と、前記Ｎ
チャネルＭＩＳトランジスタのゲートを前記低電位側電
源端子と同電位に保つ第２の手段とを具備したことを特
徴とする相補型ＭＩＳ集積回路の保護回路。(1) A first means comprising an N-channel MIS transistor whose drain is connected to a high-potential side power supply terminal and whose source and backgate are connected to a low-potential side power supply terminal;
A protection circuit for a complementary MIS integrated circuit, comprising: second means for keeping the gate of the channel MIS transistor at the same potential as the low potential side power supply terminal.
ジスタのゲートと前記低電位側電源端子とを接続する金
属配線であることを特徴とする特許請求の範囲第１項に
記載の相補型ＭＩＳ集積回路の保護回路。(2) The complementary MIS according to claim 1, wherein the second means is a metal wiring connecting the gate of the N-channel MIS transistor and the low potential side power supply terminal. Integrated circuit protection circuit.
ジスタのゲートと前記低電位側電源端子とを接続する抵
抗体であることを特徴とする特許請求の範囲第１項に記
載の相補型ＭＩＳ集積回路の保護回路。(3) The complementary MIS according to claim 1, wherein the second means is a resistor that connects the gate of the N-channel MIS transistor and the low potential side power supply terminal. Integrated circuit protection circuit.
体であることを特徴とする特許請求の範囲第３項に記載
の相補型ＭＩＳ集積回路の保護回路。(4) The protection circuit for a complementary MIS integrated circuit according to claim 3, wherein the resistor is a non-junction resistor made of polycrystalline silicon or the like.
び反対導電型ウェルのいずれかによる接合型抵抗体であ
ることを特徴とする特許請求の範囲第３項に記載の相補
型ＭＩＳ集積回路の保護回路。(5) The complementary MIS integrated circuit according to claim 3, wherein the resistor is a junction type resistor formed by any one of a source/drain diffusion layer, a substrate, and a well of an opposite conductivity type. protection circuit.
を反転させて、前記ＮチャネルＭＩＳトランジスタのゲ
ートに与えるインバータを有することを特徴とする特許
請求の範囲第１項に記載の相補型ＭＩＳ集積回路の保護
回路。(6) The second means includes an inverter that inverts the potential of the high potential side power supply terminal and applies it to the gate of the N-channel MIS transistor. Protection circuit for complementary MIS integrated circuit.
電位側電源端子に接続されドレインが低電位側電源端子
に接続されたＰチャネルＭＩＳトランジスタを備え、か
つ前記第２の手段は、前記ＰチャネルＭＩＳトランジス
タのゲートを前記高電位側電源端子と同電位に保つ手段
を備えたことを特徴とする特許請求の範囲第１項に記載
の相補型ＭＩＳ集積回路の保護回路。(7) The first means includes a P-channel MIS transistor whose source and backgate are connected to a high-potential power supply terminal and whose drain is connected to a low-potential power supply terminal, and the second means comprises a 2. The complementary MIS integrated circuit protection circuit according to claim 1, further comprising means for keeping the gate of the P-channel MIS transistor at the same potential as the high potential side power supply terminal.
を反転させて前記ＮチャネルＭＩＳトランジスタのゲー
トに与える第１のインバータと、前記低電位側電源端子
の電位を反転させて前記ＰチャネルＭＩＳトランジスタ
のゲートに与える第２のインバータとを備えたことを特
徴とする特許請求の範囲第７項に記載の相補型ＭＩＳ集
積回路の保護回路。(8) The second means includes a first inverter that inverts the potential of the high-potential side power supply terminal and applies it to the gate of the N-channel MIS transistor; 8. The protection circuit for a complementary MIS integrated circuit according to claim 7, further comprising a second inverter that applies the power to the gate of the P-channel MIS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62137487A JPH0770609B2 (en) | 1987-05-31 | 1987-05-31 | Protection circuit for complementary MIS integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62137487A JPH0770609B2 (en) | 1987-05-31 | 1987-05-31 | Protection circuit for complementary MIS integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63301557A true JPS63301557A (en) | 1988-12-08 |
| JPH0770609B2 JPH0770609B2 (en) | 1995-07-31 |
Family
ID=15199791
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62137487A Expired - Lifetime JPH0770609B2 (en) | 1987-05-31 | 1987-05-31 | Protection circuit for complementary MIS integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0770609B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0653419A (en) * | 1992-07-31 | 1994-02-25 | Kawasaki Steel Corp | Power supply protective circuit for semiconductor device |
-
1987
- 1987-05-31 JP JP62137487A patent/JPH0770609B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0653419A (en) * | 1992-07-31 | 1994-02-25 | Kawasaki Steel Corp | Power supply protective circuit for semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0770609B2 (en) | 1995-07-31 |
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Legal Events
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