JPS63301555A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63301555A JPS63301555A JP13850287A JP13850287A JPS63301555A JP S63301555 A JPS63301555 A JP S63301555A JP 13850287 A JP13850287 A JP 13850287A JP 13850287 A JP13850287 A JP 13850287A JP S63301555 A JPS63301555 A JP S63301555A
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- buried layer
- layer
- diode
- epitaxial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 230000015556 catabolic process Effects 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000002955 isolation Methods 0.000 claims abstract description 8
- 238000009792 diffusion process Methods 0.000 claims abstract description 4
- 230000005611 electricity Effects 0.000 abstract description 2
- 230000003068 static effect Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 2
- 230000001681 protective effect Effects 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 4
- 230000006378 damage Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、高耐圧素子と、低耐圧素子の混在する半導体
装置の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to the structure of a semiconductor device in which high-voltage elements and low-voltage elements coexist.
従来、この種の高耐圧素子部を含む半導体集積回路では
、低耐圧素子部にのみ保護回路を有し、高耐圧素子部に
は特に保護回路を使用ｌ−ていなかった。Conventionally, in a semiconductor integrated circuit including this type of high voltage element section, a protection circuit has been provided only in the low voltage element section, and no protection circuit has been particularly used in the high voltage element section.
上述した従来の高耐圧素子部では、特に保護回路を使用
していなかったので、静電破壊に弱いという欠点があっ
た。The above-described conventional high-voltage element section did not particularly use a protection circuit, so it had the disadvantage of being susceptible to electrostatic damage.
また、従来の保護回路は被保護素子の外に形成していた
ので、大きな耐圧をもつ保護回路では大きな占有面積を
必要とし、集積回路の集積密度低下の原因となっていた
。Furthermore, since conventional protection circuits are formed outside the protected elements, protection circuits with high breakdown voltages require a large area, which causes a reduction in the integration density of integrated circuits.
本発明によれば、特に高耐圧素子に適した保護回路を備
えており、一導電型の半導体基板に一導電型の分離用埋
込層と他の導電型の素子用埋込層を有し、その上に形成
される他の導電型の半導体層に半導体素子を形成してな
る半導体装置において、分離用埋込層と素子用埋込層と
の相対的位置関係により定まる降伏電圧をもつダイオー
ドを保護素子として有している。According to the present invention, a protection circuit particularly suitable for high voltage elements is provided, and a semiconductor substrate of one conductivity type has an isolation buried layer of one conductivity type and a buried layer for elements of another conductivity type. , a diode having a breakdown voltage determined by the relative positional relationship between the isolation buried layer and the element buried layer in a semiconductor device in which a semiconductor element is formed on a semiconductor layer of another conductivity type formed thereon. It has as a protection element.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は、本発明の一実施例の回路図であり、第２図は
その一具体例の縦断面図である。Ｐ型シリコン基板１に
Ｎ型の埋込層３とＰ型埋込層４を形成後Ｎ−型のエピタ
キシャル層２を成長し、表面から絶縁Ｐ＋！５をＰ＋型
埋込層４に達するように拡散してエピタキシャル層２に
複数の島領域を互いに分離して形成する。Ｎ型埋込層３
を有する島領域の１つに、コレクタコンタクト用Ｎ領域
、ペース用Ｐ領域およびその内部にエミッタ用Ｎ領域を
形成してＮＰＮ）ランジスタロを作る。FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a vertical cross-sectional view of one specific example. After forming an N-type buried layer 3 and a P-type buried layer 4 on a P-type silicon substrate 1, an N- type epitaxial layer 2 is grown, and an insulating P+! 5 is diffused to reach the P+ type buried layer 4 to form a plurality of isolated island regions in the epitaxial layer 2. N-type buried layer 3
An NPN (NPN) transistor is formed by forming an N region for a collector contact, a P region for a space, and an N region for an emitter inside the island region.
この時、Ｐ型基板１とＮ−型エピタキシャル層２との界
面付近では、素子分離用の埋込み１層４と埋込みＮ Ｒ
３の相対位置７によって耐圧ＶＢが定まる。この相対位
置７の距離を変えることで、この耐圧ＶＢをエピタキシ
ャルＮ層２に形成され九ＮＰＮトランジスタ６のコレク
タ耐圧よシ少し小さい値に設定すれば、トランジスタの
コレクタ耐圧より大きな電圧がコレクタにかかった時点
で埋込み２層４と埋込み８層３からなるダイオードが降
伏して、ＮＰＮ）ランジスタロの極部的な熱破壊を防ぎ
ＮＰＮ）ランジスタロを保護する。At this time, near the interface between the P-type substrate 1 and the N-type epitaxial layer 2, there is a buried layer 4 for element isolation and a buried N R
The withstand voltage VB is determined by the relative position 7 of 3. By changing the distance of this relative position 7, if this breakdown voltage VB is set to a value slightly smaller than the collector breakdown voltage of the nine NPN transistor 6 formed in the epitaxial N layer 2, a voltage larger than the collector breakdown voltage of the transistor will be applied to the collector. At this point, the diode composed of the buried 2-layer 4 and the buried 8-layer 3 breaks down to prevent local thermal damage of the NPN) transistor and protect the NPN) transistor.
この種ダイオードは降伏電圧が比較的大きいので、ＮＰ
Ｎ）ランジスタロとしては比較的高耐圧のものが有効に
保ａ可能となる。This type of diode has a relatively large breakdown voltage, so the NP
N) A relatively high breakdown voltage can be effectively maintained as a transistor.
第３図は、本発明の他の実施例の回路図であり、第４図
はその具体例の縦断面図である。第２図の具体例同様に
Ｐ型基板１上のＮ−型エピタキシャル層２はＰ埋込層４
とＰ絶縁分離層５とで複数の島領域に分けられており、
その１つのＰ型基板１との界面にＮ埋込層３を有してい
る。Ｎ埋込層３上のエピタキシャル層２には素子は形成
されておらず、単にＮ拡散層８が形成されている。Ｎ拡
散層８は次に説明するＮ埋込ｒｆ１．３とＰ埋込層４と
のなすダイオードの電極であシ、例えば電源Ｖｃｃの電
位をとるように電源端子に配線される。この時、Ｐ埋込
層４はＰ型基板１を介して最低電位ＶＣＣとなっている
ため、Ｐ＋埋込層４とＮ−埋込層３の相対位置７で決ま
るダイオードの耐圧で電源ＶｃｃとＶｓｓ間の電Ｍは制
限される。すなわち、相対位置７の距離を適切にさだめ
る事により、電源ＶｃｃとＶｓｓ間にＰ埋込／Ｊ４とＮ
埋込層３から成るダイオードの降伏電圧以上の電圧がか
かることはなく、同じ基板】上に形成した他の素子に異
常に高い電圧がかかるのを防ぎ、係争を保護する。FIG. 3 is a circuit diagram of another embodiment of the present invention, and FIG. 4 is a longitudinal sectional view of the specific example. Similar to the specific example shown in FIG.
It is divided into a plurality of island regions by a P insulating isolation layer 5,
An N buried layer 3 is provided at the interface with one of the P type substrates 1. No element is formed in the epitaxial layer 2 on the N buried layer 3, but only an N diffusion layer 8 is formed. The N diffusion layer 8 is an electrode of a diode formed by the N buried rf1.3 and the P buried layer 4, which will be described next, and is wired to a power supply terminal so as to take the potential of the power supply Vcc, for example. At this time, since the P buried layer 4 is at the lowest potential VCC via the P type substrate 1, the diode breakdown voltage determined by the relative position 7 of the P+ buried layer 4 and the N− buried layer 3 is the power supply Vcc. The voltage M between Vss is limited. In other words, by adjusting the distance of the relative position 7 appropriately, it is possible to embed P/J4 and N between the power supplies Vcc and Vss.
A voltage higher than the breakdown voltage of the diode made of the buried layer 3 is not applied, which prevents an abnormally high voltage from being applied to other elements formed on the same substrate, thereby protecting against disputes.
〔発明の効果ｊ
以上に説明したように、本発明は、素子分離用の埋込層
層と埋込Ｎ層の耐圧を、その相対位置によって制御する
ごとにより、素子を静電気等にもとづく高電圧による破
壊から防ぎ、又、高耐圧電源間の過電圧印加による内部
素子の破壊を防ぐことができる。さらにこの耐圧がＮ
とＰの埋込層の相対位置のみに関与するため、素子表面
の面積には影響しないので、集積回路の集積密度を保護
回路のために損うことはない。[Effects of the Invention j As explained above, the present invention has the advantage of controlling the withstand voltage of the buried layer for element isolation and the buried N layer by controlling their relative positions, thereby preventing the element from being exposed to high voltages caused by static electricity, etc. It is also possible to prevent damage to internal elements due to overvoltage application between high-voltage power supplies. Furthermore, this withstand pressure is N
Since it is concerned only with the relative positions of the buried layers of P and P, it does not affect the area of the element surface, so the integration density of the integrated circuit is not impaired due to the protection circuit.
第１図は、本発明の一実施例の回路図であシ、第２図は
その回路を実現した半導体装置の縦断面図である。
第３図は、本発明の他の実施例の回路図であり、第４図
はその回路を実現した半導体装置の縦断面図である。
１・・・・・・ＰＷ基板、２・・・・・・Ｎ−エピタキ
シャルＮ層、３・・・・・・Ｎ埋込層、４・・・・・・
Ｐ埋込層、５・・・・・・Ｐ絶縁分離層、６・・・・・
・ＮＰＮトランジスタ、７・・・・・・相対位置、８・
・・・・・へ拡散ｊ−０
代理人 弁理士 内 原 晋
、ｇＮＰＩＶＴｉ
だ
ＶＳ５ ＶにFIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a vertical cross-sectional view of a semiconductor device implementing the circuit. FIG. 3 is a circuit diagram of another embodiment of the present invention, and FIG. 4 is a vertical cross-sectional view of a semiconductor device implementing the circuit. 1...PW substrate, 2...N-epitaxial N layer, 3...N buried layer, 4...
P buried layer, 5...P insulating separation layer, 6...
・NPN transistor, 7... Relative position, 8.
Spread to...j-0 Agent Patent Attorney Susumu Uchihara, gNPIVTi VS5 V
Claims (1)
一導電型の埋込み層とを有し、その上に前記他の導電型
のエピタキャル層を有し、該エピタキシャル層表面から
前記一導電型の埋込み層に達するように形成されて該エ
ピタキシャル層の一部を他から分離する前記一導電型の
分離拡散領域とを有し、前記他の導電型および前記一導
電型の埋込み層の相対的位置関係により定まる降伏電圧
をもつダイオードを保護回路として有することを特徴と
する半導体装置。A buried layer of another conductivity type and the buried layer of the one conductivity type are provided on a semiconductor substrate of one conductivity type, and an epitaxial layer of the other conductivity type is provided thereon, and the epitaxial layer is formed from the surface of the epitaxial layer to the buried layer of the one conductivity type. the one conductivity type isolation diffusion region that is formed to reach the conductivity type buried layer and isolate a part of the epitaxial layer from the other conductivity type and the one conductivity type buried layer; A semiconductor device comprising a diode having a breakdown voltage determined by relative positional relationship as a protection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13850287A JPS63301555A (en) | 1987-06-01 | 1987-06-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13850287A JPS63301555A (en) | 1987-06-01 | 1987-06-01 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63301555A true JPS63301555A (en) | 1988-12-08 |
Family
ID=15223623
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13850287A Pending JPS63301555A (en) | 1987-06-01 | 1987-06-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63301555A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5521414A (en) * | 1993-04-28 | 1996-05-28 | Sgs-Thomson Microelectronics S.R.L. | Monolithic integrated structure to protect a power transistor against overvoltage |
| JP2006216802A (en) * | 2005-02-04 | 2006-08-17 | Hitachi Ulsi Systems Co Ltd | Semiconductor device |
| US8018006B2 (en) | 2005-02-04 | 2011-09-13 | Hitachi Ulsi Systems Co., Ltd. | Semiconductor device having an enlarged space area surrounding an isolation trench for reducing thermal resistance and improving heat dissipation |
| JP2013073993A (en) * | 2011-09-27 | 2013-04-22 | Semiconductor Components Industries Llc | Semiconductor device |
-
1987
- 1987-06-01 JP JP13850287A patent/JPS63301555A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5521414A (en) * | 1993-04-28 | 1996-05-28 | Sgs-Thomson Microelectronics S.R.L. | Monolithic integrated structure to protect a power transistor against overvoltage |
| JP2006216802A (en) * | 2005-02-04 | 2006-08-17 | Hitachi Ulsi Systems Co Ltd | Semiconductor device |
| US8018006B2 (en) | 2005-02-04 | 2011-09-13 | Hitachi Ulsi Systems Co., Ltd. | Semiconductor device having an enlarged space area surrounding an isolation trench for reducing thermal resistance and improving heat dissipation |
| JP2013073993A (en) * | 2011-09-27 | 2013-04-22 | Semiconductor Components Industries Llc | Semiconductor device |
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