JPS6329872B2 - - Google Patents
Info
- Publication number
- JPS6329872B2 JPS6329872B2 JP56022739A JP2273981A JPS6329872B2 JP S6329872 B2 JPS6329872 B2 JP S6329872B2 JP 56022739 A JP56022739 A JP 56022739A JP 2273981 A JP2273981 A JP 2273981A JP S6329872 B2 JPS6329872 B2 JP S6329872B2
- Authority
- JP
- Japan
- Prior art keywords
- charge transfer
- region
- transfer
- readout
- column
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000003384 imaging method Methods 0.000 claims description 47
- 238000003491 array Methods 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 239000011159 matrix material Substances 0.000 claims 1
- 239000000470 constituent Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 238000009825 accumulation Methods 0.000 description 9
- 230000006866 deterioration Effects 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011017 operating method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/715—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors using frame interline transfer [FIT]
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Solid State Image Pick-Up Elements (AREA)
Description
【発明の詳細な説明】
本発明はCCD（電荷結合素子）を用いた固体撮
像装置、特に撮像領域、蓄積領域、読み出し領域
の３領域を有する固体撮像装置に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state imaging device using a CCD (charge-coupled device), and particularly to a solid-state imaging device having three regions: an imaging region, a storage region, and a readout region.
本発明の目的は蓄積領域の占める面積を小さく
し、撮像素子の小型化を計り、歩留りの向上を計
ることにある。 An object of the present invention is to reduce the area occupied by the storage region, downsize the image sensor, and improve the yield.
第１図はフレームトランスフアー構成の電荷転
送型固体撮像装置の構成図である。この撮像装置
は受光量に応じた光入力情報を得る撮像領域１
と、この撮像領域１からの情報を一時蓄積する蓄
積領域２と、この蓄積領域２からの信号電荷を順
次読み出す、出力回路３を含む読み出し領域４と
からなつている。 FIG. 1 is a block diagram of a charge transfer type solid-state imaging device having a frame transfer configuration. This imaging device has an imaging area 1 that obtains optical input information according to the amount of received light.
, an accumulation area 2 for temporarily accumulating information from the imaging area 1, and a readout area 4 including an output circuit 3 for sequentially reading signal charges from the accumulation area 2.
いま撮像領域１に入射した光によつて生じた電
荷は一定期間集積され、光遮蔽された蓄積領域２
へ短い期間でフレーム転送され、順次光遮蔽され
た読み出し領域４から読み出される。蓄積領域２
に移された電荷が読み出されている間、撮像領域
１では入射光に応じた電荷の集積がおこなわれ
る。蓄積領域２の信号が全部読み出された後、前
記動作と同じ動作で撮像領域１の電荷が蓄積領域
２へ移される。 The charges generated by the light that has just entered the imaging area 1 are accumulated for a certain period of time, and then transferred to the light-shielded accumulation area 2.
The frames are transferred in a short period of time and read out sequentially from the light-shielded readout area 4. Accumulation area 2
While the transferred charges are being read out, charges are accumulated in the imaging region 1 according to the incident light. After all the signals in the storage area 2 are read out, the charges in the imaging area 1 are transferred to the storage area 2 in the same operation as described above.
ここで蓄積領域２は転送電極の繰り返し構造で
形成されている。構成単位数は、撮像領域１の信
号電荷をフレーム転送して蓄積する必要があるた
め、撮像領域１の構成単位数と等しくとられるの
が普通である。また蓄積領域２の構成単位の寸法
は通常、撮像領域１の構成単位と殆んど同じ寸法
にとられるため蓄積領域２全体としては撮像領域
１とほぼ同じような面積を必要とし、撮像素子全
体では撮像領域１の２倍以上の面積となり素子歩
留り上からも大きな問題となつている。撮像領域
１の寸法は、使用する光学系により決まつてしま
うため、撮像素子の面積を小さくするためには蓄
積領域２の面積を小さくすればよい。蓄積領域２
の面積を小さくするには、構成単位の転送電極寸
法を小さくしてやればよい。一方、撮像領域１の
信号電荷を蓄積領域２で蓄積するためには撮像領
域１の電荷蓄積容量を蓄積領域２の電荷蓄積容量
は同じにしておく必要がある。 Here, the storage region 2 is formed of a repeating structure of transfer electrodes. The number of constituent units is usually set equal to the number of constituent units of the imaging area 1, since it is necessary to transfer and accumulate signal charges in the imaging area 1 in frames. Furthermore, since the dimensions of the constituent units of the storage region 2 are usually almost the same as those of the constituent units of the imaging region 1, the storage region 2 as a whole requires approximately the same area as the imaging region 1, and the entire image sensor In this case, the area is more than twice that of the imaging area 1, which poses a big problem from the viewpoint of device yield. Since the dimensions of the imaging region 1 are determined by the optical system used, in order to reduce the area of the image sensor, the area of the storage region 2 may be reduced. Accumulation area 2
In order to reduce the area of the transfer electrode, the size of the transfer electrode as a structural unit may be reduced. On the other hand, in order to accumulate the signal charges in the imaging area 1 in the storage area 2, it is necessary to make the charge storage capacity of the imaging area 1 and the charge storage capacity of the storage area 2 the same.
蓄積領域２の構成単位の転送電極寸法を小さく
することは、蓄積領域２の電荷蓄積容量が減少す
ることにつながるが、この減少を補うため撮像領
域１の駆動電圧より蓄積領域２の駆動電圧を大き
くするような動作方法がとられる。しかし動作方
法の工夫のみではおのずと限界があり、また蓄積
領域２の構成単位の転送電極寸法を小さくするこ
とはプロセス上の困難が増し、歩留りも減少す
る。 Reducing the size of the transfer electrode as a constituent unit of the storage region 2 leads to a decrease in the charge storage capacity of the storage region 2, but in order to compensate for this decrease, the drive voltage of the storage region 2 is set lower than the drive voltage of the imaging region 1. An operating method is used to increase the size. However, there is a limit to the improvement of the operation method alone, and reducing the size of the transfer electrode, which is a constituent unit of the storage region 2, increases the difficulty in the process and reduces the yield.
第２図は蓄積領域２の転送電極部の断面構造を
示したものである。同図において５，６は転送電
極、７は絶縁酸化膜、８は半導体基板である。 FIG. 2 shows the cross-sectional structure of the transfer electrode portion of the storage region 2. As shown in FIG. In the figure, 5 and 6 are transfer electrodes, 7 is an insulating oxide film, and 8 is a semiconductor substrate.
転送電極寸法を小さくするためには電極長L1
を小さくしその間隔L2も小さくする必要がある。
現状で安定した歩留りの得られる最小電極長、間
隔は3μｍ程度であり、電極間の重なり精度が1μ
ｍとすると第２図でL1＝5μｍ、L2＝3μｍ、L3＝
3μｍとなり、蓄積領域２の構成単位は16μｍとな
る。これで250個の構成単位を形成したとしても、
蓄積領域２は最低４mm程度は必要となる。 To reduce the transfer electrode size, the electrode length L 1
It is necessary to make the distance L2 small.
Currently, the minimum electrode length and spacing to obtain a stable yield is approximately 3μm, and the overlap accuracy between electrodes is 1μm.
m, then in Figure 2, L 1 = 5 μm, L 2 = 3 μm, L 3 =
3 μm, and the constituent unit of the storage region 2 is 16 μm. Even if this forms 250 constituent units,
The storage area 2 needs to be at least about 4 mm.
本発明の電荷転送型固体撮像装置はかかる従来
の欠点を改善するため開発されたもので、従来の
固体撮像装置の蓄積領域の面積を飛躍的に少なく
できる利点がある。以下に本発明の実施例を用い
て説明する。 The charge transfer type solid-state imaging device of the present invention has been developed to overcome these conventional drawbacks, and has the advantage that the area of the storage region of the conventional solid-state imaging device can be dramatically reduced. The present invention will be explained below using examples.
第３図は本発明の電荷転送型固体撮像装置の構
成図であり、撮像領域の電荷転送素子列９の１列
に対して、蓄積領域の電荷転送素子１１が２列設
けられている。撮像領域と蓄積領域間には撮像領
域の電極転送素子列１列に対して蓄積領域の電荷
転送素子列２列に選択的に転送する選択転送ゲー
ト領域１０が設けられている。蓄積領域と読み出
しレジスター領域４間には蓄積領域で２列に分け
られた信号電荷を、順番に読み出し領域へ送る選
択読み出し転送ゲート領域１２が設けられてい
る。 FIG. 3 is a block diagram of the charge transfer type solid-state imaging device of the present invention, in which two rows of charge transfer devices 11 are provided in the storage region for one row of charge transfer device rows 9 in the imaging region. A selective transfer gate region 10 is provided between the imaging region and the storage region, which selectively transfers charge to two rows of charge transfer elements in the storage region with respect to one row of electrode transfer elements in the imaging region. A selective readout transfer gate region 12 is provided between the storage region and the readout register region 4 to sequentially send signal charges divided into two columns in the storage region to the readout region.
撮像領域で光により生じた信号電荷は短い時間
で蓄積領域へ転送される。この時、撮像領域の電
荷転送素子列９の信号電荷はそれぞれ各列に対し
て蓄積領域の２つの電荷転送素子列１１へ交互に
送られる。１列の電荷転送素子列内の信号電荷を
２列の電荷転送素子列へ交互に転送するため撮像
領域の電荷転送素子列９と蓄積領域の電荷転送素
子列１１間に選択転送ゲート領域１０が設けられ
ている。蓄積領域で２列の電荷転送素子列１１に
分けられた信号電荷は、撮像領域から蓄積領域の
２列の電荷転送素子列へ送られた順序で読み出し
領域４へ送られ読み出される必要がある。蓄積領
域の２列の電荷転送素子列１１中の信号電荷を決
つた順序で読み出し領域４へ送るため、蓄積領域
と読み出し領域４間には選択読み出し転送ゲート
領域１２が設けられている。蓄積領域の信号電荷
が決つた順序で順次、読み出し領域４から読み出
されている間、撮像領域では光信号電荷の発生と
蓄積がおこなわれている。 Signal charges generated by light in the imaging region are transferred to the storage region in a short time. At this time, the signal charges in the charge transfer element array 9 in the imaging region are alternately sent to the two charge transfer element arrays 11 in the storage region for each column. In order to alternately transfer signal charges in one charge transfer element column to two charge transfer element columns, a selective transfer gate region 10 is provided between the charge transfer element column 9 in the imaging area and the charge transfer element column 11 in the storage area. It is provided. The signal charges divided into the two charge transfer element columns 11 in the accumulation region need to be sent to the readout region 4 and read out in the order in which they were sent from the imaging region to the two charge transfer element columns in the accumulation region. A selective readout transfer gate region 12 is provided between the storage region and the readout region 4 in order to send the signal charges in the two rows of charge transfer element arrays 11 in the storage region to the readout region 4 in a determined order. While the signal charges in the accumulation region are sequentially read out from the readout region 4 in a predetermined order, optical signal charges are generated and accumulated in the imaging region.
このような構成をとることにより、蓄積領域の
垂直方向の構成単位数は従来の電荷転送型固体撮
像装置に必要な構成単位数の半分ですむことにな
り、蓄積領域の面積は飛躍的に減少させることが
できる。また蓄積領域の電荷転送素子列１１の構
成単位が半分になることは、電荷転送素子の段数
も半分ですむため、蓄積領域での信号電荷の転送
効率の劣化を押えることができるという大きな利
点もある。 By adopting this configuration, the number of vertical structural units of the storage region is half of the number of structural units required for conventional charge transfer solid-state imaging devices, and the area of the storage region is dramatically reduced. can be done. Furthermore, since the number of constituent units of the charge transfer element row 11 in the storage region is halved, the number of stages of charge transfer elements is also halved, which has the great advantage of suppressing deterioration in signal charge transfer efficiency in the storage region. be.
第４図は本発明の１実施例における電荷転送型
固体撮像装置の構成模式図である。撮像領域は光
電変換部としての光電変換素子列１３と電荷転送
部としての電荷転送素子列１４を分離して設けた
構成になつている。これは撮像領域から蓄積領域
へ信号電荷を転送する時にも光が入射しているた
めに生じる擬似信号を押えるためで、光電変換素
子列１３の信号電荷を光遮蔽された電荷転送素子
列１４中を転送して、同じように光遮蔽された蓄
積領域へ移すようになつている。撮像領域の電荷
転送素子列１４の信号電荷は選択転送ゲート領域
１０を通つて２列の電荷転送素子列１１に転送さ
れ、選択読み出し転送ゲート領域１２を通つて決
められた順序で読み出し領域４へ送られ読み出さ
れる。 FIG. 4 is a schematic diagram of the configuration of a charge transfer type solid-state imaging device in one embodiment of the present invention. The imaging area has a configuration in which a photoelectric conversion element array 13 as a photoelectric conversion section and a charge transfer element array 14 as a charge transfer section are provided separately. This is to suppress false signals that occur due to incident light when signal charges are transferred from the imaging area to the storage area, and the signal charges in the photoelectric conversion element array 13 are transferred to the light-shielded charge transfer element array 14. is transferred to a storage area that is also shielded from light. The signal charges in the charge transfer element array 14 in the imaging region are transferred to the two charge transfer element arrays 11 through the selective transfer gate region 10, and then to the readout region 4 through the selective readout transfer gate region 12 in a predetermined order. sent and read.
第５図ａは選択転送ゲート領域１０近辺の１列
の拡大図で、第５図ｂは選択読み出し転送ゲート
領域１２近辺の１列の拡大図である。撮像領域の
電荷転送素子列１４、蓄積領域の電荷転送素子列
１１、読み出し領域４は４相駆動構造となつてい
る。第５図ａにおいて１６，１７，１８，１９，
２０は撮像領域の電荷転送素子列１４の転送電極
でA1，A2，A3，A4の繰り返し構造となつてい
る。S1，S2は選択転送ゲート領域１０の転送電
極、２１，２２，……２９，３０は蓄積領域の電
荷転送素子列１１の転送電極でB1，B2，B3，B4
の繰り返し構造となつている。第５図ｂにおいて
BC1，BC2，VTは選択読み出し転送ゲート領域
１２の転送電極、３１，３２，３３，３４，３５
は読み出し領域４の転送電極でC1，C2，C3，C4
の繰り返し構造となつている。 FIG. 5a is an enlarged view of one row near the selective transfer gate region 10, and FIG. 5b is an enlarged view of one row near the selective readout transfer gate region 12. The charge transfer element array 14 in the imaging region, the charge transfer element array 11 in the storage region, and the readout region 4 have a four-phase drive structure. In Figure 5a, 16, 17, 18, 19,
Reference numeral 20 denotes a transfer electrode of the charge transfer element array 14 in the imaging area, which has a repeating structure of A 1 , A 2 , A 3 , and A 4 . S 1 and S 2 are transfer electrodes of the selective transfer gate region 10 , and 21 , 22 , .
It has a repeating structure. In Figure 5b
BC 1 , BC 2 , VT are transfer electrodes of the selected read transfer gate region 12, 31, 32, 33, 34, 35
are the transfer electrodes of the readout area 4, C 1 , C 2 , C 3 , C 4
It has a repeating structure.
第６図ａは撮像領域の転送電極A1，A2，A3，
A4に加えられるクロツクパルスφA1，φA2，φA3，
φA4、選択転送ゲート領域の転送電極S1，S2に加
えられるクロツクパルスφS1，φS2、蓄積領域の転
送電極B1，B2，B3，B4に加えられるクロツクパ
ルスφB1，φB2，φB3，φB4で垂直ブランキング内で
の撮像領域から蓄積領域へ転送するときのクロツ
クパルスの一部を表わしている。撮像領域の１列
の電荷転送素子列１４中の電荷は選択転送ゲート
領域１０の転送電極に加えられるクロツクパルス
φS1，φS2により、蓄積領域の２つの電荷転送素子
列のいづれかに送られる。蓄積領域の電荷転送素
子列１１の２列の１構成単位に信号電荷が送られ
て後、１構成単位分、読み出し領域４の方向へ転
送される。従つて蓄積領域の電荷転送素子列１１
へ加えられるクロツクパルスφB1，φB2，φB3，φB4
は周波数的には撮像領域の電荷転送素子列１４に
加えられるクロツクパルス、φA1，φA2，φA3，φA4
の半分となつている。 FIG. 6a shows the transfer electrodes A 1 , A 2 , A 3 ,
Clock pulses φ A1 , φ A2 , φ A3 , applied to A4
φ A4 , clock pulses φ S1 , φ S2 applied to transfer electrodes S 1 , S 2 in the selected transfer gate region, clock pulses φ B1 , φ B2 applied to transfer electrodes B 1 , B 2 , B 3 , B 4 in the storage region , φ B3 and φ B4 represent a portion of the clock pulses when transferring from the imaging area to the storage area during vertical blanking. Charges in one column of charge transfer element columns 14 in the imaging region are sent to either of the two charge transfer element columns in the storage region by clock pulses φ S1 and φ S2 applied to the transfer electrodes of the selective transfer gate region 10. After the signal charges are sent to one constituent unit of two columns of the charge transfer element arrays 11 in the storage region, they are transferred in the direction of the readout region 4 by one constituent unit. Therefore, the charge transfer element array 11 in the storage region
Clock pulses applied to φ B1 , φ B2 , φ B3 , φ B4
are the clock pulses applied to the charge transfer element array 14 in the imaging region in terms of frequency, φ A1 , φ A2 , φ A3 , φ A4
It is half of that.
第６図ｂは蓄積領域の電荷転送素子列１１か
ら、選択読み出し転送ゲート領域１２を通つて読
み出し領域４へ送られるときのクロツクパルスで
ある。φB1，φB2，φB3，φB4は蓄積領域の転送電極
B1，B2，B3，B4に加えられるクロツクパルス
で、φBC1，φBC2，φVTは選択読み出し転送ゲート
領域の転送電極BC１，BC２，VTに加えられる
クロツクパルスで、φC1，φC2，φC3，φC4は読み出
し領域の転送電極に加えられるクロツクパルスで
ある。 FIG. 6b shows a clock pulse sent from the charge transfer element array 11 in the storage region to the readout region 4 through the selective readout transfer gate region 12. φ B1 , φ B2 , φ B3 , φ B4 are transfer electrodes in the storage region
φ BC1 , φ BC2 , φ VT are clock pulses applied to B 1 , B 2 , B 3 , B 4 , and φ C1 , φ C2 are clock pulses applied to transfer electrodes BC 1 , BC 2 , VT in the selected read transfer gate region . , φ C3 and φ C4 are clock pulses applied to the transfer electrodes in the readout area.
選択読み出し転送ゲート領域に隣接した転送電
極３０に送られてきた信号電荷はBC１，BC２転
送電極にφBC1，φBC2のクロツクパルスが印加され
ることによりBC１，BC２転送電極下に転送され
る。次に転送電極VTに加えられるクロツクパル
スφVTにより転送電極VT下に拡がる。このとき
転送電極VTに隣接した、読み出し領域の転送電
極３２にはポテンシヤル井戸を形成できるクロツ
ク電圧φC2が加えられている。この後転送電極BC
１，VTが閉じるため選択読み出しゲート転送領
域の転送電極BC１下の電荷は読み出し領域の転
送電極３２下に転送され読み出される。転送電極
BC２下の電荷は転送電極VT下まで拡がるが隣
接した読み出し領域の転送電極３４下にはクロツ
クパルスφC4によりポテンシヤル井戸が形成され
ていないため転送電極VTが閉じると再び転送電
極BC２下へ引き戻され、転送電極BC１から読み
出し領域へ移された信号電荷が読み出されるまで
蓄積される。 The signal charges sent to the transfer electrode 30 adjacent to the selective readout transfer gate region are transferred to the bottom of the BC1 and BC2 transfer electrodes by applying clock pulses φ BC1 and φ BC2 to the BC1 and BC2 transfer electrodes. Next, the signal is spread under the transfer electrode VT by the clock pulse φ VT applied to the transfer electrode VT. At this time, a clock voltage φ C2 capable of forming a potential well is applied to the transfer electrode 32 in the readout region adjacent to the transfer electrode VT. After this transfer electrode BC
1. Since VT is closed, the charges under the transfer electrode BC1 in the selected read gate transfer area are transferred to and read out under the transfer electrode 32 in the read area. transfer electrode
The charge under BC2 spreads to under the transfer electrode VT, but since no potential well is formed under the transfer electrode 34 in the adjacent readout area due to the clock pulse φC4 , when the transfer electrode VT closes, it is pulled back under the transfer electrode BC2. The signal charges transferred from the transfer electrode BC1 to the readout region are accumulated until they are read out.
これは１水平期間に相当しこの後再び転送電極
VTが開き今度はクロツクパルスφC4により読み
出し領域の転送電極３４下にポテンシヤル井戸が
できているため転送電極BC２，VTが閉じるに
ともない、読み出し領域の転送電極３４下へ転送
されることになる。読み出し領域に移された信号
電荷は水平読み出し期間内に読み出される。蓄積
領域から読み出し領域への転送は１水平ブランキ
ング期間内におこなわれる。 This corresponds to one horizontal period, after which the transfer electrode
VT is opened, and a potential well is created under the transfer electrode 34 in the readout area by the clock pulse φC4 , so as the transfer electrode BC2 and VT are closed, the data will be transferred to the bottom of the transfer electrode 34 in the readout area. The signal charges transferred to the readout area are read out within the horizontal readout period. Transfer from the storage area to the readout area is performed within one horizontal blanking period.
このように蓄積領域の２列の電荷転送素子列か
ら決められた順序で読み出し領域へ転送するため
読み出し領域の転送電極は１水平期間毎にその高
値、低値を変えることになる。φC1，φC3は本実施
例では、蓄積領域の２列の電荷転送素子列の電荷
を順序に読み出し領域へ送ることに関係しないた
め、１水平期間毎に変ることはない。 In this way, since charges are transferred from the two columns of charge transfer element columns in the storage region to the readout region in a predetermined order, the transfer electrodes in the readout region change their high and low values every horizontal period. In this embodiment, φ C1 and φ C3 do not change every horizontal period because they are not related to sequentially sending the charges of the two charge transfer element columns in the storage region to the readout region.
第７図は蓄積領域の２列の電荷転送素子列の信
号電荷を読み出し領域へ移すための選択読み出し
転送ゲート領域についての他の実施例である。本
実施例では蓄積領域の２列の電荷転送素子列の信
号電荷を読み出し領域の決つた転送電極に転送で
きるような構造となつている。選択読み出し転送
ゲート領域に隣接した転送電極３６に送られた信
号電荷は選択読み出し転送ゲート領域の転送電極
BC１が開き次に転送電極VT及び読み出し領域
の転送電極３９が開く。この時転送電極VT、３
９に加えるパルス電圧は転送電極３６、BC１に
加えられているパルス電圧より大きくする。この
ため転送電極３６BC１下に拡がつた信号電荷は
転送電極VT、３９下に移動する。この後BC１
を閉じることにより転送電極BC１側の電荷は転
送電極VT、３９へ完全に転送したことになる。
つづいて転送電極VTを閉じることにより、信号
電荷は転送電極Ｃ２に移ることになり、読み出し
領域へ転送されたことになる。この後水平読み出
し領域へ移された信号電荷は読み出される。この
一連の動作期間中転送電極BC２は閉じたままで
ある。読み出し領域から転送電極BC１側の信号
電荷が読み出されて後、転送電極BC２が開き、
転送電極BC１側の電荷を水平読み出し領域へ送
つたのと同じ動作で転送され、読み出される。第
８図は本実施例の駆動パルスの１例である。この
一連の転送動作例では、通常のクロツクパルス電
圧より高いクロツクパルス電圧を加えるのは転送
電極VTと３９になつているが転送電極VTのみ
に加えて転送させることも可能である。 FIG. 7 shows another embodiment of a selective readout transfer gate region for transferring signal charges from two rows of charge transfer element columns in an accumulation region to a readout region. In this embodiment, the structure is such that the signal charges in the two rows of charge transfer element columns in the storage region can be transferred to the determined transfer electrodes in the readout region. The signal charge sent to the transfer electrode 36 adjacent to the selective read transfer gate region is transferred to the transfer electrode of the selective read transfer gate region.
BC1 opens and then transfer electrode VT and readout area transfer electrode 39 open. At this time, transfer electrode VT, 3
The pulse voltage applied to the transfer electrode 36 and BC1 is made larger than the pulse voltage applied to the transfer electrode 36 and BC1. Therefore, the signal charge spread under the transfer electrode 36BC1 moves under the transfer electrode VT, 39. After this BC1
By closing the transfer electrode BC1, the charge on the transfer electrode BC1 side is completely transferred to the transfer electrode VT, 39.
Subsequently, by closing the transfer electrode VT, the signal charge is transferred to the transfer electrode C2, and thus transferred to the readout region. Thereafter, the signal charges transferred to the horizontal readout area are read out. During this series of operations, the transfer electrode BC2 remains closed. After the signal charge on the transfer electrode BC1 side is read out from the readout region, the transfer electrode BC2 opens,
The charges on the transfer electrode BC1 side are transferred and read out in the same operation as sending them to the horizontal readout area. FIG. 8 shows an example of the drive pulse of this embodiment. In this series of transfer operation examples, the clock pulse voltage higher than the normal clock pulse voltage is applied to the transfer electrode VT and 39, but it is also possible to apply the clock pulse voltage to the transfer electrode VT only.
本発明により蓄積領域の面積は半分になるばか
りでなく転送段数も半分ですむため転送効率の劣
化も少なくてすみ、その効果は極めて大きいもの
がある。従来垂直方向の転送効率の劣化のため、
特性不良が多数発生していたが、本発明を用いる
ことにより50％程度の飛躍的な改善がみられた。 According to the present invention, not only the area of the storage region is halved, but also the number of transfer stages is also halved, so there is less deterioration in transfer efficiency, and the effect is extremely large. Conventionally, due to the deterioration of vertical transfer efficiency,
Many characteristic defects had occurred, but by using the present invention, a dramatic improvement of about 50% was observed.
本実施例においては電荷転送素子列が４相駆動
について示してあるがそれ以外の駆動でも可能で
あることは勿論である。また電荷転送素子列が表
面型電荷転送素子列、埋め込み型電荷転送素子列
のいずれでも可能であることも勿論である。 In this embodiment, the charge transfer element array is shown to be driven in four phases, but it is of course possible to drive it in other ways. It goes without saying that the charge transfer element array can be either a surface type charge transfer element array or a buried type charge transfer element array.
第１図はフレームトランスフアータイプの従来
の撮像装置の構成図、第２図は蓄積領域の断面構
造図、第３図は本発明の電荷転送型固体撮像装置
の構成図、第４図は本発明の一実施例における電
荷転送型固体撮像装置の構成模式図、第５図ａ，
ｂは本発明の実施例の選択転送ゲート領域、選択
読み出し転送ゲート領域近辺の上面構造図、第６
図ａ，ｂは本発明の電荷転送型固体撮像装置に用
いる印加クロツクパルスの一例を示す図、第７図
は本発明の他の実施例における電荷転送型固体装
置の選択読み出し転送ゲート領域の上面構造図、
第８図はその印加クロツクパルスの一例を示す図
である。
４……読み出し領域、７……絶縁酸化膜、８…
…半導体基板、１０……選択転送ゲート領域、１
１……蓄積領域の電荷転送素子列、１２……選択
読み出し転送ゲート領域、１４……撮像領域の電
荷転送素子列。
FIG. 1 is a configuration diagram of a conventional frame transfer type imaging device, FIG. 2 is a cross-sectional structural diagram of a storage region, FIG. 3 is a configuration diagram of a charge transfer type solid-state imaging device of the present invention, and FIG. 4 is a diagram of the present invention. A schematic configuration diagram of a charge transfer solid-state imaging device in an embodiment of the invention, FIG. 5a,
b is a top view of the selective transfer gate region and the vicinity of the selective readout transfer gate region in the embodiment of the present invention;
Figures a and b are diagrams showing an example of applied clock pulses used in the charge transfer solid-state imaging device of the present invention, and Fig. 7 is a top view structure of the selected readout transfer gate region of the charge transfer solid-state device in another embodiment of the present invention. figure,
FIG. 8 is a diagram showing an example of the applied clock pulse. 4... Readout area, 7... Insulating oxide film, 8...
...Semiconductor substrate, 10...Selective transfer gate region, 1
1...Charge transfer element array in the storage region, 12...Selected readout transfer gate region, 14...Charge transfer element array in the imaging region.
Claims (1)
と、各列の前記光電変換素子に集積された信号電
荷をそれぞれの列方向に転送する複数個の第１の
電荷転送素子列と、前記第１の電荷転送素子列の
各列ごとに２列ずつ対応して設けられ、前記第１
の電荷転送素子列中の信号電荷が一時蓄積される
第２の電荷転送素子列と、前記第２の電荷転送素
子列中の２列ごとの信号電荷を交互に読み出して
光電変換素子に蓄積された信号電荷を行ごとに読
み出す読み出し領域と、前記第１の電荷転送素子
列の各列とその各列に対応する２列の第２の電荷
転送素子列との間に設けられ、前記第１の電荷転
送素子列中の信号電荷を前記第２の電荷転送素子
列の２列のそれぞれに選択的に転送する選択ゲー
ト領域と、前記第２の電荷転送素子列の２列と前
記読み出し領域との間に設けられ、前記第２の電
荷転送素子列２列中の信号電荷を選択的に前記読
み出し領域へ転送する選択読み出し転送ゲート領
域とを有することを特徴とする電荷転送型固体撮
像装置。 ２ 第２の電荷転送素子列の信号電荷が読み出し
領域へ転送されるとき、少なくとも選択読み出し
転送ゲート領域の転送電極の一部あるいは読み出
し領域の転送電極の一部に印加されるクロツクパ
ルス電圧が通常の転送パルス電圧より高いことを
特徴とする特許請求の範囲第１項記載の電荷転送
型固体撮像装置。[Scope of Claims] 1. A plurality of photoelectric conversion elements arranged in a matrix, and a plurality of first charge transfers that transfer signal charges accumulated in the photoelectric conversion elements in each column in the direction of each column. Two columns are provided corresponding to each column of the element column and the first charge transfer device column, and the first
A second charge transfer element column in which the signal charges in the charge transfer element column are temporarily accumulated; and signal charges in every two columns in the second charge transfer element column are read out alternately and stored in the photoelectric conversion element. a readout region for reading signal charges row by row; and a readout region provided between each column of the first charge transfer element column and two second charge transfer element columns corresponding to each column; a selection gate region for selectively transferring signal charges in the charge transfer element array to each of the two second charge transfer element arrays; and a selection gate region for selectively transferring signal charges in the charge transfer element array to each of the two second charge transfer element arrays; A charge transfer type solid-state imaging device comprising: a selective readout transfer gate region provided between the first and second rows of charge transfer elements for selectively transferring signal charges in the two second rows of charge transfer elements to the readout region. 2. When the signal charges of the second charge transfer element array are transferred to the readout region, the clock pulse voltage applied to at least a part of the transfer electrode of the selected readout transfer gate region or a part of the transfer electrode of the readout region is 2. The charge transfer solid-state imaging device according to claim 1, wherein the voltage is higher than the transfer pulse voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56022739A JPS57136873A (en) | 1981-02-18 | 1981-02-18 | Charge-transfer type solid-state image pickup device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56022739A JPS57136873A (en) | 1981-02-18 | 1981-02-18 | Charge-transfer type solid-state image pickup device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57136873A JPS57136873A (en) | 1982-08-24 |
| JPS6329872B2 true JPS6329872B2 (en) | 1988-06-15 |
Family
ID=12091083
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56022739A Granted JPS57136873A (en) | 1981-02-18 | 1981-02-18 | Charge-transfer type solid-state image pickup device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57136873A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5969965A (en) * | 1982-10-15 | 1984-04-20 | Canon Inc | Frame transfer type image pick-up element |
| JP2566217B2 (en) * | 1984-09-17 | 1996-12-25 | オリンパス光学工業株式会社 | Electronic shutter device |
| KR920003654B1 (en) * | 1987-04-10 | 1992-05-06 | 가부시끼가이샤 도시바 | Solid-state image device having high-speed shutter function |
| JP2614263B2 (en) * | 1987-04-10 | 1997-05-28 | 株式会社東芝 | Solid-state imaging device camera |
| JP2659712B2 (en) * | 1987-04-30 | 1997-09-30 | 株式会社東芝 | Charge transfer device |
| CN101647120B (en) * | 2007-03-30 | 2012-05-16 | 松下电器产业株式会社 | CCD image pickup device with double frames storage and method using the same |
-
1981
- 1981-02-18 JP JP56022739A patent/JPS57136873A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57136873A (en) | 1982-08-24 |
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