JPS63296412A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS63296412A JPS63296412A JP62132193A JP13219387A JPS63296412A JP S63296412 A JPS63296412 A JP S63296412A JP 62132193 A JP62132193 A JP 62132193A JP 13219387 A JP13219387 A JP 13219387A JP S63296412 A JPS63296412 A JP S63296412A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- semiconductor integrated
- integrated circuit
- output signal
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 241000625014 Vir Species 0.000 abstract 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000001681 protective effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Landscapes
- Logic Circuits (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
- Electronic Switches (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置に関し、特に静電保護回路
を有する半導体集積回路装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having an electrostatic protection circuit.
従来、この種の半導体集積回路装置は、第３図に示す様
に出力信号パッド５は、電源配線１と電源配線２との間
に、それぞれ静電保護素子３および４を接続していた。Conventionally, in this type of semiconductor integrated circuit device, as shown in FIG. 3, the output signal pad 5 has electrostatic protection elements 3 and 4 connected between the power supply wiring 1 and the power supply wiring 2, respectively.
上述した従来の同電源配線が電源配線１と電源配線２と
に分離された半導体集積回路装置では、出力信号パッド
５から電源配線１および電源配線２間にそれぞれ静電保
護素子３および４を接続していた。その為、半導体集積
回路装置の個々の出力回路に静電保護素子が２個必要と
なり、半導体集積回路装置が大きくなってしまうという
欠点がある。In the conventional semiconductor integrated circuit device described above in which the same power supply wiring is separated into power supply wiring 1 and power supply wiring 2, electrostatic protection elements 3 and 4 are connected from output signal pad 5 to power supply wiring 1 and power supply wiring 2, respectively. Was. Therefore, two electrostatic protection elements are required for each output circuit of the semiconductor integrated circuit device, which has the drawback of increasing the size of the semiconductor integrated circuit device.
本発明の目的は、上記欠点を除去し対静電気にも強くて
より小型化にすることができる半導体集積回路装置を提
供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device which eliminates the above drawbacks, is resistant to static electricity, and can be made more compact.
本発明の半導体集積回路装置の構成は、パッド出力用ト
ランジスタの第１の高電位側電源配線およびそれと同電
位である同トランジスタ前段までの内部論理部の第２の
高電位側電源配線とが分離された半導体集積回路装置の
前記第１および第２の高電位側電源配線間にダイオード
を双方向に接続する事を特徴とする。In the configuration of the semiconductor integrated circuit device of the present invention, the first high-potential side power supply wiring of the pad output transistor and the second high-potential side power supply wiring of the internal logic section up to the previous stage of the same transistor, which are at the same potential, are separated. The semiconductor integrated circuit device is characterized in that a diode is bidirectionally connected between the first and second high-potential side power supply wirings.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の半導体集積回路装置の出力
信号端子部の回路および静電保護回路の回路図、第２図
は第１図の静電保護回路のダイオードを多段にした回路
図である。FIG. 1 is a circuit diagram of the output signal terminal circuit and electrostatic protection circuit of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of the electrostatic protection circuit of FIG. 1 in which diodes are arranged in multiple stages. It is a diagram.
第１図および第２図で、１および２は分離された高電位
電源配線、３は静電保護素子、５は出力信号パッド、６
，７は静電保護用ダイオード、８は出力信号用トランジ
スタである。In Figures 1 and 2, 1 and 2 are separated high-potential power supply wirings, 3 is an electrostatic protection element, 5 is an output signal pad, and 6
, 7 are electrostatic protection diodes, and 8 is an output signal transistor.
第１１図の出力信号用トランジスタ８および同トランジ
スタ前段までの内部論理部高電位側電源配線１および２
との間に静電保護用ダイオード６を双方向に半導体集積
回路装置内の１ケ所及び数ケ所に接続する事により、両
電源配線１と２間の電位差を高々ダイオードの順方向電
圧とすることができるので、出力信号パッド５から出力
信号用トランジスタ８の高電位側電源配線１と同電位の
同トランジスタ前段までの内部論理部電源配線２の間に
接続している静電保護素子３または４のどちらか一方を
不要とすることができる。The output signal transistor 8 and the internal logic section high potential side power supply wiring 1 and 2 up to the stage before the transistor in Fig. 11
By connecting an electrostatic protection diode 6 bidirectionally to one or several locations in the semiconductor integrated circuit device between the two power supply lines 1 and 2, the potential difference between the two power supply lines 1 and 2 can be made to be at most the forward voltage of the diode. Therefore, the electrostatic protection element 3 or 4 connected between the output signal pad 5 and the high potential side power supply wiring 1 of the output signal transistor 8 and the internal logic power supply wiring 2 up to the previous stage of the same transistor at the same potential. Either one can be made unnecessary.
従って、半導体集積回路装置の素子数を低減でき、半導
体集積回路装置面積を小さくできる。Therefore, the number of elements in the semiconductor integrated circuit device can be reduced, and the area of the semiconductor integrated circuit device can be reduced.
第２図では静電保護回路において、出力信号用トランジ
スタ８の高電位側電源配線１と同トランジスタ前段まで
の内部論理部高電位側電源配線２の間に双方向に接続し
ている静電保護用ダイオード７を多段にする事により、
出力信号用トランジスタ８の高電位型電源配線１と同電
位である同トランジスタ前段までの内部論理部高電位側
電源配線２間のノイズマージンを大きく採る事が出来る
。In the electrostatic protection circuit shown in FIG. 2, the electrostatic protection circuit is bidirectionally connected between the high potential side power supply wiring 1 of the output signal transistor 8 and the high potential side power supply wiring 2 of the internal logic section up to the previous stage of the same transistor. By making the diode 7 multistage,
A large noise margin can be provided between the high-potential power supply wiring 1 of the output signal transistor 8 and the internal logic high-potential power supply wiring 2 of the same potential up to the previous stage of the same transistor.
以上説明した如く、本発明によれば、半導体集積回路装
置内の出力信号用トランジスタの高電位側電源配線と、
それと同電位である同トランジスタ前段までの内部論理
部高電位電源配線間に半導体集積回路装置内の１ケ所な
いし数ケ所に静電保護用ダイオードを双方向に接続する
事により、ある出力信号パッドと出力信号用トランジス
タの高電位側電源配線間か、もしくは出力信号パッドと
同電位である同トランジスタ前段までの内部論理部高電
源配線間に接続されている静電保護素子のどちらか一方
を削減する事ができるので半導体集積回路装置内に有す
る素子数を低減させ装置面積を小さくできる効果がある
。As explained above, according to the present invention, the high potential side power supply wiring of the output signal transistor in the semiconductor integrated circuit device,
By bidirectionally connecting an electrostatic protection diode at one or several locations in the semiconductor integrated circuit device between the internal logic section high potential power supply wiring up to the previous stage of the same transistor, which has the same potential, a certain output signal pad and Eliminate either the electrostatic protection element connected between the high-potential side power supply wiring of the output signal transistor or between the high-power supply wiring of the internal logic section up to the previous stage of the same transistor, which has the same potential as the output signal pad. This has the effect of reducing the number of elements included in a semiconductor integrated circuit device and reducing the device area.
尚、同電位の高電位側電源配線と内部論理部高電位側電
源間に接続する双方向の静電保護用ダイオードを多段に
する事で両電源配線に乗るノイズに対して、多段に組む
ダイオードの順方向電圧の総合電圧までマージンが採れ
るという効果がある。In addition, multi-stage bidirectional electrostatic protection diodes are connected between the high-potential side power supply wiring of the same potential and the internal logic high-potential side power supply to prevent noise from riding on both power supply wirings. This has the effect of allowing a margin up to the total forward voltage of .
第１図は本発明の一実施例の半導体集積回路装置の出力
信号端子部の回路および静電保護回路の回路図、第２図
は第１図の静電保護回路のダイオードを多段にした回路
図、第３図は従来の出力信号用トランジスタの高電位側
電源配線と、それと同電位である同トランジスタ前段ま
での内部論理部高電位側電源配線を分離している半導体
集積回路装置の出力信号端子部の回路図である。
１・・・出力信号用トランジスタの前段までの内部論理
部高電位側電源配線、２・・・内部論理部高電位側電源
配線と同電位側電源配線、３．４・・・静電保護素子、
５・・・出力信号パッド、６．７・・・静電保護第１０
ｒＪｚ図
芳３図FIG. 1 is a circuit diagram of the output signal terminal circuit and electrostatic protection circuit of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of the electrostatic protection circuit of FIG. 1 in which diodes are arranged in multiple stages. Figure 3 shows the output signal of a semiconductor integrated circuit device in which the conventional high-potential side power supply wiring of an output signal transistor is separated from the high-potential side power supply wiring of the internal logic section up to the previous stage of the same transistor, which is at the same potential. It is a circuit diagram of a terminal part. 1... Internal logic section high potential side power supply wiring up to the stage before the output signal transistor, 2... Internal logic section high potential side power supply wiring and the same potential side power supply wiring, 3.4... Electrostatic protection element ,
5... Output signal pad, 6.7... Electrostatic protection No. 10 rJz Diagram 3
Claims (1)
よびそれと同電位である同トランジスタ前段までの内部
論理部の第２の高電位側電源配線とが分離された半導体
集積回路装置の前記第１および第２の高電位側電源配線
間にダイオードを双方向に接続する事を特徴とする半導
体集積回路装置。A semiconductor integrated circuit device in which a first high-potential side power supply wiring of a pad output transistor and a second high-potential side power supply wiring of an internal logic section up to a stage before the same transistor, which is at the same potential as the first high-potential side power supply wiring, are separated from each other. A semiconductor integrated circuit device characterized in that a diode is bidirectionally connected between second high-potential side power supply wirings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62132193A JPH088480B2 (en) | 1987-05-27 | 1987-05-27 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62132193A JPH088480B2 (en) | 1987-05-27 | 1987-05-27 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63296412A true JPS63296412A (en) | 1988-12-02 |
| JPH088480B2 JPH088480B2 (en) | 1996-01-29 |
Family
ID=15075572
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62132193A Expired - Fee Related JPH088480B2 (en) | 1987-05-27 | 1987-05-27 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH088480B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03210817A (en) * | 1990-01-12 | 1991-09-13 | Nec Corp | Semiconductor integrated circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54966A (en) * | 1977-06-06 | 1979-01-06 | Mitsubishi Electric Corp | Logic circuit |
-
1987
- 1987-05-27 JP JP62132193A patent/JPH088480B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54966A (en) * | 1977-06-06 | 1979-01-06 | Mitsubishi Electric Corp | Logic circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03210817A (en) * | 1990-01-12 | 1991-09-13 | Nec Corp | Semiconductor integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH088480B2 (en) | 1996-01-29 |
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