JPS63287080A - Manufacture of semiconductor laser - Google Patents
Manufacture of semiconductor laserInfo
- Publication number
- JPS63287080A JPS63287080A JP62121182A JP12118287A JPS63287080A JP S63287080 A JPS63287080 A JP S63287080A JP 62121182 A JP62121182 A JP 62121182A JP 12118287 A JP12118287 A JP 12118287A JP S63287080 A JPS63287080 A JP S63287080A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- current
- groove
- inp
- grow
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000010410 layer Substances 0.000 claims abstract description 87
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000011241 protective layer Substances 0.000 claims abstract description 8
- 239000007791 liquid phase Substances 0.000 claims abstract description 5
- 238000005253 cladding Methods 0.000 claims description 18
- 230000000903 blocking effect Effects 0.000 claims description 9
- 230000010355 oscillation Effects 0.000 abstract description 9
- 208000031481 Pathologic Constriction Diseases 0.000 abstract 1
- 238000004943 liquid phase epitaxy Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 6
- 230000003287 optical effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- MODGUXHMLLXODK-UHFFFAOYSA-N [Br].CO Chemical compound [Br].CO MODGUXHMLLXODK-UHFFFAOYSA-N 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000010356 wave oscillation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/1028—Coupling to elements in the cavity, e.g. coupling to waveguides adjacent the active region, e.g. forward coupled [DFC] structures
- H01S5/1032—Coupling to elements comprising an optical axis that is not aligned with the optical axis of the active region
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Weting (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
この発明は、基本縦そ−ド発振する半導体レーザの製造
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor laser that performs basic longitudinal wave oscillation.
(従来の技術)
従来、縦単一モード発振が可能な半導体レーザとして、
D B R(pistributad Bragg R
eflector )型半導体レーザが提案されている
。第4図は文献:第46回応用物理学会学術講演会予稿
集、 1985年、206頁、2P−N−9,2P−N
−10に開示された従来の埋込み型fiunde −I
nlegratad Guide構造DBR(BH−L
B工G−DBR)半導体レーザの構造図であり、第5図
(a)〜(d)はその製造の工程図である。(Conventional technology) Conventionally, as a semiconductor laser capable of longitudinal single mode oscillation,
DBR (pistributad Bragg R)
effrector) type semiconductor lasers have been proposed. Figure 4 is a reference: Proceedings of the 46th Academic Conference of the Japan Society of Applied Physics, 1985, 206 pages, 2P-N-9, 2P-N
-10 The conventional implantable fiunde -I disclosed in
nlegratad Guide structure DBR (BH-L
FIG. 5A is a structural diagram of a semiconductor laser (G-DBR), and FIGS. 5A to 5D are process diagrams of its manufacturing process.
まずhp−InP基板12上に、p−1nP下側り2ラ
ド層13 、 GaInAsP活性層14、n−InP
保護層15を液相エピタキシャル成長(’L P E
)法で。First, on the hp-InP substrate 12, a p-1nP lower two-rad layer 13, a GaInAsP active layer 14, and an n-InP
The protective layer 15 is grown by liquid phase epitaxial growth ('L P E
) in law.
順次に形成する(第5図(a)参照)。次に、n−In
P保護層15とGaInAsP活性層14の不要部分を
エツチングで除去し、一部、p−InP下側クラッド層
13の表面が露出するようにし、この部分に通常のホロ
グラフィックリングラフィ技術により適正なピットと深
さをもつ友グレーティング1’3a(但し1これを波形
、 corrugationともいう)を形成する(第
5図(b)参照)。このグレーティング13aのついた
部分は、外部導波路領域13bとして機能する。They are formed sequentially (see FIG. 5(a)). Next, n-In
Unnecessary portions of the P protective layer 15 and the GaInAsP active layer 14 are removed by etching to expose a portion of the surface of the p-InP lower cladding layer 13, and this portion is etched using a normal holographic phosphorography technique. A companion grating 1'3a (also referred to as corrugation) having pits and depth is formed (see FIG. 5(b)). The portion with the grating 13a functions as an external waveguide region 13b.
次に、2回目のLPE法によ’) n−GaInAsP
外部導波路層16.n−InP上側クラッド層17を全
面に順次に形成する(第5図(C)参照)。次に横モー
ド制御及び電流狭窄の九めに通常の埋込み型中導体レー
ザの製造方法と同じように、フオlソグラフイ技術、化
学エツチングによ、9(011)方向に逆メサ型ストラ
イプ18を形成する(第5図(d)参照)。活性層14
の幅Wは安定した横モード発振するように適正な幅にす
るが、上記文献によれば2〜3μmである。次に、第3
回目のLPE法で逆メサ型ストライプ18をn−InP
第1電流狭窄層19及びp−InP第2電流狭窄層20
で埋込む(第4図参照)。Next, by the second LPE method') n-GaInAsP
Outer waveguide layer 16. An n-InP upper cladding layer 17 is sequentially formed over the entire surface (see FIG. 5(C)). Next, in the ninth stage of transverse mode control and current confinement, an inverted mesa-shaped stripe 18 is formed in the 9 (011) direction using phosphorography technology and chemical etching in the same way as in the manufacturing method of ordinary buried medium conductor lasers. (See Figure 5(d)). Active layer 14
The width W is set to an appropriate width for stable transverse mode oscillation, and according to the above-mentioned document, it is 2 to 3 μm. Next, the third
In the second LPE process, the inverted mesa stripe 18 was formed using n-InP.
First current confinement layer 19 and p-InP second current confinement layer 20
(See Figure 4).
次に、n−InP上側クラッド層17とp−InP第2
電流狭窄層20の表面にsio!等の絶縁膜21を形成
し% GaInAsP活性層14のある活性領域13c
の上部でn−InP上側クラッド層17の部分に電極用
窓を開ける(第4図参照)。なお、第4図には示してな
いが、絶縁膜21を含むn−InP上側クラッド層17
側全面に負電極を、p−InP基板12側に正電極を各
々形成して半導体レーザを得る。Next, the n-InP upper cladding layer 17 and the p-InP second
sio! on the surface of the current confinement layer 20. An active region 13c with a GaInAsP active layer 14 is formed.
An electrode window is opened in the upper part of the n-InP upper cladding layer 17 (see FIG. 4). Although not shown in FIG. 4, the n-InP upper cladding layer 17 including the insulating film 21
A negative electrode is formed on the entire side, and a positive electrode is formed on the p-InP substrate 12 side to obtain a semiconductor laser.
次に動作について説明する。図示しない両電極に適正な
バイアスをかけると電流はp −InP基板12側から
n−InP上側クラッド層17上部の窓型電極の負電極
に流れる。この負電極が活性領域13cの上部にある窓
型電極であるため、グレーティング13aのついた外部
導波路領域13bに電流はあま9流れない。ま友、埋込
み層部分ではn−InP第1電流狭窄層19とp−In
P第2電流狭゛デ層2゜の界面が逆バイアスになるため
に電流が流れない。Next, the operation will be explained. When a proper bias is applied to both electrodes (not shown), a current flows from the p-InP substrate 12 side to the negative electrode of the window-type electrode above the n-InP upper cladding layer 17. Since this negative electrode is a window-type electrode located above the active region 13c, no current flows through the external waveguide region 13b provided with the grating 13a. Mayu, in the buried layer part, the n-InP first current confinement layer 19 and the p-In
Since the interface of the P second current narrowing layer 2° is reverse biased, no current flows.
活性領域13cは順バイアスのために活性層14に電流
が流れて光が発生し、この光は外部導波路領域13bに
導波され、グレーティング13mでブラッグ反射され、
縦単一モードで発振する。この場合、外部導波路領域1
3bには光の損失が小さくなるように電流を流さないよ
うにする方がより発振効率がよくなる。In the active region 13c, a current flows through the active layer 14 due to the forward bias, and light is generated. This light is guided to the external waveguide region 13b, Bragg-reflected by the grating 13m,
Oscillates in a single vertical mode. In this case, the outer waveguide region 1
The oscillation efficiency will be better if no current is allowed to flow through 3b so as to reduce optical loss.
(発明が解決しようとする問題点)
しかし、以上述べた製造方法であっても外部導波路領域
13bでの光損失を少なくするために電流を流さなくす
る場合、 Sin、等の絶縁膜21により電極を活性領
域13cの上部に窓型に形成することで行っているが、
この場合、n−InP上側クラッド層17で電流が拡が
るためどうしてもかなシの電流が外部導波路領域13b
に流れて損失が大きくなり、従って発振効率が悪くなっ
て低閾値電流及び高出力が得られなく、技術的に満足で
きるものは得られなかり九。(Problems to be Solved by the Invention) However, even with the manufacturing method described above, when the current is not allowed to flow in order to reduce optical loss in the external waveguide region 13b, the insulating film 21 such as Sin is used. This is done by forming an electrode in a window shape above the active region 13c.
In this case, since the current spreads in the n-InP upper cladding layer 17, a small current inevitably flows into the external waveguide region 13b.
The loss increases due to the current flow, and the oscillation efficiency deteriorates, making it impossible to obtain a low threshold current and high output, making it impossible to obtain a technically satisfactory result.9.
この発明は1以上述べ友外部導波路領域での大きな光損
失に帰因する発振効率の低下という問題点を除去し、高
発振効率で低閾値電流、かつ高出力の動作が可能な半導
体レーザの製造方法を提供することを目的とする。The present invention eliminates the problem of reduced oscillation efficiency caused by large optical loss in the external waveguide region as described above, and provides a semiconductor laser capable of operating with high oscillation efficiency, low threshold current, and high output. The purpose is to provide a manufacturing method.
(問題点を解決するための手段)
この発明に係る半導体レーザの製造方法は、下側クラッ
ド層上の一部にグレーティングを形成するBH−BIG
−DBR型半導体レーザの製造方法において、(100
)表面を有する半導体基板に側面が(111)A面で〔
011〕方向に長い複数の溝を(011)方向に形成し
、溝以外の表面に電流ブロック層を選択的にLPEで形
成し、更にバッファ層をLPEで全面に形成するように
したものである。(Means for Solving the Problems) A method for manufacturing a semiconductor laser according to the present invention includes a method for manufacturing a BH-BIG semiconductor laser in which a grating is formed on a portion of a lower cladding layer.
- In a method of manufacturing a DBR type semiconductor laser, (100
) with a (111)A side surface [
A plurality of long grooves are formed in the (011) direction, a current blocking layer is selectively formed on the surface other than the grooves using LPE, and a buffer layer is further formed on the entire surface using LPE. .
(作用) この発明における半導体レーザの製造方法は。(effect) A method of manufacturing a semiconductor laser according to the present invention is as follows.
LPEの成長速度の面方位依存性を利用して電流ブロッ
ク層を溝以外の表面に形成し、電流ブロック層とその上
のバッファ層とで逆バイアス層を作り、この上にあるグ
レーティングの外部導波領域に電流を流さないようにす
る。A current blocking layer is formed on the surface other than the groove by utilizing the plane orientation dependence of the growth rate of LPE, and a reverse bias layer is created with the current blocking layer and the buffer layer above it, and the external conduction of the grating on this layer is Avoid passing current into the wave region.
(実施例)
以下、この発明の一実施例を図面に基づいて詳細に説明
する。第1図乃至第3図はこの発明の一実施例を示す工
程図である。まず、(100)表面を有するp−InP
基板l上にエツチングマスク、例えばSiO!膜2を形
成し、(OIT:]方向に長い多数個のエツチング用窓
2aを(011)方向に列状にして開ける(第1図(a
)参照)。sio、膜2の厚さは0.2μm程度で、エ
ツチング用窓2aの寸法は、(0111方向の寸法Wa
が1.5〜3μm、 (OIT〕方向の寸法静か約5μ
mであシ、エッチング用窓2a同士の間隔Wcが0.5
〜1.5μm1エツチング用窓2aの(011)方向の
配列全幅Wdが150〜2004mにする。次に、臭素
−メタノール液を用いてp−InP基板1’にエツチン
グ用窓2a等からエツチングして溝1aを形成し、この
後KStO,膜2を除去する(第1図(b)参照)。第
1図(0)は第111N(b)のA −A’断面即ち〔
011〕方向に沿った断面の状態を示し、第1図(d)
はB −8’断面即ち〔O11〕方向に沿つ次断面の状
態を示す。第1図(e)及び同図(d)に示したような
谷溝1aの深さを約0.2μmにするとその溝laの側
面には(111)A面が現われ、その溝1aの底面は彎
曲した面(面方位はないが(111)A面のような性質
をもつ面)になる。(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings. 1 to 3 are process diagrams showing one embodiment of the present invention. First, p-InP with (100) surface
An etching mask, for example SiO!, is placed on the substrate l. A film 2 is formed, and a large number of long etching windows 2a are opened in the (011) direction in a row in the (011) direction (see FIG. 1(a)).
)reference). The thickness of the film 2 is approximately 0.2 μm, and the dimensions of the etching window 2a are (dimension Wa in the 0111 direction).
is 1.5 to 3μm, and the dimension in the (OIT) direction is approximately 5μm.
m, and the distance Wc between the etching windows 2a is 0.5
~1.5 μm The total array width Wd of each etching window 2a in the (011) direction is set to 150 to 2004 m. Next, a groove 1a is formed by etching the p-InP substrate 1' through the etching window 2a using a bromine-methanol solution, and then the KStO and film 2 are removed (see FIG. 1(b)). . Figure 1 (0) is the A-A' cross section of No. 111N (b), that is, [
FIG. 1(d) shows the state of the cross section along the [011] direction.
shows the state of the B-8' cross section, that is, the next cross section along the [O11] direction. When the depth of the valley groove 1a as shown in FIGS. 1(e) and 1(d) is set to about 0.2 μm, a (111)A surface appears on the side surface of the groove la, and the bottom surface of the groove 1a becomes a curved surface (a surface with properties similar to the (111) A surface, although there is no surface orientation).
次に、溝1a′ff:設は友p−InP基板l上に第1
回目のLPE法でn−InP電流ブロック層3、p−G
aInAsPバッファ層4.p−InP下側クラッド層
5、GaInAsP活性層6、n−InP保護層7を順
次に成長させる(第2図(a)及び同図(切参照)。但
し、第2図(a)は第1図(c)と同様の断面、第2図
(b)は第1図(d)と同様の断面である。この成長に
おいて、n−InP電流電流クロッ2層31aがエツチ
ング用窓2aと略同等の寸法であれば成長温度600℃
程度で、溝1a内部には全く成長しない。これはLPE
法特有の性質で、 InPは(111)A面が(10
0)面に比して著るしく成長しにくいことを利用してい
る。また% n−(np電電流クロッ2層3溝1a同士
の間の(100)面には多少成長する場合があるが、レ
ーザの特性上ら″!jシ問題にならない。p−GaIn
AsPバッファ層4はInPに比して成長の面方位依存
性がな(、(111)A面つまシ溝1aの内部において
も(100)表面と同様に成長可能であり、また、その
上へのp−InP下側クラッド層5以降の層も全面に成
長可能である。p−InP下側クラッド層5は活性層6
との界面が平担になる迄成長させる。Next, the groove 1a'ff is set on the p-InP substrate l.
In the second LPE method, the n-InP current blocking layer 3 and the p-G
aInAsP buffer layer 4. The p-InP lower cladding layer 5, the GaInAsP active layer 6, and the n-InP protective layer 7 are grown in sequence (see FIG. 2(a) and the same figure (cut)). However, FIG. 1(c), and FIG. 2(b) is a cross-sectional view similar to FIG. 1(d).In this growth, the n-InP current current block 2 layer 31a is formed into an etching window 2a. If the dimensions are the same, the growth temperature is 600℃.
It does not grow inside the groove 1a at all. This is LPE
Due to the unique property of InP, the (111) A side is (10
0) It takes advantage of the fact that it is significantly difficult to grow compared to the surface. In addition, some growth may occur on the (100) plane between the 2 layers 3 grooves 1a of the %n-(np current crystals, but this does not pose a problem due to the characteristics of the laser.p-GaIn
Compared to InP, the AsP buffer layer 4 has less dependence on the plane orientation of growth (it can grow inside the (111) A-plane groove 1a in the same way as on the (100) surface, and can grow on the (100) surface. It is also possible to grow the layers after the p-InP lower cladding layer 5 on the entire surface.
Let it grow until the interface with it becomes flat.
以下の工程は従来のBH−BIG−DBR半導体レーデ
の製造方法とほぼ同じである。i*−InP保護層7と
GaInAaP活性層6の不要部分をエツチングで除去
し、溝1mがある部分よ!D (011)方向側のp−
InP下側クラッド層5の表面が露出するようにし、そ
とに通常のホログラフィックリングラフィ技術を用いて
適正なピッチと深さをもつ次グレーティング5aを形成
する(第2図(e)参照)。The following steps are almost the same as those for manufacturing a conventional BH-BIG-DBR semiconductor radar. Unnecessary parts of the i*-InP protective layer 7 and GaInAaP active layer 6 are removed by etching, and this is the part where the groove 1m is located! D p- on the (011) direction side
The surface of the InP lower cladding layer 5 is exposed, and a sub-grating 5a having an appropriate pitch and depth is formed thereon using a normal holographic phosphorography technique (see FIG. 2(e)). .
次に第2回目のLPE法でn−GaInAsP外部導波
路層8、n−InP上側り2ラド層9を全面に順次に形
成する(第2図(d)参照)。Next, by a second LPE method, an n-GaInAsP external waveguide layer 8 and an n-InP upper two rad layer 9 are sequentially formed over the entire surface (see FIG. 2(d)).
次に、第3図(a)に示すように従来のBH−BIG−
DBR半導体レーザの製造方法と同じように逆メサ型ス
トライプMを形成する几めに逆メサ状にエツチングで不
要部分を取除く。この逆メサ型ストライプMは溝l&の
上に位置するように(011〕方向に形成する。逆メサ
の「くびれ」となる部分5bは従来型とほぼ同じでよく
、図ではp−InP下側クラッド層5にある場合で、n
−InP電流ブロック層3の一部が露出する迄エツチン
グした例を示す。次に、第3回目のLPE法でn−In
P第1電流狭窄層10.p−InP第2電流狭窄層11
.全成長させ、逆メサ型ストライプMを埋込む(第3図
(b)参照)。Next, as shown in Fig. 3(a), the conventional BH-BIG-
In the same way as the method for manufacturing a DBR semiconductor laser, unnecessary portions are removed by etching in an inverted mesa shape to form an inverted mesa stripe M. This inverted mesa stripe M is formed in the (011) direction so as to be located above the groove l&.The "neck" part 5b of the inverted mesa may be almost the same as that of the conventional type, and in the figure, it is located below the p-InP. In the case of cladding layer 5, n
An example is shown in which the -InP current blocking layer 3 is etched until a part of it is exposed. Next, in the third LPE method, n-In
P first current confinement layer 10. p-InP second current confinement layer 11
.. The entire structure is grown, and an inverted mesa stripe M is buried (see FIG. 3(b)).
電極については、従来型BH−BIG−DBR半導体レ
ーザと同じ電極か又は正、負電極どちらも全面電極にし
てもよい。Regarding the electrodes, the same electrodes as those of the conventional BH-BIG-DBR semiconductor laser may be used, or both the positive and negative electrodes may be full-surface electrodes.
か\る製法により製造した半導体レーザを全面電極で正
常なバイアスをかけて動作させると第3図(b)のx印
部分が逆バイアスとなり、外部導波路領域となるグレー
ティング5aの部分には電流が流れない。即ち、n−I
nP電流電流クロッ2層3−GaInAsPバッファ層
4との境界面やn−InP第1電流狭窄層ioとp−I
nP第2電流狭窄層11との境界面が逆バイアスとなり
、n−InP電流電流クロッ2層3−GaInAsPバ
ッファ層4との境界面上にあるグレーティング5aの部
分には電流が流れない。When a semiconductor laser manufactured by such a manufacturing method is operated with a normal bias applied to the entire surface electrode, the part marked with an x in FIG. does not flow. That is, n-I
The interface between the nP current current block 2 layer 3 and the GaInAsP buffer layer 4 and the n-InP first current confinement layer io and p-I
The interface with the nP second current confinement layer 11 becomes a reverse bias, and no current flows through the portion of the grating 5a on the interface between the n-InP current block layer 2 layer 3 and the GaInAsP buffer layer 4.
以上の説明ではp−InP基板を用い次場合を例にとっ
て説明したが、n−InP基板を用いても導電型を反転
させるだけで全く同じようにして半導体レーザを製造で
きる。In the above description, a p-InP substrate was used and the following case was explained as an example. However, even if an n-InP substrate is used, a semiconductor laser can be manufactured in exactly the same manner by simply reversing the conductivity type.
(発明の効果) 以上のようにこの発明の製造方法によれば。(Effect of the invention) According to the manufacturing method of the present invention as described above.
BH−BIG−DBR型半導体レーザの製造方法におい
て、LPE法の成長速度の面方位依存性を利用し、半導
体基板に設けt溝以外のその表面に電流ブロック層を選
択的に形成し、その上のバッファ層とで逆バイアス部分
を作り、その上のグレーティングのある外部導波路領域
に電流を流さないようKしたので、低損失な導波領域と
な夛発振効率がよく、低閾値電流、高出力動作が可能と
なり、しかも従来のものと同じく3回のLPEで製造が
可能となるものが期待出来るのである。In a method for manufacturing a BH-BIG-DBR type semiconductor laser, a current blocking layer is selectively formed on the surface of a semiconductor substrate other than the T-groove by utilizing the plane orientation dependence of the growth rate of the LPE method, and then Since we created a reverse bias area with the buffer layer and set it so that no current flows into the external waveguide area with the grating above it, we created a low-loss waveguide area with good oscillation efficiency, low threshold current, and high It can be expected that output operation will be possible, and that manufacturing will be possible in three LPEs, as with conventional products.
第1図乃至第3図はこの発明の一実施例による半導体レ
ーザの製造方法を示す各工程図、第4図は従来のBH−
BIG−DBR半導体レーデの構造図、第5図は従来の
BH−BIG−DBR半導体レーザの製造方法を示す工
程図である。
1=p−InP基板、la”−溝、2 ・Sin、膜。
2a・・・エツチング用窓、3・・・n−InP電流電
流クロッ2層 ・・・P−GaInAsPバッファ層、
5 ”・p −InP下側クラッド層、5a・・・
グレーティング、6・・・Ga In、As P活性層
、7・・・n−InP保護層、8・・・外部導波路層、
9・・・n−InP上側クラッド層、10・・・n−I
nP第1電流狭窄層−1ll・・・p−InP第2電流
狭窄層、M・・・逆メサ型ストライプ。
第1図
¥55FIA
第5図1 to 3 are process diagrams showing a method for manufacturing a semiconductor laser according to an embodiment of the present invention, and FIG. 4 is a conventional BH-
A structural diagram of a BIG-DBR semiconductor laser, and FIG. 5 is a process diagram showing a method of manufacturing a conventional BH-BIG-DBR semiconductor laser. 1 = p-InP substrate, la"-groove, 2 - Sin, film. 2a... window for etching, 3... n-InP current current block 2 layer... P-GaInAsP buffer layer,
5”.p-InP lower cladding layer, 5a...
grating, 6... Ga In, AsP active layer, 7... n-InP protective layer, 8... external waveguide layer,
9...n-InP upper cladding layer, 10...n-I
nP first current confinement layer-1ll...p-InP second current confinement layer, M...inverted mesa type stripe. Figure 1 ¥55FIA Figure 5
Claims (1)
A面で〔01@1@〕方向に長い複数の溝を〔011〕
方向に形成する第1工程と、 次に、電流ブロック層、該電流ブロック層とは逆導電型
のバッファ層、下側クラッド層、活性層、保護層を順次
に液相エピタキシャル成長させ、上記電流ブロック層を
上記溝以外の部分に選択的に成長させ、上記下側クラッ
ド層上部では全面を平担化させる第2工程と、 次に、上記保護層及び活性層の一部をエッチングで選択
的に取除き、露出した上記下側クラッド層上にグレーデ
ィングを形成する第3工程と、次に、外部導波路層、上
側クラッド層を順に液相エピタキシャル成長させる第4
工程と、 次に、上記溝の上部で〔011〕方向に逆メサ型ストラ
イプを形成し、第1電流狭窄層、第2電流狭窄層を順に
液相エピタキシャル成長させて上記逆メサ型ストライプ
を埋込む第5工程とを備えた半導体レーザの製造方法。[Claims] A semiconductor substrate having a (100) surface and a side surface having (111)
Create multiple long grooves in the [01@1@] direction on the A side [011]
Next, a current blocking layer, a buffer layer of the opposite conductivity type to the current blocking layer, a lower cladding layer, an active layer, and a protective layer are sequentially grown by liquid phase epitaxial growth to form the current blocking layer a second step of selectively growing the layer in areas other than the grooves and flattening the entire surface on the upper part of the lower cladding layer, and then selectively etching a part of the protective layer and the active layer. a third step of forming a grading on the removed and exposed lower cladding layer; and a fourth step of sequentially growing an outer waveguide layer and an upper cladding layer by liquid phase epitaxial growth.
Next, an inverted mesa stripe is formed in the [011] direction at the top of the groove, and a first current confinement layer and a second current confinement layer are sequentially grown by liquid phase epitaxial growth to fill the inverted mesa stripe. A method for manufacturing a semiconductor laser, comprising a fifth step.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62121182A JPS63287080A (en) | 1987-05-20 | 1987-05-20 | Manufacture of semiconductor laser |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62121182A JPS63287080A (en) | 1987-05-20 | 1987-05-20 | Manufacture of semiconductor laser |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63287080A true JPS63287080A (en) | 1988-11-24 |
Family
ID=14804881
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62121182A Pending JPS63287080A (en) | 1987-05-20 | 1987-05-20 | Manufacture of semiconductor laser |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63287080A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6167071A (en) * | 1997-09-25 | 2000-12-26 | Fuji Photo Film Co., Ltd. | Semiconductor laser |
-
1987
- 1987-05-20 JP JP62121182A patent/JPS63287080A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6167071A (en) * | 1997-09-25 | 2000-12-26 | Fuji Photo Film Co., Ltd. | Semiconductor laser |
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