JPS63287065A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63287065A JPS63287065A JP62121703A JP12170387A JPS63287065A JP S63287065 A JPS63287065 A JP S63287065A JP 62121703 A JP62121703 A JP 62121703A JP 12170387 A JP12170387 A JP 12170387A JP S63287065 A JPS63287065 A JP S63287065A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- forming
- ions
- substrate
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 150000002500 ions Chemical class 0.000 claims abstract description 6
- 238000005468 ion implantation Methods 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 18
- 238000009792 diffusion process Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 239000002356 single layer Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 150000002736 metal compounds Chemical class 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract description 2
- 238000010884 ion-beam technique Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特に多層ゲー
ト電極に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a multilayer gate electrode.
（従来の技術〕
従来の電気的にデータ変更可能なポリシリコン１層タイ
プの半導体不揮発性メモリーの多層ゲート電極の形成方
法のうち、ｍｌのゲート電極を拡散層に１より形成する
場合、第２図（ａ）〜（ｅ）に示すように、 シリコ
ン基板上に酸化膜を通して、イオンＰ（リン）をイオン
ビーム照ｎ＃シ、拡散層形成した・次に、前記電極上に
熱酸化により絶縁層として、酸化膜を形成し、更にポリ
シリコンを付むさせることにより、第２のゲート電極を
形成していた。(Prior Art) Among the conventional methods for forming a multilayer gate electrode of a polysilicon single layer type semiconductor non-volatile memory in which data can be electrically changed, when forming a ml gate electrode in a diffusion layer, the second method is used. As shown in Figures (a) to (e), a diffusion layer was formed by ion beam irradiation of ions P (phosphorous) through an oxide film on a silicon substrate.Next, an insulating layer was formed on the electrode by thermal oxidation. The second gate electrode was formed by forming an oxide film as a layer and then attaching polysilicon.
しかし、前述の従来の技術では、第１のゲート電極を拡
散層によって形成するため、前記第１のゲート電極と基
板間のジャンクシロン耐圧が低く前記１７ｒｌのゲート
電極と基板間に高電圧をかけると漏れｉｕ流が起き易い
という問題点がある。However, in the above-mentioned conventional technology, since the first gate electrode is formed by a diffusion layer, the breakdown voltage between the first gate electrode and the substrate is low, and a high voltage is applied between the 17rl gate electrode and the substrate. There is a problem that leakage is likely to occur.
そこで２本発明はこのような問題点を解決するもので、
その目的とするところは、拡散層にょうて形成する第１
のゲート電極と基板間のジャンクシ、ン耐圧を高＜Ｌ、
、 ＠れ電流を起き難くするゲート電極の形成方法を
提供するところにある。Therefore, the present invention aims to solve these problems.
The purpose of this is to form the first
The junction voltage between the gate electrode and the substrate is high <L,
The present invention provides a method for forming a gate electrode that makes it difficult to generate leakage current.
本発明の半導体装置の製造方法は、ポリシリコン１層タ
イプの半導体不揮発メモリにおいて（ａ）基板に同ｇｉ
または、 異種のイオンを用いて、２回以上のイオン注
入により拡散層を形成する工程と
（ｂ）前記拡散層上に絶縁膜を介してポリシリコンまた
は、金属あるいは、金屑化合物の電極を形成する工程か
らなることを特徴とする。The method for manufacturing a semiconductor device of the present invention includes (a) a semiconductor device having the same gi on a substrate in a polysilicon single layer type semiconductor nonvolatile memory
Alternatively, a step of forming a diffusion layer by ion implantation twice or more using different types of ions, and (b) forming an electrode of polysilicon, metal, or gold scrap compound on the diffusion layer with an insulating film interposed therebetween. It is characterized by the process of
以下１本発明について、実施例に基づき、詳細に説明す
る。第１図（ａ）〜（ｆ）は９本発明の実施例を工程順
に示したものである。The present invention will be described in detail below based on examples. FIGS. 1(a) to 1(f) show nine embodiments of the present invention in order of process.
まず、第１図（ａ）に、示すようにＰ型基板のウェハー
１上にレジスト層３により、パターニングされたシリコ
ン上に１０００°Ｃ１雰囲気Ｏ２中で約６００人の熱酸
化膜２を通して、エネルギー８０ｋｅＶ、 ドーズｌ
１ｌｔ４Ｘ１０’″ｃｍ−’で高濃度のイオ７Ａ＠のイ
オンビーム照射を行ない。First, as shown in FIG. 1(a), a resist layer 3 is placed on a P-type substrate wafer 1, and energy is applied through a thermal oxide film 2 of approximately 600 layers on patterned silicon at 1000° C. in an O2 atmosphere. 80keV, dose l
Ion beam irradiation with a high concentration of 7A@ was carried out at 1lt4×10'''cm-'.
ウェハー上に、第１回目のイオン注入を施す・次に、
第１図（ｂ）に示すように、 ｍ１図（ａ）と同様に
、前記酸化１１２を通して、エネルギー８０ ｋ ｅ
Ｖ、 Ｆ−ズｆｌｔ５Ｘ１０” ’ ｃｍ−’でイ氏
’ＣｚＫのイオンＰ（リン）のイオンビーム６照射し、
第２回目のイオン注入（２）を行なう参次いで、第１図
（Ｃ）に示すように、０．プラズマと硫酸により、レジ
スト層３を除去した後。Perform the first ion implantation onto the wafer.Next,
As shown in Figure 1(b), similar to Figure 1(a), through the oxidation 112, energy of 80 k e
Irradiated with 6 ion beams of Mr. Lee's CzK ion P (phosphorus) at V, F-sflt5X10''cm-',
After performing the second ion implantation (2), as shown in FIG. After removing the resist layer 3 by plasma and sulfuric acid.
窒素雰囲気中で１０００℃のアニールを３０分間行ない
、電極として形成された拡散層５．７を伸ばすψ
次に、第１図（ｄ）に示すように、ポリシリコンを厚さ
４０００人程度２堆積する。Annealing is performed at 1000°C for 30 minutes in a nitrogen atmosphere to extend the diffusion layer 5.7 formed as an electrode.Next, as shown in Figure 1(d), polysilicon is deposited to a thickness of about 4000°C. do.
そして、第１図（ｅ）に示すように、レジスト層８によ
り、バターニングを行ない、もうひとつの電極を形成し
、第１図＜ｒ＞の構造を得る。Then, as shown in FIG. 1(e), patterning is performed using the resist layer 8 to form another electrode, thereby obtaining the structure <r> in FIG.
以上、述べたように２本発明によれば、拡＠層によって
形成された第１のゲート電極と基板間のジャンクシ９ン
耐圧は、高くなり１ｇＡれ電流が。As described above, according to the present invention, the breakdown voltage of the junction between the first gate electrode formed by the expanded layer and the substrate is increased, and the leakage current is 1 gA.
起き難くなる。また、それにより、高電圧の動作が可能
となり１品質勿よび信頼性が向上するという効果がある
。It becomes difficult to wake up. Furthermore, this has the effect of enabling high voltage operation and improving quality and reliability.
１￥１図（ａ）〜＜ｒ＞は１本発明のゲート電極形成方
法の一実施例を示す主要断面図、 第２図（ａ）〜（ｅ
）は、従来のゲート電極形成方法を示す主要断面図であ
る。
１・・・シリコン基板
２・・・酸化膜
３．８・・・レジスト
４・・・へＳイオンビーム
５・・・高０度拡散層
６．９・・・１）（リン）イオンビーム７・・・低にｉ
度拡散層
１０・・・拡散層
以 上
ＣＣＬ） （ｂ）第１図1￥1 Figures (a) to <r> are main cross-sectional views showing one embodiment of the gate electrode forming method of the present invention, and Figures 2 (a) to (e
) is a main cross-sectional view showing a conventional gate electrode forming method. 1...Silicon substrate 2...Oxide film 3.8...S ion beam to resist 4...S ion beam 5...High 0 degree diffusion layer 6.9...1) (phosphorus) ion beam 7 ...low i
degree diffusion layer 10...diffusion layer or above CCL) (b) Figure 1
Claims (1)
半導体不揮発メモリーからなる半導体装置の製造方法に
おいて、 （ａ）基板に同種または、異種のイオンを用いて、２回
以上のイオン注入により拡散層を形成する工程と （ｂ）前記拡散層上に絶縁膜を介してポリシリコンまた
は、金属あるいは、金属化合物の電極を形成する工程か
らなることを特徴とする半導体装置の製造方法。[Claims] In a method for manufacturing a semiconductor device comprising a polysilicon single layer type semiconductor nonvolatile memory in which data can be electrically changed, (a) ions of the same type or different types are used on the substrate, A method for manufacturing a semiconductor device, comprising the steps of: forming a diffusion layer by ion implantation; and (b) forming an electrode of polysilicon, metal, or metal compound on the diffusion layer via an insulating film. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62121703A JPS63287065A (en) | 1987-05-19 | 1987-05-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62121703A JPS63287065A (en) | 1987-05-19 | 1987-05-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63287065A true JPS63287065A (en) | 1988-11-24 |
Family
ID=14817789
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62121703A Pending JPS63287065A (en) | 1987-05-19 | 1987-05-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63287065A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5156990A (en) * | 1986-07-23 | 1992-10-20 | Texas Instruments Incorporated | Floating-gate memory cell with tailored doping profile |
-
1987
- 1987-05-19 JP JP62121703A patent/JPS63287065A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5156990A (en) * | 1986-07-23 | 1992-10-20 | Texas Instruments Incorporated | Floating-gate memory cell with tailored doping profile |
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