JPS63282U - - Google Patents

Info

Publication number
JPS63282U
JPS63282U JP9264186U JP9264186U JPS63282U JP S63282 U JPS63282 U JP S63282U JP 9264186 U JP9264186 U JP 9264186U JP 9264186 U JP9264186 U JP 9264186U JP S63282 U JPS63282 U JP S63282U
Authority
JP
Japan
Prior art keywords
turning angle
radar
circuit
generates
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9264186U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9264186U priority Critical patent/JPS63282U/ja
Publication of JPS63282U publication Critical patent/JPS63282U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Radar Systems Or Details Thereof (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案による3次元サーチレーダ表
示装置の全体構成図、第2図は従来の表示装置の
全体構成図、第3図はレーダに動揺がない場合の
アンテナビームの様子とPPIスコープ上の表示
との関係図、第4図はレーダに動揺がある場合の
アンテナビームの様子と従来のPPIスコープ上
の表示との関係図、第5図はこの考案による表示
装置でのPPIスコープ上の表示を表わす図であ
る。 図において、1はレーダ情報を記憶するメモリ
、2は旋回角発生回路、3は書込みアドレス発生
回路、4は遅延時間発生回路、5は遅延回路、6
はOR回路、7はPPIである。なお、各図中同
一符号は同一または相当部分を示す。
Figure 1 is an overall configuration diagram of a three-dimensional search radar display device based on this invention, Figure 2 is an overall configuration diagram of a conventional display unit, and Figure 3 is an antenna beam diagram and a PPI scope when there is no movement in the radar. Figure 4 is a diagram showing the relationship between the state of the antenna beam when there is fluctuation in the radar and the display on a conventional PPI scope, and Figure 5 is a diagram showing the relationship between the display on the PPI scope and the display device of this invention. It is a figure showing a display. In the figure, 1 is a memory for storing radar information, 2 is a turning angle generation circuit, 3 is a write address generation circuit, 4 is a delay time generation circuit, 5 is a delay circuit, and 6
is an OR circuit, and 7 is a PPI. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 旋回角方向にスキヤンする3次元サーチレーダ
の表示装置において、目標からの反射波の有無を
1ビツトで表現したレーダ情報を各3次元座標(
距離、俯仰角、旋回角)ごとに記憶するメモリと
、レーダのスキヤンに応じて変化する旋回角を発
生する旋回角発生回路と、前記旋回角発生回路か
らの旋回角情報に、俯仰角情報を付加し、前記メ
モリへの書き込みアドレスを発生する書き込みア
ドレス発生回路と、表示装置外のレーダの動揺を
調べる装置からの出力を入力とし、そのレーダの
動揺の度合に応じて遅延時間を発生する遅延時間
発生回路と、前記旋回角発生回路からの旋回角に
対し、前記遅延時間発生回路から出力された時間
だけ遅延させて前記メモリの読出しアドレスを発
生する遅延回路と、前記メモリ出力の俯仰角方向
の論理和を出力するOR回路と、前記OR回路出
力を表示するPPI(Plan Positio
n Indicator)とを備えたことを特徴
とする表示装置。
In the display device of a three-dimensional search radar that scans in the direction of the turning angle, radar information that expresses the presence or absence of reflected waves from the target with one bit is displayed at each three-dimensional coordinate (
A turning angle generation circuit that generates a turning angle that changes according to the scan of the radar, and a turning angle information from the turning angle generation circuit that stores the turning angle information for each distance, elevation angle, turning angle). and a write address generation circuit that generates a write address to the memory, and a delay that takes as input an output from a device that checks the fluctuation of the radar outside the display device, and generates a delay time depending on the degree of fluctuation of the radar. a time generating circuit; a delay circuit that generates a read address for the memory by delaying the turning angle from the turning angle generating circuit by the time output from the delay time generating circuit; and an elevation angle direction of the memory output. an OR circuit that outputs the logical sum of , and a PPI (Plan Position
n Indicator).
JP9264186U 1986-06-18 1986-06-18 Pending JPS63282U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9264186U JPS63282U (en) 1986-06-18 1986-06-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9264186U JPS63282U (en) 1986-06-18 1986-06-18

Publications (1)

Publication Number Publication Date
JPS63282U true JPS63282U (en) 1988-01-05

Family

ID=30954523

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9264186U Pending JPS63282U (en) 1986-06-18 1986-06-18

Country Status (1)

Country Link
JP (1) JPS63282U (en)

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