JPS63276275A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63276275A JPS63276275A JP11190987A JP11190987A JPS63276275A JP S63276275 A JPS63276275 A JP S63276275A JP 11190987 A JP11190987 A JP 11190987A JP 11190987 A JP11190987 A JP 11190987A JP S63276275 A JPS63276275 A JP S63276275A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- source
- drain electrodes
- type
- ohmic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 abstract description 6
- 239000000956 alloy Substances 0.000 abstract description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract 1
- 229910052739 hydrogen Inorganic materials 0.000 abstract 1
- 239000001257 hydrogen Substances 0.000 abstract 1
- 238000007740 vapor deposition Methods 0.000 abstract 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 15
- 238000000034 method Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- MBGCACIOPCILDG-UHFFFAOYSA-N [Ni].[Ge].[Au] Chemical compound [Ni].[Ge].[Au] MBGCACIOPCILDG-UHFFFAOYSA-N 0.000 description 1
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 125000005842 heteroatom Chemical class 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にアルミニウムガリウム
ヒ素（Ａｊ’ｘ Ｇａ１−）（Ａｓ ） ／ガリウムヒ
素（ＧａＡｓ）のへテロ接合を有するトランジスタの構
造に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a structure of a transistor having a heterojunction of aluminum gallium arsenide (Aj'x Ga1-) (As)/gallium arsenide (GaAs). Regarding.
従来この種のトランジスタのソース・ドレイン電極とし
てのオーミック電極の形成は第３図に示し如く、不純物
がドープされたｎ型Ａ！ｘＧａｔ−ｘＡｓ（以下ｎ型Ａ
ｆｆＧａＡｓと記す）３Ａ上又はｎ型ＡｆＧａＡｓ３Ａ
上設けられなｎ＋型Ｇ ａ Ａ ｓ Ｎ４上に金ゲルマ
ニウムニッケル（ＡｎＧｅ−Ｎｉ ）６などを被着し、
熱処理によりＧａＡｓ基板１とＡｕＧｅとの合金層８を
形成してオーム性接触を得ることにより行われている。Conventionally, the ohmic electrodes used as the source and drain electrodes of this type of transistor were formed using n-type A! impurity-doped ohmic electrodes, as shown in FIG. xGat-xAs (hereinafter n-type A
ffGaAs) 3A or n-type AfGaAs3A
Gold germanium nickel (AnGe-Ni) 6 or the like is deposited on the n+ type GaAs N4 provided above,
This is done by forming an alloy layer 8 of the GaAs substrate 1 and AuGe through heat treatment to obtain ohmic contact.
上述した従来のオーミック電極の形成方法では、ｎ型Ａ
ｌＧａＡｓ３ＡとアンドープＧａＡｓ層２とのへテロ構
造を有するトランジスタの場合、電子のチャネル層は、
このヘテロ界面のいわゆる二次元電子ガス層（２ＤＥＧ
層）であるため、オーミック金属と半導体の合金層８が
この２ Ｄ Ｅ Ｇ層より深く存在しなければならず、
このため、合金層８を深くするためにオーミック金属の
厚さを通常のＧａＡｓ層 ＭＥＳＦＥＴの場合よりも
厚くする必要がある。In the conventional ohmic electrode formation method described above, n-type A
In the case of a transistor having a heterostructure of lGaAs3A and undoped GaAs layer 2, the electron channel layer is
The so-called two-dimensional electron gas layer (2DEG) at this hetero interface
layer), the alloy layer 8 of ohmic metal and semiconductor must exist deeper than this 2D E G layer,
Therefore, in order to deepen the alloy layer 8, it is necessary to make the ohmic metal thicker than in the case of a normal GaAs layer MESFET.
そのため後工程でのオーミック電極近傍でのゲート電極
形成予定領域でホトレジストを用いたパターニングの際
に、ウェハー表面の凹凸、すなわちオーミック金属膜と
ＧａＡｓ基板表面との高低差により、安定した微細パタ
ーンの形成ができないという欠点があった。Therefore, when patterning using photoresist in the area where the gate electrode is planned to be formed near the ohmic electrode in the subsequent process, a stable fine pattern can be formed due to the unevenness of the wafer surface, that is, the height difference between the ohmic metal film and the GaAs substrate surface. The drawback was that it was not possible.
これは、トランジスタの性能に大きな影響を及ぼすソー
スシリーズ抵抗（Ｒｓ）を小さくするために、ソース電
極に近づけてゲート電極を形成しようとする時に顕著で
あり、従ってあまりソース電極に近づけてゲート電極を
形成できないためＲ５が大きくなるという欠点もあった
。This is noticeable when trying to form the gate electrode close to the source electrode in order to reduce the source series resistance (Rs), which has a large effect on the performance of the transistor. There was also a drawback that R5 became large because it could not be formed.
本発明の目的は、ソース電極に近接したゲート電極を容
易に形成できしかもソースシリーズ抵抗の低減された半
導体装置を提供することにある。An object of the present invention is to provide a semiconductor device in which a gate electrode close to a source electrode can be easily formed and the source series resistance can be reduced.
本発明の半導体装置は、半絶縁性ＧａＡｓ基板上に形成
されたアンドープＧａＡｓ層と、該アンドープＧａＡｓ
層上に形成されたＡｌＧａＡｓ層と、前記アンドープＧ
ａＡｓ層とＡｌＧａＡｓ層にオーミック接続するソース
・ドレイン電極とを有する半導体装置であって、前記ソ
ース・ドレイン電極は、少くとも前記アンドープＧａＡ
ｓＪＩの表面に達する深さを有する溝に埋め込まれたオ
ーミック金属から構成されているものである。A semiconductor device of the present invention includes an undoped GaAs layer formed on a semi-insulating GaAs substrate, and an undoped GaAs layer formed on a semi-insulating GaAs substrate.
The AlGaAs layer formed on the layer and the undoped G
A semiconductor device having source/drain electrodes ohmically connected to an aAs layer and an AlGaAs layer, wherein the source/drain electrodes include at least the undoped GaA layer.
It consists of an ohmic metal embedded in a groove deep enough to reach the surface of the sJI.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の断面図である。以下第２図
（ａ）〜（ｃ）を併用してその製造方法と共に説明する
。FIG. 1 is a sectional view of an embodiment of the present invention. The manufacturing method will be explained below with reference to FIGS. 2(a) to 2(c).
まず第２図（ａ）に示すように半絶縁性のＧａＡｓ基板
１上にアンドープＧａＡｓ層を約１μｒｎ、さらにシリ
コン（Ｓｉ）をｎ型不純物として３Ｘ１０１８ｃｍ−３
ドーピングしたｎ＋型Ａ ｅ Ｏ０３Ｇ ａ Ｏ，？
Ａ ８層３を３００人、さらに同じくＳｉを３Ｘ１０”
ｃｍ−３ドーピングしたｎ生型Ｇａ Ａ ８層４を５０
０人を各々連続してＭＢＥ法により成長する。First, as shown in FIG. 2(a), an undoped GaAs layer of about 1 μrn is formed on a semi-insulating GaAs substrate 1, and silicon (Si) is added as an n-type impurity to a thickness of 3×1018 cm−3.
Doped n+ type A e O03G a O,?
A: 300 people with 8 layers 3, and 3×10” Si
50 cm-3 doped n-type Ga A 8 layers 4
0 people are each successively grown using the MBE method.
次に第２図（ｂ）に示すように、ソース・ドレイン電極
形成予定領域５を開口するパターニングをホトリソグラ
フィーにより行い、リン酸：過酸化水素水：水＝４：１
：９０のエッチャントを用いてｎ＋型ＧａＡｓ層４及び
ｎ）型Ａ ｊ’ ｏ５ Ｇ ａ （Ｔ、７Ａ ｓ 騙３
を約８００人エツチングし、このエツチング呈と同じ厚
さになるようにＡ ｕ Ｇ ｅを６００人、Ｎｉを２０
０人真空蒸着法にて被着し、ＡｕＧｅ−Ｎｉ層６を形成
する。次でソース・ドレイン電極形成予定領域５以外の
Ａ ｕ Ｇ ｅ −Ｎ ｉ Ｎをリフトオフ法により除
去する。Next, as shown in FIG. 2(b), patterning is performed by photolithography to open the regions 5 where source/drain electrodes are to be formed. Phosphoric acid:hydrogen peroxide:water=4:1
:90 etchant to form n+ type GaAs layer 4 and n) type A j' o5 Ga (T,7A s 3
Approximately 800 layers of etching were performed, and 600 layers of AuG and 20 layers of Ni were added to the same thickness as the etching.
The AuGe--Ni layer 6 is formed by a zero-person vacuum evaporation method. Next, the A u G e -N i N other than the region 5 where the source/drain electrodes are to be formed is removed by a lift-off method.
次に第２図（ｃ）に示すように、水素雰囲気にて４５０
°Ｃで２分間熱処理を行い、合金層８を形成することに
よりオーミックなソース・ドレイン電極１０．１１が形
成される。この時、ソース・ドレイン間はほぼソース・
ドレイン電極部を含めて平坦となる。Next, as shown in Figure 2(c), 450
Heat treatment is performed at .degree. C. for 2 minutes to form alloy layer 8, thereby forming ohmic source/drain electrodes 10.11. At this time, the distance between the source and drain is almost source/drain.
It becomes flat including the drain electrode part.
次に第１図に示すように、ｎ＋型ＧａＡｓ層４に開口部
を設けたのちゲート電極１２を形成する。この時、ソー
ス・ドレイン電極１０．１１を含む表面は平坦化されて
いるめ微細なパターニングはきわめて容易に行うことが
できる。しかもソース電極１０に近接してゲート電極１
２を形成できるため、チャネル抵抗が小さくなり、また
２Ｄ、ＥＧｌに確実にオーミックコンタクトがとれるた
めに安定したコンタクト抵抗が得られ、従ってＲ’ｓの
低い良好な性能を有するトランジスタができる。 −
〔発明の効果〕
以上説明したように本発明は、ソース・ドレイン電極を
・、少なくともアンドープ・Ｇ ａ Ａ 、ｓ屑の表面
に達する深さを有する溝に埋め込まれたオーミック金属
から構成することにより、確実にしがち低接触抵抗にて
チャネル層にオーミックなソース・ドレイン電極が形成
できる。また、ゲート電極形成予定領域近傍が−きわめ
て平坦となっているために、ソース電極に近接したゲー
ト電極を容易に形成できる効果がある。この為チャネル
抵抗も小さくでき、従ってＲ５が小さく、雑音特性や利
得のすぐれた良好な半導体装置が得られる。Next, as shown in FIG. 1, an opening is provided in the n+ type GaAs layer 4, and then a gate electrode 12 is formed. At this time, since the surface including the source/drain electrodes 10.11 is flattened, fine patterning can be performed extremely easily. Moreover, the gate electrode 1 is located close to the source electrode 10.
Since 2D and EG1 can be formed, the channel resistance becomes small, and since ohmic contact can be made reliably with 2D and EG1, stable contact resistance can be obtained. Therefore, a transistor with low R's and good performance can be obtained. - [Effects of the Invention] As explained above, the present invention provides that the source/drain electrodes are made of an ohmic metal embedded in a groove having a depth that reaches at least the surface of undoped Ga, S scraps. As a result, ohmic source/drain electrodes can be formed in the channel layer with low contact resistance. Furthermore, since the vicinity of the region where the gate electrode is to be formed is extremely flat, there is an effect that the gate electrode can be easily formed close to the source electrode. For this reason, the channel resistance can also be made small, so that a good semiconductor device with small R5 and excellent noise characteristics and gain can be obtained.
第１図は本発明の一実施例の断面図、第２図（ａ ）〜
（ｃ）は本発明の一実施例の製造方法を説明するための
工程順に示した半導体チップの断面図、第３図は従来の
半導体装置の断面図である。
１・・・ＧａＡｓ基板、２・・・アンドープＧ ａ Ａ
ｓ層、３ ＝−ｎ＋型Ａ ｅ Ｏ，３Ｇ ａ ｏ、７
Ａ ｓ Ｒ１４−ｎ＋型（Ｊｒ ａ Ａ ｓ層、５・・
・オーミック電極形成予定領域、６・・・ＡｕＧｅ−Ｎ
ｉ層、８・・・合金層、９・・・二次元電子ガス層（２
ＤＥＧ層）、１０・・・ソース電極、１１・・・トレイ
ン電極、１２・・・ゲート電極。Fig. 1 is a sectional view of one embodiment of the present invention, Fig. 2(a) -
(c) is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view of a conventional semiconductor device. 1...GaAs substrate, 2...Undoped GaA
s layer, 3 = -n+ type A e O, 3G a o, 7
As R14-n+ type (Jra As layer, 5...
- Ohmic electrode formation area, 6...AuGe-N
i layer, 8... alloy layer, 9... two-dimensional electron gas layer (2
DEG layer), 10... source electrode, 11... train electrode, 12... gate electrode.
Claims (1)
ｓ層と、該アンドープＧａＡｓ層上に形成されたＡｌＧ
ａＡｓ層と、前記アンドープＧａＡｓ層とＡｌＧａＡｓ
層にオーミック接続するソース・ドレイン電極とを有す
る半導体装置において、前記ソース・ドレイン電極は、
少くとも前記アンドープＧａＡｓ層の表面に達する深さ
を有する溝に埋め込まれたオーミック金属から構成され
ていることを特徴とする半導体装置。Undoped GaA formed on a semi-insulating GaAs substrate
s layer and AlG formed on the undoped GaAs layer.
aAs layer, the undoped GaAs layer and AlGaAs
In a semiconductor device having source/drain electrodes that are ohmically connected to a layer, the source/drain electrodes are
A semiconductor device comprising an ohmic metal embedded in a groove having a depth reaching at least the surface of the undoped GaAs layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11190987A JPS63276275A (en) | 1987-05-08 | 1987-05-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11190987A JPS63276275A (en) | 1987-05-08 | 1987-05-08 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63276275A true JPS63276275A (en) | 1988-11-14 |
Family
ID=14573160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11190987A Pending JPS63276275A (en) | 1987-05-08 | 1987-05-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63276275A (en) |
-
1987
- 1987-05-08 JP JP11190987A patent/JPS63276275A/en active Pending
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