JPS63275219A - Multiplication circuit - Google Patents

Abstract

PURPOSE:To prevent a duty cycle from being changed by an input frequency by comparing the mean voltage of an output pulse with a reference voltage, and controlling the integrated quantity of an integration circuit based on a voltage controlled current source and a capacitor according to said comparative output. CONSTITUTION:A waveform B is obtained from an input signal A through the use of a first voltage controlled current source 1, a first capacitor 2 and a first voltage control switch 3, and simultaneously, the waveform C is obtained from the use of a NOT circuit 4, a second voltage controlled current source 5, a second capacitor 6 and a second voltage control switch 7. The waveform B and the waveform C generate the output waveform D through the use of a NOT circuit 8, and at the same time, the output waveform D is converted into the mean voltage by a smoothing circuit 9. Then, an operational amplifier 10 controls the control terminals of the first voltage controlled current source 1 and the second voltage controlled current source 5 so that the output voltage of the smoothing circuit 9 and the voltage of a reference voltage source 11 are equal. Thus, even if the frequency of the input signal fluctuates, the duty cycle of a multiplication output is constant.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、逓倍回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a multiplier circuit.

〔従来の技術〕[Conventional technology]

従来、逓倍回路には、排他的論理和回路（以下ＥＸ−Ｏ
Ｒという）と遅延回路とを使用した第３図に示す回路が
使われている。第４図は第３図に示す従来例のタイミン
グチャートである。入力端子１０３に入力信号Ｊを入力
すると、遅延回路１０１により、信号ＫがＥＸ−ＯＲ１
０２に入力される。ＥＸ−ＯＲ１０２により入力信号Ｊ
と信号にとの排他的論理和を取ることにより、出力端子
１０４に出力波形りが得られ、逓倍動作を行う。Conventionally, an exclusive OR circuit (hereinafter EX-O) is used as a multiplier circuit.
A circuit shown in FIG. 3 using a delay circuit (referred to as R) and a delay circuit is used. FIG. 4 is a timing chart of the conventional example shown in FIG. When input signal J is input to input terminal 103, signal K is output to EX-OR1 by delay circuit 101.
02 is input. Input signal J by EX-OR102
By taking the exclusive OR of the signal and the signal, an output waveform is obtained at the output terminal 104, and a multiplication operation is performed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の逓倍回路は、ある決まった遅延時間を持
った遅延回路により入力信号を遅らせ、入力信号と排他
的論理和をとるため、入力信号の周波数により逓倍出力
のデユーティサイクルが一定でないという欠点がある。The conventional multiplier circuit described above delays the input signal using a delay circuit with a fixed delay time and performs an exclusive OR with the input signal, so the duty cycle of the multiplied output is not constant depending on the frequency of the input signal. There are drawbacks.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の逓倍回路は、第一の電圧制御電流源の出力に第
一のコンデンサの一端を接続し、この第一のコンデンサ
の多端を接地し、この第一のコンデンサの両端に餉−の
電圧制御スイ・ｙチの接点を接続し、第二の電圧制御電
流源の出力に第二のコンデンサの一端を接続し、この第
二のコンデンサの他端を接地し、この第二のコンデンサ
の両端に第二の電圧制御スイッチの接点を接続し、入力
信号は前記第一の電圧制御スイッチの制御端子および否
定回路の入力に接続し、この否定回路の出力は前記第二
の電圧制御スイッチの制御端子に接続し、前記第一の電
圧制御電流源の出力および前記第二の電圧制御電流源の
出力は論理回路に入力し、この論理回路の出力は平滑回
路に入力し、この平滑回路の出力は演算増幅器の反転入
力に接続し、この演算増幅器の非反転入力は基準電圧源
に接続し、前記演算増幅器の出力は前記第一の電圧制御
電流源の制御端子および前記第二の電圧制御電流源の制
御端子に接続し、前記論理回路の出力を逓倍出力とする
構成からなる。The multiplier circuit of the present invention connects one end of a first capacitor to the output of a first voltage-controlled current source, grounds the other end of this first capacitor, and applies a voltage across both ends of this first capacitor. Connect the contacts of the control switch Y, connect one end of the second capacitor to the output of the second voltage controlled current source, ground the other end of this second capacitor, and connect both ends of this second capacitor. A contact of a second voltage controlled switch is connected to the input signal, and an input signal is connected to a control terminal of the first voltage controlled switch and an input of an inverting circuit, and the output of this inverting circuit is connected to the control terminal of the second voltage controlled switch. terminal, the output of the first voltage-controlled current source and the output of the second voltage-controlled current source are input to a logic circuit, the output of this logic circuit is input to a smoothing circuit, and the output of this smoothing circuit is is connected to the inverting input of an operational amplifier, the non-inverting input of this operational amplifier is connected to a reference voltage source, and the output of the operational amplifier is connected to the control terminal of the first voltage-controlled current source and to the second voltage-controlled current source. The output of the logic circuit is connected to the control terminal of the power source, and the output of the logic circuit is multiplied.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は発明の一実施例を示すブロック図、第２図は第
１図に示す実施例のタイミングチャートである。FIG. 1 is a block diagram showing one embodiment of the invention, and FIG. 2 is a timing chart of the embodiment shown in FIG.

入力信号Ａは、第一の電圧制御電流源１と、第一のコン
デンサ２と、ＮＰＮトランジスタによる第一の電圧制御
スイッチ３とにより波形Ｂを得る。同時に入力信号Ａは
、否定回路４と、第二の電圧制御電流源５と、第二のコ
ンデンサ６と、ＮＰＮ）ランジスタによる第二の電圧制
御スイッチ７とにより、波形Ｃを得る。波形Ｂと波形Ｃ
とは否定和回路８により、出力波形りを得る。第２図で
、Ｅは否定和回路８のしきい電圧を示す。出力波形りは
、平滑回路９により平均電圧に変換される。演算増幅器
１０は、平滑回路９の出力電圧と基準電圧源１１の電圧
とが同じになるように、第一の電圧制御電流源１および
第二の電圧制御電流源５の制御端子を制御する。出力デ
ユーティ−サイクルは次式で示される。An input signal A obtains a waveform B by a first voltage-controlled current source 1, a first capacitor 2, and a first voltage-controlled switch 3 formed by an NPN transistor. At the same time, the input signal A obtains a waveform C by the inverter 4, the second voltage-controlled current source 5, the second capacitor 6, and the second voltage-controlled switch 7 which is an NPN) transistor. Waveform B and waveform C
The output waveform is obtained by the negative sum circuit 8. In FIG. 2, E indicates the threshold voltage of the negative sum circuit 8. The output waveform is converted into an average voltage by a smoothing circuit 9. The operational amplifier 10 controls the control terminals of the first voltage-controlled current source 1 and the second voltage-controlled current source 5 so that the output voltage of the smoothing circuit 9 and the voltage of the reference voltage source 11 become the same. The output duty cycle is given by the following equation.

出力デユーティ−サイクル・ なお、否定和回路８のかわりに論理和回路または排他的
論理和回路を用いてもよい。この場合、出力波形は第２
図に示す出力波形りを反転した波形になる。Output Duty Cycle Note that the NOR circuit 8 may be replaced with an OR circuit or an exclusive OR circuit. In this case, the output waveform is
The output waveform shown in the figure is inverted.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、出力パルスの平均電圧と
基準電圧とを比較し、その比較出力で電圧制御電流源と
コンデンサとによる積分回路の積分量を制御するため、
入力周波数によりデユーティ−サイクルが変らない効果
がある。As explained above, the present invention compares the average voltage of an output pulse with a reference voltage, and uses the comparison output to control the amount of integration of an integrating circuit made up of a voltage-controlled current source and a capacitor.
This has the effect that the duty cycle does not change depending on the input frequency.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を示すブロック図、第２図は
第１図に示す実施例のタイミングチャート、第３図は従
来の逓倍回路の一例のブロック図、第４図は第３図に示
す従来例のタイミングチャートである。FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart of the embodiment shown in FIG. 1, FIG. 3 is a block diagram of an example of a conventional multiplier circuit, and FIG. 3 is a timing chart of the conventional example shown in the figure.

Claims (4)

【特許請求の範囲】[Claims] （１）第一の電圧制御電流源の出力に第一のコンデンサ
の一端を接続し、この第一のコンデンサの多端を接地し
、この第一のコンデンサの両端に第一の電圧制御スイッ
チの接点を接続し、第二の電圧制御電流源の出力に第二
のコンデンサの一端を接続し、この第二のコンデンサの
他端を接地し、この第二のコンデンサの両端に第二の電
圧制御スイッチの接点を接続し、入力信号は前記第一の
電圧制御スイッチの制御端子および否定回路の入力に接
続し、この否定回路の出力は前記第二の電圧制御スイッ
チの制御端子に接続し、前記第一の電圧制御電流源の出
力および前記第二の電圧制御電流源の出力は論理回路に
入力し、この論理回路の出力は平滑回路に入力し、この
平滑回路の出力は演算増幅器の反転入力に接続し、この
演算増幅器の非反転入力は基準電圧源に接続し、前記演
算増幅器の出力は前記第一の電圧制御電流源の制御端子
および前記第二の電圧制御電流源の制御端子に接続し、
前記論理回路の出力を逓倍出力とすることを特徴とする
逓倍回路。(1) Connect one end of the first capacitor to the output of the first voltage-controlled current source, ground the other end of this first capacitor, and connect the contacts of the first voltage-controlled switch to both ends of this first capacitor. connect one end of a second capacitor to the output of the second voltage-controlled current source, ground the other end of this second capacitor, and connect a second voltage-controlled switch across this second capacitor. the input signal is connected to the control terminal of the first voltage controlled switch and the input of the inverting circuit, the output of this inverting circuit is connected to the control terminal of the second voltage controlled switch, and the input signal is connected to the control terminal of the first voltage controlled switch and the input of the inverting circuit. The output of the first voltage-controlled current source and the output of the second voltage-controlled current source are input to a logic circuit, the output of this logic circuit is input to a smoothing circuit, and the output of this smoothing circuit is input to the inverting input of an operational amplifier. a non-inverting input of the operational amplifier is connected to a reference voltage source, and an output of the operational amplifier is connected to a control terminal of the first voltage-controlled current source and a control terminal of the second voltage-controlled current source. ,
A multiplier circuit characterized in that the output of the logic circuit is a multiplier output. （２）論理回路を否定和回路で構成した特許請求の範囲
第１項記載の逓倍回路。(2) The multiplier circuit according to claim 1, wherein the logic circuit is constituted by a negative sum circuit. （３）論理回路を論理和回路で構成した特許請求の範囲
第１項記載の逓倍回路。(3) The multiplier circuit according to claim 1, wherein the logic circuit is constituted by an OR circuit. （４）論理回路を排他的論理和回路で構成した特許請求
の範囲第１項記載の逓倍回路。(4) The multiplier circuit according to claim 1, wherein the logic circuit is an exclusive OR circuit.