JPS63274237A - Test system - Google Patents
Test systemInfo
- Publication number
- JPS63274237A JPS63274237A JP10861787A JP10861787A JPS63274237A JP S63274237 A JPS63274237 A JP S63274237A JP 10861787 A JP10861787 A JP 10861787A JP 10861787 A JP10861787 A JP 10861787A JP S63274237 A JPS63274237 A JP S63274237A
- Authority
- JP
- Japan
- Prior art keywords
- test
- test pattern
- circuit
- section
- relay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 75
- 230000005540 biological transmission Effects 0.000 claims abstract description 22
- 238000001514 detection method Methods 0.000 claims abstract description 18
- 238000003780 insertion Methods 0.000 claims abstract description 5
- 230000037431 insertion Effects 0.000 claims abstract description 5
- 238000010998 test method Methods 0.000 claims description 10
- 230000001360 synchronised effect Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
Landscapes
- Detection And Prevention Of Errors In Transmission (AREA)
- Dc Digital Transmission (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は多段中継伝送において、各中継区間に割りふっ
たアドレスと当該区間のエラー数により各中継区間の伝
送品質を判冗する自動試験方式に関する。Detailed Description of the Invention (Field of Industrial Application) The present invention is an automatic test method for determining the transmission quality of each relay section based on the address assigned to each relay section and the number of errors in that section in multi-stage relay transmission. Regarding.
（従来の技術）
従来の多段中継伝送における試験方式は各中継装置毎に
固有のアドレスを割シふり、試験器から試験設定フラグ
とアドレス全送出し、該当する中継装置でエラーの試験
全行なった後、試験結果を折返し試験データを得ていた
。(Prior art) The conventional test method for multi-stage relay transmission was to allocate a unique address to each relay device, send out all test setting flags and addresses from the tester, and perform all error tests on the corresponding relay device. After that, the test results were returned and test data was obtained.
（発明が解決しようとする問題点）
このような従来の試験方式では障害区間を判定するため
にｎ段中継の場合には試験器から最大ｎ回アドレスを変
えて試験を実行しなければならない場合があシ、試験に
手間がかかるという欠点があった。(Problem to be Solved by the Invention) In such a conventional test method, in the case of an n-stage relay, in order to determine a fault section, the test must be performed by changing the address from the tester up to n times. However, the drawback was that the test was time-consuming.
本発明の目的は上記欠点を解決するもので。The object of the present invention is to overcome the above-mentioned drawbacks.
１回の試験の実行でｎ段の中継区間を試験することがで
きる試験方式を提供することにある。An object of the present invention is to provide a test method capable of testing n-stage relay sections by executing the test once.
（問題点′！！ｌ−解決するための手段）前記目的を達
成するために本発明による試験方式は多段中継伝送路に
試験パターンを送出し。(Problem '!!l - Means for Solving) In order to achieve the above object, the test method according to the present invention sends a test pattern to a multi-stage relay transmission line.
エラー数を検出することにより各中継区間の伝送品質全
判定する試験方式において、各中継装置に、試験器また
は前段の中継装置からの試験パターン列を含む情報を受
信し、同期化する第１同期回路と、前記試験パターン列
よシェラ−ビット数を計数する第１エラー検出回路と、
第１試験パターン発生回路と、前記第１試験パターン発
生回路が出力する試験パターン列、当該中継区間のアド
レスおよび前記エラー検出回路からのエラービット数を
所定のデータ部に挿入し、後段の伝送路に送出するデー
タ挿入回路とを設け、伝送路に試験パターン列を送出す
る第２試験パターン発生回路と、伝送路からの試験パタ
ーン列を含む情報を受信し、同期化する第２同期回路と
、前記試験パターン列よりエラービット数を計数する第
２エラー検出回路と、前記第２エラー検出回路からの当
該区間アドレスおよびエラービット数を受けるとともに
伝送路からの試験結果データ部の結果を受けて、各中継
区間の伝送品質を判定する判定回路とからなる試験器を
設けて構成しである。In a test method that determines the overall transmission quality of each relay section by detecting the number of errors, each relay device receives information including a test pattern sequence from a tester or a previous relay device, and synchronizes it. a first error detection circuit that counts the number of Scherrer bits based on the test pattern sequence;
A first test pattern generation circuit, a test pattern sequence outputted by the first test pattern generation circuit, the address of the relay section, and the number of error bits from the error detection circuit are inserted into a predetermined data section, and a second test pattern generation circuit that sends out a test pattern sequence to the transmission line; and a second synchronization circuit that receives and synchronizes information including the test pattern sequence from the transmission line; a second error detection circuit that counts the number of error bits from the test pattern sequence; and receiving the section address and the number of error bits from the second error detection circuit and receiving the result of the test result data section from the transmission line; The system includes a tester including a determination circuit that determines the transmission quality of each relay section.
（実施例） 以下１図面を参照して本発明金さらに詳しく説明する。(Example) The present invention will be described in more detail below with reference to one drawing.
第１図および第２図は本発明による試験方式の一実施例
を示す因で、第１図は試験器の構成を、第２図は中継装
置の構成をそれぞれ示している。1 and 2 show an embodiment of the test method according to the present invention; FIG. 1 shows the configuration of a tester, and FIG. 2 shows the configuration of a relay device.
第３図は本発明にかかる試験パターンの一例を示す図で
ある。０ｔ）Ｔ １ 、 ＯＵＴ ２は送信出力、ＩＮ
ｌ、ＩＮ２は受信入力をそれぞれ示す。試験器は試験パ
ターン発生回路、同期回路２％受信データから誤シを検
出し、エラービット数を計数するエラー検出回路３．お
よび試験結果データ部のアドレスとエラービット数から
各中継区間の伝送品質を判定する判定回路４とから構成
されている。各中継装置は同期回路５．試験パターン発
生回路６．エラー検出回路７．試験中は試験パターン発
生回路からの試験データを試験終了後各中継区間のアド
レスとともにエラー検出回路からのエラービット数を試
験結果データとして送出するデータ挿入回路８を含んで
いる。FIG. 3 is a diagram showing an example of a test pattern according to the present invention. 0t) T 1 , OUT 2 is the transmission output, IN
1 and IN2 indicate reception inputs, respectively. The tester includes a test pattern generation circuit, a synchronization circuit, and an error detection circuit that detects errors from 2% received data and counts the number of error bits.3. and a determination circuit 4 that determines the transmission quality of each relay section from the address of the test result data section and the number of error bits. Each relay device has a synchronous circuit 5. Test pattern generation circuit6. Error detection circuit 7. During a test, a data insertion circuit 8 is included which sends test data from a test pattern generation circuit and, after the test is completed, the address of each relay section and the number of error bits from an error detection circuit as test result data.
次に、この実施例の動作について説明する。Next, the operation of this embodiment will be explained.
試験パターン発生回路ｌより送出された試験パターン列
は中継装置の同期回路５で同期がとられる。この同期回
路のタイミングでエラー検出回路７において試験パター
ン列の試験データ部９の誤シが検出され、エラービット
数が計数さ１、る。データ挿入回路８は試験パターン発
生回路６で発生した試験パターン列を試験データ部９に
、当該中継区間のアドレスとエラー検出回路７からのエ
ラービット数を試験結果データ部ｌＯにそれぞれ挿入す
る。The test pattern sequence sent out from the test pattern generation circuit 1 is synchronized by the synchronization circuit 5 of the relay device. At the timing of this synchronization circuit, the error detection circuit 7 detects an error in the test data portion 9 of the test pattern sequence, and the number of error bits is counted. The data insertion circuit 8 inserts the test pattern sequence generated by the test pattern generation circuit 6 into the test data section 9, and inserts the address of the relay section and the number of error bits from the error detection circuit 7 into the test result data section IO.
次段以降の中継装置でも同様の動作をする。Similar operations are performed in the relay devices at the next and subsequent stages.
最後に試験器の受信部では中継装置と同様に同期回路２
で同期をとシ、エラー検出回路３で試験パターン列の試
験データ部９の誤シを検出し、エラービット数を計数す
る。Finally, in the receiving section of the tester, the synchronous circuit 2 is
When synchronization is established, the error detection circuit 3 detects an error in the test data section 9 of the test pattern sequence, and counts the number of error bits.
判定回路４Ｆｉ試験パタ一ン列の試験結果データ部ｌＯ
より各中継区間のアドレスとともにエラービット数ｔ−
読み取シ、各中継区間の伝送品質を判定する。Judgment circuit 4Fi test pattern row test result data section lO
Therefore, along with the address of each relay section, the number of error bits t-
Then, the transmission quality of each relay section is determined.
（発明の効果）
以上、説明したように本発明は試験データ列の試験結果
データ部にアドレスならびにエラービット数を挿入し、
試験器でこれｔａみ取るように構成されているので、各
中継区間の伝送品質ｉ１回の試験の実行で判定できると
いう効果がある。(Effects of the Invention) As explained above, the present invention inserts an address and the number of error bits into the test result data part of the test data string,
Since the tester is configured to measure this, there is an effect that the transmission quality i of each relay section can be determined by performing one test.
第１図および第２図は本発明による試験方式の一実施例
を示すブロック図で、第１図は試験器の構成を、第２図
は中継装置側の構成をそれぞれ示している。第３図は本
発明にかかる試験パターンの一例を示す図である。
ｌ・・・試験パターン発生回路
２・・・同期回路 ３・・・エラー検出回路４・・・
判定回路 ５・・・同期回路６・・・試験パターン発
生回路
７・・・エラー検出回路
８・・・データ挿入回路 ９・・・試験データ部１０
・・・試験結果データ部
特許出願人 日本電気株式会社
代理人 弁理士 井 ノ ロ 壽第１コ
２２図
す
２３図FIGS. 1 and 2 are block diagrams showing an embodiment of the test method according to the present invention. FIG. 1 shows the configuration of the tester, and FIG. 2 shows the configuration of the relay device. FIG. 3 is a diagram showing an example of a test pattern according to the present invention. l...Test pattern generation circuit 2...Synchronization circuit 3...Error detection circuit 4...
Judgment circuit 5...Synchronization circuit 6...Test pattern generation circuit 7...Error detection circuit 8...Data insertion circuit 9...Test data section 10
...Test Results Data Department Patent Applicant NEC Co., Ltd. Agent Patent Attorney Hisashi Inoro Figure 1 Figures 22 and 23
Claims (1)
出することにより各中継区間の伝送品質を判定する試験
方式において、各中継装置に試験器または前段の中継装
置からの試験パターン列を含む情報を受信し、同期化す
る第１同期回路と、前記試験パターン列よりエラービッ
ト数を計数する第１エラー検出回路と、第１試験パター
ン発生回路と、前記第１試験パターン発生回路が出力す
る試験パターン列、当該中継区間のアドレスおよび前記
エラー検出回路からのエラービット数を所定のデータ部
に挿入し、後段の伝送路に送出するデータ挿入回路とを
設け、伝送路に試験パターン列を送出する第２試験パタ
ーン発生回路と、伝送路からの試験パターン列を含む情
報を受信し、同期化する第２同期回路と、前記試験パタ
ーン列よりエラービット数を計数する第２エラー検出回
路と、前記第２エラー検出回路からの当該区間アドレス
およびエラービット数を受けるとともに伝送路からの試
験結果データ部の結果を受けて、各中継区間の伝送品質
を判定する判定回路とからなる試験器を設けたことを特
徴とする試験方式。In a test method that sends a test pattern to a multi-stage relay transmission line and determines the transmission quality of each relay section by detecting the number of errors, each relay device receives information including a test pattern sequence from a tester or a previous relay device. a first synchronization circuit that receives and synchronizes the test pattern, a first error detection circuit that counts the number of error bits from the test pattern sequence, a first test pattern generation circuit, and a test output from the first test pattern generation circuit. A data insertion circuit that inserts the pattern string, the address of the relay section, and the number of error bits from the error detection circuit into a predetermined data section and sends it to a subsequent transmission path is provided, and the test pattern string is sent to the transmission path. a second test pattern generation circuit; a second synchronization circuit that receives and synchronizes information including a test pattern sequence from a transmission path; a second error detection circuit that counts the number of error bits from the test pattern sequence; A tester is provided, which includes a judgment circuit that receives the section address and the number of error bits from the second error detection circuit and receives the results of the test result data section from the transmission line, and judges the transmission quality of each relay section. This test method is characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10861787A JPS63274237A (en) | 1987-05-01 | 1987-05-01 | Test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10861787A JPS63274237A (en) | 1987-05-01 | 1987-05-01 | Test system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63274237A true JPS63274237A (en) | 1988-11-11 |
Family
ID=14489336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10861787A Pending JPS63274237A (en) | 1987-05-01 | 1987-05-01 | Test system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63274237A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0447834A (en) * | 1990-06-15 | 1992-02-18 | Nec Corp | Optical repeater |
| US6973603B2 (en) * | 2002-06-28 | 2005-12-06 | Intel Corporation | Method and apparatus for optimizing timing for a multi-drop bus |
-
1987
- 1987-05-01 JP JP10861787A patent/JPS63274237A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0447834A (en) * | 1990-06-15 | 1992-02-18 | Nec Corp | Optical repeater |
| US6973603B2 (en) * | 2002-06-28 | 2005-12-06 | Intel Corporation | Method and apparatus for optimizing timing for a multi-drop bus |
| US7117401B2 (en) | 2002-06-28 | 2006-10-03 | Intel Corporation | Method and apparatus for optimizing timing for a multi-drop bus |
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