JPS63272062A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPS63272062A
JPS63272062A JP62107497A JP10749787A JPS63272062A JP S63272062 A JPS63272062 A JP S63272062A JP 62107497 A JP62107497 A JP 62107497A JP 10749787 A JP10749787 A JP 10749787A JP S63272062 A JPS63272062 A JP S63272062A
Authority
JP
Japan
Prior art keywords
leads
lead
die pad
inner leads
internal leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62107497A
Other languages
Japanese (ja)
Other versions
JPH0824159B2 (en
Inventor
Minao Isayama
諌山　皆夫
Michiaki Kita
北　道明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP62107497A priority Critical patent/JPH0824159B2/en
Publication of JPS63272062A publication Critical patent/JPS63272062A/en
Publication of JPH0824159B2 publication Critical patent/JPH0824159B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To avoid defects such as a short-circuit between inner leads or bonding wires and obtain a highly reliable semiconductor device by a method wherein some of the inner leads have smaller lead widths than the other inner leads and are extended closer to a die pad and have widened parts at their tips. CONSTITUTION:A die pad 2 on which a semiconductor element is mounted, a plurality of inner leads 4 whose tips are extended close to the die pad 2, outer leads extended outward from the inner leads 4 and tie-bars supporting the inner leads 4 and the outer leads are provided. In a lead frame like this, some 4b of the inner leads 4 have smaller lead widths t2 than the other inner leads 4a and are extended closer to the die pad 2 and have widened parts (f) at their tips. The inner leads 4b with the widened parts (f) at their tips and the inner leads 4a without the widened parts are, for instance, arranged alternately.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は、半導体装置用のリードフレームに係り、特に
半導体ｌ！積回路（ＩＣ）や大規模集積回路（ＬＳＩ）
等の組立に用いるリードフレームに間する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a lead frame for a semiconductor device, and particularly to a lead frame for a semiconductor device. Integrated circuit (IC) and large-scale integrated circuit (LSI)
It is attached to a lead frame used for the assembly of etc.

〔従来の技術およびその問題点〕[Conventional technology and its problems]

ＩＣ，ＬＳＩ等の半導体装置は、第２図に示すように、
リードフレーム１のダイパッド２に半導体素子３を固着
し、この半導体素子のポンディングパッドとリードフレ
ームの内部リード４とを金線あるいはアルミ線等のボン
ディングワイヤ５によって結線し、更にこれらを樹脂６
で封止することにより製造されている。As shown in Figure 2, semiconductor devices such as IC and LSI are
A semiconductor element 3 is fixed to a die pad 2 of a lead frame 1, and a bonding pad of this semiconductor element and an internal lead 4 of the lead frame are connected with a bonding wire 5 such as a gold wire or an aluminum wire.
It is manufactured by sealing with.

このように、半導体素子の支持および電気的接続のため
に用いられるリードフレームは、通常、第３図（ａ）お
よび第３図（ｂ）に１例を示す如く、半導体素子を搭載
するためのダイパッド２と、先端が該ダイパッドをとり
囲むように延在せしめられた２０本の内部リード４と、
該内部リードとほぼ直交する方向に延びこれら内部リー
ドを一体的に支持するタイバー１１と、該タイバーの外
側に前記各内部リードに接続するように配設せしめられ
た外部リード１２とダイパッド２を支持するサポートパ
ー１３から構成されている。As described above, lead frames used for supporting and electrically connecting semiconductor elements are usually used for mounting semiconductor elements, as shown in FIGS. 3(a) and 3(b). a die pad 2; 20 internal leads 4 whose tips extend so as to surround the die pad;
Tie bars 11 extend in a direction substantially perpendicular to the internal leads and integrally support these internal leads, and external leads 12 and die pads 2 are supported on the outside of the tie bars so as to be connected to each of the internal leads. It consists of 13 support pars.

ここで、内部リード先端は、ダイパッド２を取り囲むよ
うに所定の間隔をおいて、ダイパッドの外周と平行に配
置されている。Here, the tips of the internal leads are arranged parallel to the outer periphery of the die pad 2 at a predetermined interval so as to surround the die pad 2 .

ところで、半導体集積回路の高密度化および高集積化に
伴い、リードビン数は増加するもののパッケージは従来
通り、若しくは小型化の傾向にある。Incidentally, as semiconductor integrated circuits become more dense and highly integrated, the number of lead bins increases, but packages tend to remain the same or become smaller.

同−面積内において内部リードの本数が増加すれば、当
然ながら内部リードの幅および隣接する内部リードとの
間隔は減少する。このため、強度の低下による内部リー
ドの変形及びその変形による内部リード間の短絡を生じ
ることがある。As the number of internal leads increases within the same area, the width of the internal leads and the distance between adjacent internal leads naturally decrease. Therefore, deformation of the internal leads due to a decrease in strength and short circuits between the internal leads due to the deformation may occur.

また、半導体素子のポンディングパッドと内部リードと
をボンディングワイヤによって接続するワイヤボンディ
ングに際して、ワイヤボンダーの精度も高いものが要求
される。更にまた、ワイヤボンディングが順調に行なわ
れた後においても、ワイヤ同志の接触、短絡のおそれが
ある。Further, when wire bonding is performed to connect the bonding pad of a semiconductor element and an internal lead using a bonding wire, a wire bonder is required to have high precision. Furthermore, even after wire bonding is successfully performed, there is a risk that the wires may come into contact with each other and short circuit.

本発明は、前記実情に鑑みてなされたもので、信頼性の
高い半導体装置を得ることのできるり一ドフレームを提
供することを目的とする。The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a frame that can provide a highly reliable semiconductor device.

〔問題点を解決するための手段〕[Means for solving problems]

そこで本発明のリードフレームでは、半導体素子を搭載
するためのダイパッドの近傍に先端が延設せしめられて
なる内部リードのうちの１部が先端部で他の内部リード
よりもリード幅が小さくなるように形成されると共に、
他の内部リードの先端よりもダイパッドに近接するよう
に伸長する幅広部を形成するように構成されている。Therefore, in the lead frame of the present invention, one part of the internal leads whose tips extend near the die pad for mounting a semiconductor element has a smaller lead width at the tip than the other internal leads. Along with being formed,
It is configured to form a wide portion that extends closer to the die pad than the tips of the other internal leads.

〔作　用〕[For production]

上記構成により、１部の内部リードのリード幅が狭くな
っている分だけ、内部リード間の間隔を広くとることが
できる。With the above configuration, the interval between the internal leads can be increased by the narrower lead width of some of the internal leads.

一方、リード幅の狭い内部リードは先端に突出する幅広
部を有しているため、充分なボンディングエリアを得る
ことができ、確実なボンディングが可能である。On the other hand, since the internal lead having a narrow lead width has a wide portion that protrudes at the tip, a sufficient bonding area can be obtained and reliable bonding can be performed.

また、ダイパッドに近接した分だけ、ボンディングワイ
ヤを短くすることができる上、これに伴い、ワイヤ同志
あるいはワイヤと内部リード間の接触や短絡も低減され
る。Further, the bonding wire can be shortened by the proximity to the die pad, and contact and short circuits between the wires or between the wires and the internal leads are also reduced accordingly.

〔実施例〕〔Example〕

以下、本発明の実施例について、図面を参照しつつ詳細
に説明する。Embodiments of the present invention will be described in detail below with reference to the drawings.

第１図は、本発明実施例のリードフレームの要部拡大図
である。FIG. 1 is an enlarged view of main parts of a lead frame according to an embodiment of the present invention.

このリードフレームは、内部リードの先端部の形状に特
徴を有するものでダイパッド２の周囲に伸長する２０本
の内部リード４を含み、この内部リードは第１のリード
４ａと、ライン１の位置で該第１のリード４ａのリード
幅ｔ１よりもリード幅ｔ２が小さくかつ先端が第１のリ
ード４ａよりもダイパッド２に近接するように伸長し幅
広部ｆを形成してなる第２のり一ド４ｂとからなり、第
１のリード４ａと第２のり一ド４ｂとが千鳥状すなわち
交互に配置せしめられている。ここで１３′はサポート
バーである。また他の部分については、第３図＜　ｂ　
＞　ｉ−１単位の全体図を示したものと同様である。す
なわち半導体素子を搭載するためのダイパッド２と先端
が該ダイパッドをとり囲むように延在せしめられた２０
本の内部り一ド４と、該内部リードとほぼ直交する方向
に延びこれら内部リードを一体的に支持するタイバー１
１と、該タイバーの外側に前記各内部リードに接続する
ように配設せしめられた外部リード１２とから構成され
ている。This lead frame is characterized by the shape of the tips of the internal leads, and includes 20 internal leads 4 extending around the die pad 2. A second glue lead 4b having a lead width t2 smaller than the lead width t1 of the first lead 4a and whose tip extends closer to the die pad 2 than the first lead 4a to form a wide part f. The first leads 4a and the second leads 4b are arranged in a staggered manner, that is, alternately. Here, 13' is a support bar. For other parts, see Figure 3 < b
> This is the same as the overall diagram of the i-1 unit. That is, a die pad 2 for mounting a semiconductor element and a tip 20 extending so as to surround the die pad.
The inner leads 4 of the book and the tie bars 1 extending in a direction substantially perpendicular to the inner leads and integrally supporting these inner leads.
1, and an external lead 12 disposed on the outside of the tie bar so as to be connected to each of the internal leads.

このリードフレームによれば、第２のリードのリード幅
ｔ２が第１のリードのリード幅ｔ１よりも狭くなってい
る分だけ、内部リード間の間隔を広くすることができる
ため、強度の低下によってリードが変形してもリード同
志の短絡を防止することができる。また、間隔を広くと
る代わりにリード幅を少しでも大きくすればリードの変
形を防止することができる。According to this lead frame, the interval between internal leads can be increased by the amount that the lead width t2 of the second lead is narrower than the lead width t1 of the first lead, so that the strength is reduced. Even if the leads are deformed, short circuits between the leads can be prevented. Further, deformation of the leads can be prevented by increasing the lead width even a little instead of widening the interval.

また、内部リード間の間隔の増大に加えて、第２のリー
ドの先端は幅広部を構成しているため、充分なボンディ
ングエリアを得ることができ、ボンディングを確実にす
ることができる。Furthermore, in addition to the increased spacing between the internal leads, the tips of the second leads constitute a wide portion, so that a sufficient bonding area can be obtained and bonding can be ensured.

更には、幅広部が、ダイパッドに近接した分だけ、ボン
ディングワイヤを短くすることができ、ワイヤ同志ある
いはワイヤと内部リード間の接触や短絡も低減される。Furthermore, the bonding wire can be made shorter as the wide portion is closer to the die pad, and contact and short circuits between the wires or between the wires and the internal leads are reduced.

なお、実施例では、第１のリードと、第１のリードより
もリード幅の狭い第２のリードとを交互に配置したが、
必ずしも交互とする必要はなく、適宜配置可能である。In addition, in the embodiment, the first lead and the second lead having a narrower lead width than the first lead are arranged alternately.
They do not necessarily have to be arranged alternately, and can be arranged as appropriate.

また、リードのパターン形状についても実施例に限定さ
れるものではない。Furthermore, the shape of the lead pattern is not limited to the embodiment.

更に、第２のリードは、先端近傍で第１のリードよりも
リード幅が小さければよく、タイバーの部分でのリード
幅は、適宜選択可能である。Furthermore, the second lead only needs to have a smaller lead width than the first lead near the tip, and the lead width at the tie bar portion can be selected as appropriate.

〔発明の効果〕〔Effect of the invention〕

以上説明してきたように、本発明のリードフレームによ
れば、先端がダイパッドに近接するように配置された内
部リードのうちの１部が他の内部リードよりもリード幅
が小さくかつ、先端が他の内部リードの先端よりもダイ
パッドに近接するように伸長する幅広部を形成している
ため、内部リード同志およびボンディングワイヤの短絡
等を防止することができ、信頼性の高い半導体装置を得
ることができる。As described above, according to the lead frame of the present invention, one of the internal leads arranged so that the tip is close to the die pad has a smaller lead width than the other internal leads, and Since a wide part is formed that extends closer to the die pad than the tips of the internal leads, it is possible to prevent short circuits between the internal leads and the bonding wires, and to obtain a highly reliable semiconductor device. can.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明実施例のリードフレームの部分拡大説
明図、第２図は、通常の半導体装置の実装状態を示す図
、第３図（ａ）および１３図（ｂ）は従来例のリードフ
レームおよびその部分拡大図である。 １・・・リードフレーム、２・・・ダイパッド、３・・
・半導体素子、４・・・内部リード、４ａ・・・第１の
リード、４ｂ・・・第２のリード、５・・・ボンディン
グワイヤ、１１・・・タイバー、１２・・・外部リード
。 第１図 第２図FIG. 1 is a partially enlarged explanatory diagram of a lead frame according to an embodiment of the present invention, FIG. 2 is a diagram showing a mounting state of a normal semiconductor device, and FIGS. 3(a) and 13(b) are diagrams of a conventional example. It is a lead frame and its partially enlarged view. 1...Lead frame, 2...Die pad, 3...
- Semiconductor element, 4... Internal lead, 4a... First lead, 4b... Second lead, 5... Bonding wire, 11... Tie bar, 12... External lead. Figure 1 Figure 2

Claims (2)

【特許請求の範囲】[Claims] （１）半導体素子を搭載するためのダイパッドと、 先端が該ダイパッドの近傍に延設せしめられてなる複数
の内部リードと、 該内部リードから外方に伸長せしめられる外部リードと
、 これら内部リードおよび外部リードを支持するタイバー
とを具えたリードフレームにおいて、前記内部リードの
うちの１部が他の内部リードよりも小さいリード幅でダ
イパッドにより近接するように伸長し、 先端で幅広部を形成するようにしたことを特徴とするリ
ードフレーム。(1) A die pad for mounting a semiconductor element, a plurality of internal leads whose tips extend near the die pad, external leads extending outward from the internal leads, and these internal leads and and a tie bar supporting external leads, wherein one of the internal leads extends closer to the die pad with a smaller lead width than the other internal leads, forming a wide portion at the tip. A lead frame characterized by: （２）前記内部リードは先端に幅広部を有するものと有
さないものが交互となるように配置されていることを特
徴とする特許請求の範囲第（１）項記載のリードフレー
ム。(2) The lead frame according to claim (1), wherein the internal leads are arranged such that those having a wide portion at their tips and those not having a wide portion at their tips alternate.
JP62107497A 1987-04-30 1987-04-30 Lead frame Expired - Fee Related JPH0824159B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62107497A JPH0824159B2 (en) 1987-04-30 1987-04-30 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62107497A JPH0824159B2 (en) 1987-04-30 1987-04-30 Lead frame

Publications (2)

Publication Number Publication Date
JPS63272062A true JPS63272062A (en) 1988-11-09
JPH0824159B2 JPH0824159B2 (en) 1996-03-06

Family

ID=14460707

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62107497A Expired - Fee Related JPH0824159B2 (en) 1987-04-30 1987-04-30 Lead frame

Country Status (1)

Country Link
JP (1) JPH0824159B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030053970A (en) * 2001-12-24 2003-07-02 동부전자 주식회사 Lead frame of semiconductor package

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6190452A (en) * 1984-10-09 1986-05-08 Nec Corp Lead frame for semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6190452A (en) * 1984-10-09 1986-05-08 Nec Corp Lead frame for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030053970A (en) * 2001-12-24 2003-07-02 동부전자 주식회사 Lead frame of semiconductor package

Also Published As

Publication number Publication date
JPH0824159B2 (en) 1996-03-06

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