JPS63272056A - Connection electrodes of integrated semiconductor device - Google Patents
Connection electrodes of integrated semiconductor deviceInfo
- Publication number
- JPS63272056A JPS63272056A JP62104230A JP10423087A JPS63272056A JP S63272056 A JPS63272056 A JP S63272056A JP 62104230 A JP62104230 A JP 62104230A JP 10423087 A JP10423087 A JP 10423087A JP S63272056 A JPS63272056 A JP S63272056A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- electrode
- wiring board
- connection
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000007747 plating Methods 0.000 claims abstract description 6
- 229910052802 copper Inorganic materials 0.000 claims abstract description 4
- 229910052737 gold Inorganic materials 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims 1
- 229910045601 alloy Inorganic materials 0.000 claims 1
- 229910052718 tin Inorganic materials 0.000 claims 1
- 230000004907 flux Effects 0.000 abstract description 12
- 229910052751 metal Inorganic materials 0.000 abstract description 9
- 239000002184 metal Substances 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract description 7
- 238000009713 electroplating Methods 0.000 abstract description 6
- 229910000679 solder Inorganic materials 0.000 description 11
- 238000010438 heat treatment Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000002844 melting Methods 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000005275 alloying Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 241000277269 Oncorhynchus masou Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体素子の実装方法に係り、特に高密度の突
起ｉ′ｆｔｗ４を有するフリップチップ型の半導体素子
を配線基板に接続するのに好適な集積半導体装置の接続
用電極の構造及びその製法に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for mounting a semiconductor element, and is particularly suitable for connecting a flip-chip type semiconductor element having high-density protrusions i'ftw4 to a wiring board. The present invention relates to a structure of a connection electrode of an integrated semiconductor device and a method of manufacturing the same.
従来のフリップチップ素子の突起電極には、特開昭６１
−６５４４２号あるいは特開昭５９−２１０６４９号に
記載のようにＰ ｂ ／ Ｓ ｎ系をはじめとする低融
点のはんだ材が用いられている。また、鉛−インジウム
系の突起電極については、アイ・イー・イー・トランザ
クション オン パーツ、ハイブリッドアンドパッケー
ジング、ビーエッチビー１３゜（１９７７年）第１９４
頁から第１９８頁（ＩＨＨＩＩＥ 。The protruding electrodes of conventional flip-chip devices are disclosed in JP-A-61
As described in JP-A-65442 or JP-A-59-210649, low-melting point solder materials such as Pb/Sn-based solders are used. Regarding lead-indium protruding electrodes, IE Transactions on Parts, Hybrid and Packaging, BHC 13° (1977) No. 194
Pages 198 to 198 (IHHIIE.
Ｔｒａｎｓａｃｔｉｏｎ ｏｎ ｐｏｒｔｓ、Ｈｙｂｒ
ｉｄ、ａｎｄ Ｐａｃｋａｇｉｎｇｖｏｌ、ＰＨＰ−１
３，Ｎ１１３ （１９７７） ＰＰＩ ９４−１９８）
において論じられている。この突起Ｗ１ｔｉは通常、メ
カニカルマスクを用いてはんだ材を選択蒸着した後、は
んだ電極を加熱溶融することにより得られる。また、配
線基板に搭載後はんだ電極を再溶融することにより基板
相互の接続を行っていた。しかし、これらの方法では半
導体素子の高集積化に伴う突起電極の高密度化に対する
配慮がされていなかった。すなわち、メカニカルマスり
の加工寸法に限界があり、１００μｍ以上の高さを持つ
突起電極を２００μｍ以下のｆ！！極ピッチで実現する
ことが不可能であった。さらに、フリップチップボンデ
ィング工程において、従来のはんだ電極ではフラックス
の使用が余儀なくされるため、ボンディング後の僅かな
フラックス残渣により接続部の腐食が進行して素子の信
頼性を損ねる問題があり、このようなフラックスの完全
除去に対する配慮も不充分であった。特に突起電極の高
密度化により電極間隔が減少し、フラックスの洗浄除去
が増々困霞になることが予測される。Transaction on ports, Hybr
id, and Packagingvol, PHP-1
3, N113 (1977) PPI 94-198)
It is discussed in This protrusion W1ti is usually obtained by selectively depositing a solder material using a mechanical mask and then heating and melting the solder electrode. Further, after mounting on a wiring board, the solder electrodes are remelted to connect the boards to each other. However, these methods do not take into account the increased density of protruding electrodes that accompanies the increased integration of semiconductor devices. In other words, there is a limit to the processing dimensions of mechanical massing, and a protruding electrode with a height of 100 μm or more can be reduced to an f! of 200 μm or less. ! It was impossible to achieve this with extreme pitch. Furthermore, in the flip-chip bonding process, conventional solder electrodes require the use of flux, so there is a problem that a small amount of flux residue after bonding progresses corrosion of the connection part and impairs the reliability of the device. There was also insufficient consideration given to the complete removal of flux. In particular, it is predicted that as the density of protruding electrodes increases, the electrode spacing will decrease, making cleaning and removal of flux increasingly difficult.
上記従来技術は半導体素子上に形成する突起電極の高密
度化に対する配慮がされておらず、高さが１００μｍ以
上の突起電極を２００μｍ以下のピッチで形成できない
問題があった。さらに、はんだ材で構成する突起電極を
配線基板上に溶融接続する際にフラックスの使用が不可
欠であり、このフラックスの残渣に対する配慮も不充分
であり、接続部の汚染及び腐食に起因する実装素子の信
頼性低下を招く問題があった。The above-mentioned conventional technology does not take into consideration the high density of protruding electrodes formed on a semiconductor element, and there is a problem that protruding electrodes having a height of 100 μm or more cannot be formed at a pitch of 200 μm or less. Furthermore, the use of flux is essential when melting and connecting protruding electrodes made of solder material onto wiring boards, and insufficient consideration is given to the residue of this flux. There was a problem that led to a decrease in reliability.
本発明の目的は上記２点を鑑み、高アスペクト比の突起
電極の高密度比が図れ、且つフラックスを用いないで清
浄な雰囲気のもとてフリップチップボンディングを可能
にする接続用電極を提供することにある。In view of the above two points, it is an object of the present invention to provide a connection electrode that can achieve a high density ratio of protruding electrodes with a high aspect ratio, and also enables flip-chip bonding in a clean atmosphere without using flux. There is a particular thing.
上記目的は、微細パターンの加工が容易なホトリソグラ
フィ技術と金属層の渾膜形成が可能な電気めっき技術の
組み合せにより突起電極を形成し、且つ突起電極の接続
面に低温で合金化反応が進行する金属膜を予め形成して
おくことにより達成される。The above purpose is to form protruding electrodes by a combination of photolithography technology, which facilitates the processing of fine patterns, and electroplating technology, which enables the formation of a metal layer, and to allow an alloying reaction to proceed at low temperatures on the connection surface of the protruding electrodes. This is achieved by forming a metal film in advance.
まず、半導体素子あるいは配線基板上に１００μｍ以上
の厚膜レジストを塗布し電極のパターニングを行う、こ
のレジスト膜が突起電極形成時の選択マスクとなる。ま
た、レジスト膜厚に対応して突起電極の高さが決定する
。レジストの厚膜化に従ってパターン加工精度が増加す
るが、ホトリソグラフィ技術での露光、現像条件の最適
化により１００μｍ厚のレジスト膜に対して１００μｍ
φのｆｆ１ｔ！パターンを１５０μｍピッチで形成でき
ることが分かった。一方、ＡｕあるいはＣｕのめつき時
にはパターニングを行った開口部のみにめっき金属が堆
積する。すなわち、レジスト膜のパターン寸法及び形状
に従って突起電極の寸法及び形状が決定するため、１０
０μｍの高さを持つ突起電極を１５０μｍ以下のピッチ
で形成可能になる。First, a thick resist film of 100 μm or more is applied onto a semiconductor element or a wiring board, and electrodes are patterned. This resist film serves as a selective mask when forming protruding electrodes. Further, the height of the protruding electrode is determined depending on the resist film thickness. The pattern processing accuracy increases as the resist film becomes thicker, but by optimizing the exposure and development conditions in photolithography technology, the pattern processing accuracy can be reduced to 100 μm for a 100 μm thick resist film.
φ's ff1t! It was found that patterns could be formed at a pitch of 150 μm. On the other hand, when plating Au or Cu, the plating metal is deposited only on the patterned openings. That is, since the dimensions and shape of the protruding electrode are determined according to the pattern dimensions and shape of the resist film,
It becomes possible to form protruding electrodes with a height of 0 μm at a pitch of 150 μm or less.
また、この突起電極の下層及びフリップチップボンディ
ング時に対向する電極面に予めＡ ｕ ／ Ｓ ｎある
いはＡ ｕ ／ Ｇ ｎ層を形成しておくことにより、
ボンディング時にこれらの金属が溶融し、突起電極金属
と合金化反応するために機械的に強固な接続が実現でき
る。特に加熱時に基板相互を十分に加圧することにより
接続強度の安定化が図れる。In addition, by forming an A u / S n or A u / G n layer in advance on the lower layer of this protruding electrode and on the electrode surface opposite during flip chip bonding,
During bonding, these metals melt and undergo an alloying reaction with the protruding electrode metal, making it possible to achieve a mechanically strong connection. In particular, by applying sufficient pressure between the substrates during heating, the connection strength can be stabilized.
以下、本発明の実施例を第１図、第２図、第３図、第４
図を用いて説明する。Embodiments of the present invention will be described below with reference to FIGS. 1, 2, 3, and 4.
This will be explained using figures.
実施例１
第１図、第２図に本発明を用いてＳｉバイポーラＬＳＩ
を配線基板上にフリップチップボンディングした例を示
す、第１図（ａ）に示すように、ＬＳＩ素子１０１上に
予めＡｕを主成分とする突起１ｔｔＪｉ１０２を形成し
た。この接続部の断面構造第１図（ｂ）に示した。突起
電極１０２の下層に予めＡ ｕ ／ Ｓ ｎ層（上部金
属をＡｕとする）を形成し、この電極上に電気めっきに
よりＡｕ柱を形成した。さらに、配線基板１０１の配線
金属層１０５上にＬＳＩ素子側のＡ ｕ ／ Ｓ ｎ
ｆ！！極１０２’と同一組成のＡ ｕ ／ Ｓ ｎ電極
１０２′を形成し、相互の電極を位置合わせ後加熱溶融
することにより第１図（ｃ）に示すようにＬＳ ＩＪ子
１０１を配線基板１０３上に突起電極１０２を介して接
続した。Example 1 A Si bipolar LSI was constructed using the present invention in FIGS. 1 and 2.
As shown in FIG. 1(a), which shows an example of flip-chip bonding on a wiring board, protrusions 1ttJi102 containing Au as a main component were previously formed on an LSI element 101. The cross-sectional structure of this connection portion is shown in FIG. 1(b). An A u /S n layer (the upper metal is Au) was formed in advance under the protruding electrode 102, and Au pillars were formed on this electrode by electroplating. Further, on the wiring metal layer 105 of the wiring board 101, A u / S n on the LSI element side
f! ! By forming an A u/S n electrode 102' having the same composition as the electrode 102' and heating and melting the electrodes after aligning them, the LS IJ element 101 is placed on the wiring board 103 as shown in FIG. 1(c). was connected to via a protruding electrode 102.
めっきにより形成する金属柱は予め配線基板側に形成し
ておいても良い。また、電気めっきの他に無電解めっき
の適用も可能である１次にこれらの製法を第２図及び第
３図を用いて詳細に説明する。まずＬＳＩ素子２０１の
配線層２０６上に突起電極の下地電極としてＡ ｕ ／
Ｎ ｉ ／ Ｔ ｉ電極２０２を形成した。次にこの
電極上にＳｎＭ２Ｏ３゜Ａ ｕ Ｍ ２０４を連続蒸着
した。次いで、レジスト膜を塗布（１５０μｒｎ）Ｌ電
極のパターニングを行った・このレジスト膜をマスクと
してＡｕ２０５の電気めっき（１００μｍ厚）を行い、
レジスト膜除去及び電極部以外の不要Ａ ｕ ／ Ｓ
ｎ層のエツチング除去を通して第３図（ａ）に示す電極
構造を得た。一方、配線基板２０８側にも第３図（ｂ）
に示すように上記電極２０２，２０３，２０４と同一の
電極を形成した。次に第３図（ｃ）に示すように、配線
基板２０８上にＬＳＩ素子２０１を位置合わせした後加
熱処理により相互の基板接続を行った。なお、この工程
では素子に荷重を加えながら熱処理することにより接続
強度の向上がみられた。なお、本実施例では、ＬＳＩ素
子と配線基板をそれぞれ置き換えることができる０本実
施例によれば突起電極の加工をホトリソグラフィの加工
精度で実施できるため、突起電極の寸法精度の向上、Ｗ
１極の高密度化が図れる。さらに基板接続時にフラック
スを用いないため、ボンディング後の実装素子の信頼性
を飛躍的に向上する効果がある。The metal pillars formed by plating may be formed in advance on the wiring board side. Further, in addition to electroplating, electroless plating can also be applied. These manufacturing methods will be explained in detail with reference to FIGS. 2 and 3. First, A u /
A Ni/Ti electrode 202 was formed. Next, SnM2O3°A u M 204 was continuously deposited on this electrode. Next, a resist film was applied (150 μrn) and the L electrode was patterned. Using this resist film as a mask, Au205 was electroplated (100 μm thick).
Unnecessary A u/S other than resist film removal and electrode part
The electrode structure shown in FIG. 3(a) was obtained by removing the n-layer by etching. On the other hand, on the wiring board 208 side, as shown in FIG.
The same electrodes as the electrodes 202, 203, and 204 were formed as shown in FIG. Next, as shown in FIG. 3(c), after aligning the LSI element 201 on the wiring board 208, the boards were connected to each other by heat treatment. In addition, in this step, the connection strength was improved by heat-treating the element while applying a load. In addition, in this embodiment, the LSI element and the wiring board can be respectively replaced. According to this embodiment, the protruding electrodes can be processed with the processing accuracy of photolithography, so the dimensional accuracy of the protruding electrodes can be improved, and W
High density of one pole can be achieved. Furthermore, since flux is not used when connecting the substrate, it has the effect of dramatically improving the reliability of mounted elements after bonding.
実施例２
第４図に高周波ＦＥＴ集積回路パッケージを示す。まず
、フリップチップ化したＭＭＩＣ（Ｍｏｎｏｌｉｔｈｉ
ｃＭｉｅｒｏｗａｖｅ Ｉｎｔｅｇｒａｔｅｄ Ｃ１ｒ
ｃｕｉｔ）素子３０１をＰ ｂ ／ Ｓ ｎはんだバン
プ３０２を介して配線基板３０３上にフェースダウンで
ボンディングした。この配線基板３０３上の外部電極端
子には予めホトレジスト膜をマスクとしてＡｕの電気め
っきあるいは無電解めっきを行い柱状の突起電極３０４
を形成しておく。次にセラミックパッケージ３０６の電
極パッドと配線基板の突起電極３０４を位置合わせした
後、配線基板を下側にして加熱処理により相互の電極を
接続した。なお、パッケージの電極パッド３０６上には
予めＡｕ／Ｓｎ層を形成した。さらに、チップとパッケ
ージの間隙に熱伝導性樹脂３０９を充填固着後、配線基
板固着用はんだ３０５を介してパッケージのリッド３０
７付けを行った。本実施例によれば配線による寄生イン
ダクタンスの制御が重要となる高周波素子において配線
抵抗及び配線インダクタンスの低減及び均一化が図れる
ため従来の実装方式に比べ著しい性能向上の効果がある
。Embodiment 2 FIG. 4 shows a high frequency FET integrated circuit package. First, a flip-chip MMIC (Monolithi)
cMierowave Integrated C1r
Cuit) The element 301 was bonded face down onto the wiring board 303 via the Pb/Sn solder bumps 302. External electrode terminals on this wiring board 303 are coated with Au electroplating or electroless plating using a photoresist film as a mask in advance to form columnar protruding electrodes 304.
Form it. Next, after aligning the electrode pads of the ceramic package 306 and the protruding electrodes 304 of the wiring board, the electrodes were connected to each other by heat treatment with the wiring board facing down. Note that an Au/Sn layer was previously formed on the electrode pad 306 of the package. Furthermore, after filling and fixing a thermally conductive resin 309 into the gap between the chip and the package, the lid 30 of the package is soldered via solder 305 for fixing the wiring board.
I gave it a 7. According to this embodiment, the wiring resistance and wiring inductance can be reduced and made uniform in a high-frequency element in which control of parasitic inductance due to wiring is important, so that there is a significant performance improvement effect compared to the conventional mounting method.
実施例３
第５図にウェーハ規模集積回路基板の積層実装例を示す
。第５図（ａ）−に示すように集積回路基板４０１の上
面にＡ ｕ ／ Ｓ ｎ電極５０３を形成後。Embodiment 3 FIG. 5 shows an example of stacking and mounting a wafer-scale integrated circuit board. After forming the Au/Sn electrode 503 on the upper surface of the integrated circuit board 401 as shown in FIG. 5(a).
厚膜レジストをマスクとしてＡｕの電気めっきにより柱
状の突起電極４０２を形成した。さらに貫通配線層４０
２を介して突起電極と反対の位置に表面と同一組成のＡ
ｕ ／ Ｓ ｎ電極を形成した。この集積回路基板を
複数枚積層した後、加熱処理により第５図（ｂ）のよう
に回路基板相互の接続を実施した０本実施例によれば、
突起電極が５００個／ｄを超えるような高密度の電極接
続をフラックスを用いないで実施できるためフランクス
残渣による素子の汚染、腐食が皆無になり実装システム
全体の信頼度向上に効果がある。Columnar protruding electrodes 402 were formed by electroplating Au using a thick film resist as a mask. Furthermore, the through wiring layer 40
A with the same composition as the surface is placed opposite the protruding electrode through 2.
U/S n electrodes were formed. According to this embodiment, after a plurality of integrated circuit boards are stacked, the circuit boards are connected to each other by heat treatment as shown in FIG. 5(b).
Since high-density electrode connections with more than 500 protruding electrodes/d can be performed without using flux, there is no contamination or corrosion of elements due to Franks residue, which is effective in improving the reliability of the entire mounting system.
本発明によれば、半導体素子の実装において、接続用電
極ピッチを縮小できるため半導体素子に形成する電極密
度を向上する効果がある。これにより実装デバイスある
いはシステムを小型化できる。また、電極間の接続工程
でフラックスが不必要となり清浄な雰囲気中で電極接続
が可能である。According to the present invention, in mounting a semiconductor element, since the pitch of connection electrodes can be reduced, the density of electrodes formed on the semiconductor element can be improved. This allows the mounted device or system to be miniaturized. Further, flux is not required in the process of connecting the electrodes, and the electrodes can be connected in a clean atmosphere.
このため、フラックスによる汚染、腐食が皆無であり、
接続部の信頼性を著しく向上する効果がある。Therefore, there is no contamination or corrosion caused by flux.
This has the effect of significantly improving the reliability of the connection.
本発明はＳｉ基板を用いた［Ｃ，ＬＳＩ素子の他に種々
の化合物半導体基板を用いたＩＣ，ＬＳＩ素子及び発光
素子等の単体デバイスの実装用接続電極として有効であ
る。The present invention is effective as a connection electrode for mounting single devices such as ICs, LSI elements, and light emitting elements using various compound semiconductor substrates in addition to LSI elements using Si substrates.
第１図は本発明によるＳｉ ＬＳＩの実装構造を示す
斜視図及び縦断面図、第２図は第１図の製造工程フロー
、第３図はそのＷ造縦断面図、第４図は本発明による高
周波ＦＦ：Ｔｉ子の実装方法の一実施例を示す縦断面図
、第５図は本発明によるウェーハ規模集積回路の積層実
装方法の一実施例を示す縦断面図である。
１０１・・・Ｓｉ、ＬＳＩ素子、１０２・・・突起電極
。
１０２’・ＬＳＩ素子側Ａ ｕ ／ Ｓ ｎ ｆ＆極、
１０２’・・・配線基板側Ａ ｕ ／ Ｓ ｎ電極、
１０３・・・配線基板、１０４・・・絶縁膜、１０５・
・・配線導体、１０６・・・絶縁膜、２０１−８ｉ
ＬＳＩ素子−２０２・＝Ａｕ／ Ｎ ｉ ／ Ｔ ｉ電
極、２０３− Ｓ ｎ層、２０４・・・Ａｕ層、２０５
・・・Ａｕ突起電極、２０６・・・配線導体、２０７・
・・絶縁膜、２０８・・・配線基板、３０１・・・高周
波ＦＥＴ素子、３０２・・・はんだバンプ。
３０３・・・配線基板、３０４・・・Ａｕ突起電極、３
０５・・・配線基板固着用はんだ、３０６・・・パッケ
ージ本体、３０７・・・リッド、３０８・・・外部端子
、３０９・・・熱伝導性樹脂、４０１・・・ウェーハ規
模集積回路、４０２ ・・・貫通配線層、 ４０３−Ａ
ｕ／ Ｓ ｕｆｔｔ極、代理人 升理工 小川ＦＩｙ
Ｉぐ ；第 １ 図
１０ｈ・・・紺Ｊ象墜
２０８・・・配線基板
＄４ＥＪ
、３０９・・・熱伝導性樹脂
第 ５ 目
（すFIG. 1 is a perspective view and a vertical cross-sectional view showing the mounting structure of a Si LSI according to the present invention, FIG. 2 is a manufacturing process flow of FIG. 1, FIG. 3 is a vertical cross-sectional view of the W structure, and FIG. FIG. 5 is a longitudinal sectional view showing an embodiment of the method for mounting a wafer-scale integrated circuit in a stacked manner according to the present invention. 101...Si, LSI element, 102...Protrusion electrode. 102'・LSI element side A u / S n f & pole,
102'...Wiring board side A u/S n electrode,
103... Wiring board, 104... Insulating film, 105...
...Wiring conductor, 106...Insulating film, 201-8i
LSI element-202・=Au/Ni/Ti electrode, 203-Sn layer, 204...Au layer, 205
...Au protruding electrode, 206...wiring conductor, 207.
... Insulating film, 208 ... Wiring board, 301 ... High frequency FET element, 302 ... Solder bump. 303... Wiring board, 304... Au protruding electrode, 3
05... Solder for fixing wiring board, 306... Package body, 307... Lid, 308... External terminal, 309... Thermal conductive resin, 401... Wafer scale integrated circuit, 402 ・...Through wiring layer, 403-A
u/ S uftt Goku, agent Masu Riko Ogawa FIy
Ig; 1st Fig. 10h...Navy J 208...Wiring board $4EJ, 309...Thermal conductive resin No. 5
Claims (1)
相互接続する実装構造において、該接続用電極が感光性
レジストをマスクとして選択的にめつきされたＡｕある
いはＣｕにより構成されることを特徴とする集積半導体
装置の接続用電極。 ２、特許請求の範囲第１項に記載の接続用電極構造にお
いて、めつき層の下地電極として第１層にＳｎあるいは
Ｇｅ、第２層にＡｕを用いた２層膜あるいはこれらの合
金膜を設けることを特徴とする集積半導体装置の接続用
電極。[Claims] 1. In a mounting structure for interconnecting flip-chip semiconductor elements or wiring substrates, the connection electrodes are made of Au or Cu selectively plated using a photosensitive resist as a mask. A connection electrode for an integrated semiconductor device, characterized by: 2. In the connection electrode structure according to claim 1, a two-layer film using Sn or Ge for the first layer and Au for the second layer, or an alloy film of these, is used as the base electrode of the plating layer. An electrode for connection of an integrated semiconductor device, characterized in that it is provided with an electrode for connection of an integrated semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62104230A JPS63272056A (en) | 1987-04-30 | 1987-04-30 | Connection electrodes of integrated semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62104230A JPS63272056A (en) | 1987-04-30 | 1987-04-30 | Connection electrodes of integrated semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63272056A true JPS63272056A (en) | 1988-11-09 |
Family
ID=14375161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62104230A Pending JPS63272056A (en) | 1987-04-30 | 1987-04-30 | Connection electrodes of integrated semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63272056A (en) |
-
1987
- 1987-04-30 JP JP62104230A patent/JPS63272056A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0398485B1 (en) | A method of making a Flip Chip Solder bond structure for devices with gold based metallisation | |
| US6858941B2 (en) | Multi-chip stack and method of fabrication utilizing self-aligning electrical contact array | |
| US6940169B2 (en) | Torch bump | |
| US6960828B2 (en) | Electronic structures including conductive shunt layers | |
| US8710664B2 (en) | Wafer-level chip scale package | |
| US7906425B2 (en) | Fluxless bumping process | |
| US6825547B2 (en) | Semiconductor device including edge bond pads | |
| US6319751B1 (en) | Bumpless flip chip assembly with solder via | |
| US7338891B2 (en) | Semiconductor chip, mounting structure thereof, and methods for forming a semiconductor chip and printed circuit board for the mounting structure thereof | |
| US6583039B2 (en) | Method of forming a bump on a copper pad | |
| US20040206801A1 (en) | Electronic devices including metallurgy structures for wire and solder bonding | |
| JP2000100851A (en) | Semiconductor substrate and manufacture thereof and structure and method for mounting semiconductor parts | |
| KR20010067448A (en) | Wire bonding method for copper interconnects in semiconductor devices | |
| KR20030067590A (en) | Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same | |
| US5646068A (en) | Solder bump transfer for microelectronics packaging and assembly | |
| JPH0214796B2 (en) | ||
| US6664176B2 (en) | Method of making pad-rerouting for integrated circuit chips | |
| JP2007184381A (en) | Flip chip mounting circuit board, its manufacturing method, semiconductor device, and its manufacturing method | |
| JPH07201864A (en) | Projection electrode formation method | |
| JPH06132474A (en) | Semiconductor device | |
| US20050026416A1 (en) | Encapsulated pin structure for improved reliability of wafer | |
| JPH11340270A (en) | Solder bump formation method and manufacture of semiconductor module | |
| JPS63272056A (en) | Connection electrodes of integrated semiconductor device | |
| JPS63168028A (en) | Fine connection structure | |
| JPH09321050A (en) | Forming barrier metal in solder ball bump forming process |