JPS63261736A - Printed wiring board - Google Patents

Printed wiring board

Info

Publication number
JPS63261736A
JPS63261736A JP9654987A JP9654987A JPS63261736A JP S63261736 A JPS63261736 A JP S63261736A JP 9654987 A JP9654987 A JP 9654987A JP 9654987 A JP9654987 A JP 9654987A JP S63261736 A JPS63261736 A JP S63261736A
Authority
JP
Japan
Prior art keywords
holes
circuit chips
conductor layer
inner conductor
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9654987A
Other languages
Japanese (ja)
Inventor
Eiichi Tsunashima
瑛一 綱島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP9654987A priority Critical patent/JPS63261736A/en
Publication of JPS63261736A publication Critical patent/JPS63261736A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]

Abstract

PURPOSE:To achieve high power consumption allowance, to make it possible to mount two electronic circuit chips used for dual circuits in holes in both surfaces of the same wiring board and to implement a compact configuration, by using a metal plate or a metal film as an inner conductor layer, attaching multilayer interconnection boards having the holes to both surfaces of the inner conductor layer, and mounting the electronic circuit chips in said holes. CONSTITUTION:Aluminum is used for a metal plate, i.e., an inner conductor layer 10. As wiring boards, insulating layers 6 and 7 made of aramid-fiber epoxy-resin impregnated cloth and electrodeposited copper foils 9 and 11 are provided. Die bonding of semiconductor integrated circuit chips 1 and 3 on both surfaces is performed by silver paint 12 and its thermosetting. Wires 2 and 4 are gold wire. Holes 13 and 14 are provided. The thicknesses of the insulating layers 5, 6, 7 and 8 are changed by the thicknesses and the sizes of the semiconductor integrated circuit chips 1 and 3. The exposed parts of the conductor layers 9 and 11 are plated with silver and used as outer pads for the bonding of the wires 2 and 4. The hole parts can be filled with epoxy resin and the like.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、エレクトロニクス機器に使われるプリント配
線板の構造に関するもので、とり分け、三層プリント配
線に半導体チップをワイア及びダイボンディングにより
効率よく内装状態で取りつける事を可能ならしめるもの
である。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the structure of printed wiring boards used in electronics equipment, and in particular, the invention relates to the structure of printed wiring boards used in electronic equipment. This makes it possible to install it with

従来の技術 従来、半導体チップをプリント配線板にとりつける技術
はテープキャリヤ、チップオンボードがある。2. Description of the Related Art Conventionally, there are tape carriers and chip-on-board techniques for attaching semiconductor chips to printed wiring boards.

発明が解決しようとする問題点 テープキャリヤ技術は、チップの独立キャリヤーである
が多重めっき技術、ポリイミドフィルム自体のエツチン
グ技術の工数が多く、面倒な上コストが高い。チップオ
ンボード技術はチップが基板面に突出するので、チップ
又はワイアの破損の心配があり、樹脂による保護コート
の信頼性も充分でない。Problems to be Solved by the Invention Tape carrier technology is an independent carrier for chips, but requires a large number of steps for multiple plating technology and etching technology for the polyimide film itself, making it troublesome and high in cost. In the chip-on-board technology, since the chip protrudes from the substrate surface, there is a risk of damage to the chip or the wire, and the reliability of the protective resin coating is not sufficient.

加えて、半導体の放熱性が悪く、むしろ蓄熱性であり、
半導体の回路的動作の不安定さを招いていた。In addition, semiconductors have poor heat dissipation properties, rather they accumulate heat,
This led to instability in the circuit operation of semiconductors.

問題点を解決するための手段 本発明は、金属板又は金属フィルムを内層導体として用
いて、この内層導体の両面に開孔を有する多層の配線板
を、おのおの、貼り合わせて、前記各開孔内に電子回路
チップを搭載した構成である。Means for Solving the Problems The present invention uses a metal plate or a metal film as an inner layer conductor, and laminates multilayer wiring boards each having holes on both sides of the inner layer conductor. It has an electronic circuit chip mounted inside.

作用 本発明によると、電子回路チップ２個を両面の各開孔内
に配置でき、非常にコンパクトにできる。According to the present invention, two electronic circuit chips can be placed in each opening on both sides, making it extremely compact.

実施例 図面は実施例プリント配線板の要部断面図であり金属板
すなわち導体内層１０としてアルミニウムの厚さ０　、
５　ｗｓ　、配線板としてアーラミドせんいエポキシ樹
脂含浸布の絶縁層６，７の厚さ０．２５＋ｗ、銅箔９，
１１の厚さ３５μの電着鋼箔、両面の半導体集積回路チ
ップ１．３のダイボンディングは銀ペイント１２とその
１５０℃での熱硬化、ワイア２，４は直径３８μ閣の金
線、開孔１３．１４をもち、また、絶縁層５，６，７．
８の厚さは半導体集積回路チップ１，３の厚さ、大きさ
によって変更される。例として厚さ０　、２　ｍ　。The drawing of the embodiment is a sectional view of the main part of the printed wiring board of the embodiment, and the metal plate, that is, the conductor inner layer 10 is made of aluminum with a thickness of 0,
5 ws, the thickness of the insulating layers 6 and 7 of Aramide fiber epoxy resin impregnated cloth as the wiring board is 0.25+w, the copper foil 9,
Electroplated steel foil 11 with a thickness of 35 μm, die bonding of semiconductor integrated circuit chip 1.3 on both sides with silver paint 12 and heat curing at 150°C, wires 2 and 4 with gold wires with a diameter of 38 μm, and holes. 13.14, and also has insulating layers 5, 6, 7 .
The thickness of 8 changes depending on the thickness and size of semiconductor integrated circuit chips 1 and 3. For example, thickness 0, 2 m.

１、ＯＸｏ、８ｍのシリコンチップに開孔１３の径を４
ｍｍの円形、開孔１４の径を８ｍの円形とすることがで
きる。導体層９及び導体層１１の露出部分は銀めっきし
てワイア２，４のボンディングのアウターパッドとする
。1. OXo, the diameter of the opening 13 on the 8m silicon chip is 4
The diameter of the aperture 14 can be 8 m. The exposed portions of the conductor layer 9 and the conductor layer 11 are plated with silver to serve as outer pads for bonding the wires 2 and 4.

なお、開孔部には、エポキシ樹脂、シリコン樹脂、ポリ
ウレタン樹脂、ポリイミド樹脂などで充填することがで
きる。Note that the opening can be filled with epoxy resin, silicone resin, polyurethane resin, polyimide resin, or the like.

発明の効果 本発明によれば、許容消費電力がたとえば６ビン３０で
０．２５Ｗのものが、１．７５Ｗとなるなど、高い許容
消費電力が達成され、また、デュアル回路に使う電子回
路チップが同一配線基板の両面の開孔に２個実装されコ
ンパクト化が達成される。Effects of the Invention According to the present invention, a high allowable power consumption is achieved, for example, the allowable power consumption is reduced from 0.25W to 1.75W for 6 bins 30, and the electronic circuit chip used for the dual circuit is Compactness is achieved by mounting two of them in the openings on both sides of the same wiring board.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の実施例プリント配線板の要部断面図である
。 １．３・・・・・・半導体集積回路チップ、２，４・・
・・・・ワイア、５，６，７．８・・・・・・絶縁層、
９，１１・・・・・・導体層、１０・・・・・・導体内
層、１２・・・・・・ダイボンディング部分、１３．１
４・・・・・・開孔。The figure is a sectional view of a main part of a printed wiring board according to an embodiment of the present invention. 1.3...Semiconductor integrated circuit chip, 2,4...
...Wire, 5,6,7.8...Insulating layer,
9, 11... Conductor layer, 10... Conductor inner layer, 12... Die bonding part, 13.1
4...Open hole.

Claims (1)

【特許請求の範囲】[Claims] 　金属板または金属フィルムを内層導体として用いて、
この内層導体の両面に開孔を有する配線板を、おのおの
、貼り合わせて、前記各開孔内に電子回路チップを搭載
したプリント配線板。Using a metal plate or metal film as an inner layer conductor,
A printed wiring board in which wiring boards having holes on both sides of the inner layer conductor are bonded together, and electronic circuit chips are mounted in each of the holes.
JP9654987A 1987-04-20 1987-04-20 Printed wiring board Pending JPS63261736A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9654987A JPS63261736A (en) 1987-04-20 1987-04-20 Printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9654987A JPS63261736A (en) 1987-04-20 1987-04-20 Printed wiring board

Publications (1)

Publication Number Publication Date
JPS63261736A true JPS63261736A (en) 1988-10-28

Family

ID=14168168

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9654987A Pending JPS63261736A (en) 1987-04-20 1987-04-20 Printed wiring board

Country Status (1)

Country Link
JP (1) JPS63261736A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09199824A (en) * 1995-11-16 1997-07-31 Matsushita Electric Ind Co Ltd Printed wiring board and its mounting body
US5748452A (en) * 1996-07-23 1998-05-05 International Business Machines Corporation Multi-electronic device package
US6414381B1 (en) * 1999-03-15 2002-07-02 Fujitsu Media Devices Limited Interposer for separating stacked semiconductor chips mounted on a multi-layer printed circuit board
USRE41721E1 (en) * 1994-12-20 2010-09-21 Renesas Electronics Corporation Semiconductor device having an improved connected arrangement between a semiconductor pellet and base substrate electrodes
CN113038714A (en) * 2021-03-08 2021-06-25 浙江万正电子科技有限公司 Multilayer circuit board positive pitting process and aerospace high-reliability high-temperature-resistant multilayer circuit board
US20230008736A1 (en) * 2019-12-17 2023-01-12 Nitto Denko Corporation Manufacturing method for double-sided wiring circuit board and double- sided wiring circuit board

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE41721E1 (en) * 1994-12-20 2010-09-21 Renesas Electronics Corporation Semiconductor device having an improved connected arrangement between a semiconductor pellet and base substrate electrodes
USRE41722E1 (en) * 1994-12-20 2010-09-21 Renesas Electronics Corp. Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof
JPH09199824A (en) * 1995-11-16 1997-07-31 Matsushita Electric Ind Co Ltd Printed wiring board and its mounting body
US5748452A (en) * 1996-07-23 1998-05-05 International Business Machines Corporation Multi-electronic device package
US5963430A (en) * 1996-07-23 1999-10-05 International Business Machines Corporation Multi-electronic device package comprising at least two substrates and at least four layers of electrically conductive circuitry
US6101100A (en) * 1996-07-23 2000-08-08 International Business Machines Corporation Multi-electronic device package
US6414381B1 (en) * 1999-03-15 2002-07-02 Fujitsu Media Devices Limited Interposer for separating stacked semiconductor chips mounted on a multi-layer printed circuit board
US20230008736A1 (en) * 2019-12-17 2023-01-12 Nitto Denko Corporation Manufacturing method for double-sided wiring circuit board and double- sided wiring circuit board
CN113038714A (en) * 2021-03-08 2021-06-25 浙江万正电子科技有限公司 Multilayer circuit board positive pitting process and aerospace high-reliability high-temperature-resistant multilayer circuit board

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