JPS63260147A - Method of verifying pattern - Google Patents
Method of verifying patternInfo
- Publication number
- JPS63260147A JPS63260147A JP62094413A JP9441387A JPS63260147A JP S63260147 A JPS63260147 A JP S63260147A JP 62094413 A JP62094413 A JP 62094413A JP 9441387 A JP9441387 A JP 9441387A JP S63260147 A JPS63260147 A JP S63260147A
- Authority
- JP
- Japan
- Prior art keywords
- verification
- design data
- region
- regular
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 7
- 238000012795 verification Methods 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 2
- 230000001788 irregular Effects 0.000 abstract description 12
- 238000007796 conventional method Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 2
Landscapes
- Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体ウェーハもしくはマスク基板上に形成
された集積回路パターンの検証方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for verifying an integrated circuit pattern formed on a semiconductor wafer or mask substrate.
従来、との稽の集積回路パターンの検証方法は、第４図
に示す、基板４２上に形成された集積回路パターン４１
に対して、第３図に示すようにその全領域に対応した配
列をもつ検証用設計データ３１を用い、各小領域（Ａ、
Ｍとして示す）ごとに逐次照合して集積回路の１チップ
分のパターン検証を行なうものであった。Conventionally, a method of verifying an integrated circuit pattern is based on an integrated circuit pattern 41 formed on a substrate 42, as shown in FIG.
As shown in FIG. 3, each small region (A,
The pattern verification for one chip of the integrated circuit was performed by sequentially comparing each pattern (denoted as M).
前述した従来のパターン検証方法には、検証用設計デー
タのデータ量が極めて膨大になる欠点がある。近年の集
積回路は数千刃側の素子を１チツプ上に集積しており、
これらのパターンの設計データの量はギガバイトの領域
にも及ぶ膨大なものになっている。したがって集積回路
１チップ分の領域に相当する検証用設計、データも同程
度の量になシ、データの作成、計算機への入出力、パタ
ーン検証などに非常に長時間を要し、生産性が極めて悪
い。The conventional pattern verification method described above has the drawback that the amount of verification design data is extremely large. In recent years, integrated circuits have integrated thousands of blade-side elements on a single chip.
The amount of design data for these patterns is enormous, reaching into the gigabyte range. Therefore, the verification design and data equivalent to the area of one integrated circuit chip are not available, and it takes a very long time to create the data, input/output it to the computer, and verify the pattern, which reduces productivity. Extremely bad.
本発明の目的は、集積回路１チップ分のパターン設計デ
ータに比べて検証用設計データの量を少なくすることの
できる新規なパターン検証方法を提供することにある。An object of the present invention is to provide a novel pattern verification method that can reduce the amount of design data for verification compared to the pattern design data for one integrated circuit chip.
本発明の検証方法は、集積回路パターン内に単位領域が
連続的に配列してなる規則的な部分領域（規則領域）を
選択し、前記単位領域の検証用設計データ、もしくは前
記単位領域の検証用設計データによって検証した１０単
位領域の形成パターンを、前記規則領域の形成パターン
の各単位領域の照合に繰返し利用するようにしたもので
ある。The verification method of the present invention selects a regular partial region (regular region) in which unit regions are continuously arranged in an integrated circuit pattern, and selects design data for verification of the unit region or verification of the unit region. The formation pattern of 10 unit areas verified by the standard design data is repeatedly used to check each unit area of the formation pattern of the regular area.
集積回路パターンは、通常１チツプ内には単位領域の配
列からなる規則領域と、そうでなく不規則な配列をなす
不規則領域とがある。本発明では不規則領域については
、同一の配列を有する検証用設計データを用いるが、規
則領域についてはその繰返しの単位領域に対応する検証
用設計データだけを用意し、これを繰返して照合に利用
する。An integrated circuit pattern usually has a regular area consisting of an arrangement of unit areas and an irregular area consisting of an irregular arrangement within one chip. In the present invention, for irregular regions, verification design data having the same arrangement is used, but for regular regions, only verification design data corresponding to the unit region of repetition is prepared, and this is repeatedly used for verification. do.
以下、図面を参照して、本発明の一実施例につき説明す
る。第１図は、本発明の一実施例である検証用設計デー
タである。第２図はマスク基板２１上に形成された集積
回路パターン２２を示す。図にみるように、同一パター
ンの繰返しからなる規則領域あと、不規則領域器とから
なっている。これに対応して、第１図の検証用設計デー
タは、集積回路パターンｎの不規則領域るに対応する検
証用設計データ１１と、規則領域列の最小繰返し単位領
域に対応する検証用設計データ１２とを独立に用意して
おく。検証用設計データ１１は配列まで同一とするもの
である。Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows verification design data according to an embodiment of the present invention. FIG. 2 shows an integrated circuit pattern 22 formed on a mask substrate 21. FIG. As shown in the figure, it consists of a regular area consisting of repeating the same pattern and an irregular area. Correspondingly, the verification design data in FIG. 12 are prepared separately. The verification design data 11 has the same arrangement.
集積回路パターンρの検証を実施する際は、先ず被検証
領域として、不規則領域２３ヲ選択し、検証用設計デー
タ１１とを照合し、次に、規則領域列中の各最小繰返し
単位領域ごとに、前記の検証用設計データ１２ヲ繰返し
利用して照合する。When verifying the integrated circuit pattern ρ, first select the irregular region 23 as the region to be verified, compare it with the verification design data 11, and then select the irregular region 23 as the region to be verified. Then, the verification design data 12 is repeatedly used for verification.
前記実施例では、規則領域スのすべてを検証用設計デー
タ化と照合しているが、別の例につき説明する。この例
では、第２図の集積回路パターンρの規則領域列のうち
の一定の単位領域２５を、検証用設計データｎで照合検
証してから、この検証済みの形成された単位領域δのパ
ターンを利用して他の同等の形成された単位領域を検証
するのに用いる。In the embodiment described above, all of the rule areas are compared with the design data for verification, but another example will be explained. In this example, a certain unit area 25 of the regular area sequence of the integrated circuit pattern ρ shown in FIG. is used to verify other equivalent formed unit areas.
以上説明したように、本発明では、集積回路パターンの
うち、部分的にパターンの繰返しになっている規則領域
を選択し、この領域の検証は、繰返しの単位となる領域
についての設計データを検証用設計データに用いる。す
なわち規則領域の全体についての設計データは検証に用
いないで、上記単位領域の検証用設計デーータを繰返し
、検証用に用いることで規則領域の検証を行なう。その
ため、検証用設計データのデータ量は規則領域の割合が
大きくなる程、従来方法に比べて減少できることになる
。１７５〜１／７程度になることが通常であって、デー
タ作成。As explained above, in the present invention, a regular region in which the pattern is partially repeated is selected from the integrated circuit pattern, and verification of this region is performed by verifying design data for the region that is the unit of repetition. Used for design data. That is, the design data for the entire regular area is not used for verification, but the design data for verification of the unit area is repeatedly used for verification to verify the regular area. Therefore, the amount of verification design data can be reduced compared to the conventional method as the proportion of the regular area increases. It is normal that it is about 175 to 1/7, and the data is created.
計算機へのデータ人出力、パターン検証等に費やす時間
を大幅に短縮できる。The time spent on manually outputting data to a computer, verifying patterns, etc. can be significantly reduced.
なお、規則領域の検証に用いる検証用設計データは、最
小繰返し単位領域であれば最も時間節約になるが、事情
によっては、ある程度大きい単位領域でもよい。また設
計データで検証した、単位領域の形成パターンを照合用
に用いるようにすることもできる。It should be noted that the verification design data used for verifying the regular area will save the most time if it is the minimum repeating unit area, but depending on the circumstances, it may be a somewhat larger unit area. Further, it is also possible to use the formation pattern of the unit area, which has been verified using design data, for verification.
第１図は、本発明の一実施例の検証用設計データ、第２
図はマスク基板上に形成された集積回路パターン、第３
図、第４図は従来例による検証用設計データ、集積回路
パターンである。
１１・・・（不規則領域）検証用設計データ、稔・・・
（規則領域）検証用設計データ、２１・・・マスク基板
、
ｎ・・・集積回路パターン、
る・・・不規則領域、 冴・・・規則領域、５・・・
単位領域。
第１図
（ａ）
第２図
第３図
第４因FIG. 1 shows design data for verification of an embodiment of the present invention;
The figure shows the integrated circuit pattern formed on the mask substrate, the third
4 shows design data for verification and an integrated circuit pattern according to a conventional example. 11...(Irregular area) Verification design data, Minoru...
(Regular area) Verification design data, 21...Mask substrate, n...Integrated circuit pattern, Ru...Irregular area, Sae...Regular area, 5...
unit area. Figure 1 (a) Figure 2 Figure 3 Factor 4
Claims (1)
回路パターンを、該集積回路パターンの検証用設計デー
タと照合することによりパターン検証を行なう方法にお
いて、 集積回路パターン内に単位領域が連続的に配列してなる
規則的な部分領域（規則領域）を選択し、前記単位領域
の検証用設計データ、もしくは前記単位領域の検証用設
計データによつて検証した１の単位領域の形成パターン
を、前記規則領域の形成パターンの各単位領域の照合に
繰返し利用することを特徴とするパターン検証方法。[Claims] A method for performing pattern verification by comparing an integrated circuit pattern formed on a semiconductor wafer or a mask substrate with design data for verification of the integrated circuit pattern, comprising: a unit area in the integrated circuit pattern; A formation pattern of one unit area that is verified by selecting regular partial areas (regular areas) arranged continuously and using the verification design data of the unit area or the verification design data of the unit area. is repeatedly used to verify each unit area of the pattern forming the regular area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62094413A JPS63260147A (en) | 1987-04-17 | 1987-04-17 | Method of verifying pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62094413A JPS63260147A (en) | 1987-04-17 | 1987-04-17 | Method of verifying pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63260147A true JPS63260147A (en) | 1988-10-27 |
Family
ID=14109554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62094413A Pending JPS63260147A (en) | 1987-04-17 | 1987-04-17 | Method of verifying pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63260147A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08339074A (en) * | 1995-03-22 | 1996-12-24 | Hyundai Electron Ind Co Ltd | Manufacture of exposure mask |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57207335A (en) * | 1981-06-15 | 1982-12-20 | Fujitsu Ltd | Pattern checking system |
-
1987
- 1987-04-17 JP JP62094413A patent/JPS63260147A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57207335A (en) * | 1981-06-15 | 1982-12-20 | Fujitsu Ltd | Pattern checking system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08339074A (en) * | 1995-03-22 | 1996-12-24 | Hyundai Electron Ind Co Ltd | Manufacture of exposure mask |
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