JPS63260057A - Resin sealed type semiconductor device - Google Patents
Resin sealed type semiconductor deviceInfo
- Publication number
- JPS63260057A JPS63260057A JP62094373A JP9437387A JPS63260057A JP S63260057 A JPS63260057 A JP S63260057A JP 62094373 A JP62094373 A JP 62094373A JP 9437387 A JP9437387 A JP 9437387A JP S63260057 A JPS63260057 A JP S63260057A
- Authority
- JP
- Japan
- Prior art keywords
- lattice
- cracks
- resin
- thin plate
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 229920005989 resin Polymers 0.000 title claims abstract description 16
- 239000011347 resin Substances 0.000 title claims abstract description 16
- 239000003822 epoxy resin Substances 0.000 abstract description 7
- 229920000647 polyepoxide Polymers 0.000 abstract description 7
- 239000011521 glass Substances 0.000 abstract description 4
- 239000000835 fiber Substances 0.000 abstract description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052709 silver Inorganic materials 0.000 abstract description 2
- 239000004332 silver Substances 0.000 abstract description 2
- 239000010409 thin film Substances 0.000 abstract description 2
- 239000003566 sealing material Substances 0.000 abstract 1
- 238000007789 sealing Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体素子を樹脂封止してなる樹脂封止型半導
体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin-sealed semiconductor device in which a semiconductor element is sealed with a resin.
従来の樹脂封止型半導体装置は、第３図（ａ）。 A conventional resin-sealed semiconductor device is shown in FIG. 3(a).
（ｂ）に示すように、半導体素子１をリードフレームの
半導体素子搭載台部２に金ペーストまたはＡ ｕ −Ｓ
ｉ共晶合金等により固着し、金線３等により半導体素
子の電極４と外部へ導出するリード５とをボンディング
した後、エポキシ樹脂（６）等により封止した構造を有
していた。As shown in (b), the semiconductor element 1 is mounted on the semiconductor element mounting base 2 of the lead frame using gold paste or Au-S.
It had a structure in which the electrodes 4 of the semiconductor element were fixed with an i-eutectic alloy, etc., and the electrodes 4 of the semiconductor element and the leads 5 leading to the outside were bonded with gold wires 3, etc., and then sealed with an epoxy resin (6) or the like.
上述した従来の樹脂封止型半導体装置は、特にＳＯＰ
（スモール・アウトライン・パッケージ（Ｓｍａｌｌ
０ｕｔｌｉｎｅ Ｐａｃｋａｇｅ））等の小型パッ
ケージの場合、プリント基板実装時に赤外線リフローソ
ルダリングやｖｐｓ （ベイパー・′フェース・ソルダ
リング（ＶａｐｏｒＰｈａｓｅ Ｓｏｌｄｅｒｉｎｇ
））等のパッケージ全体が高温に加熱される実装方法を
用いると、パッケージの内部から外部迄クラックが入り
、ひいては、半導体装置の耐湿性が劣化し、不良を発生
するという問題点がある。The conventional resin-sealed semiconductor device described above is particularly suitable for SOP
(Small Outline Package
In the case of small packages such as 0utline Package), infrared reflow soldering or VPS (Vapor Phase Soldering) is used when mounting printed circuit boards.
If a mounting method such as )) is used in which the entire package is heated to a high temperature, cracks will occur from the inside of the package to the outside, which will eventually deteriorate the moisture resistance of the semiconductor device and cause defects.
本発明の樹脂封止型半導体装置は、半導体素子搭載台部
の下面または上面から下方の樹脂部にかけて、格子状の
網目を有する薄板を設けてなるというものである。The resin-sealed semiconductor device of the present invention includes a thin plate having a lattice-like mesh extending from the lower surface or upper surface of the semiconductor element mounting base to the lower resin portion.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）、（ｂ）はそれぞれ本発明の第１の実施例
の平面図及び断面図である。半導体素子１は、厚さ５μ
ｍ〜６０μｍ程度のガラスエポキシ樹脂繊維からなる格
子状網目薄板（エポキシ樹脂繊維が含浸されたガラスク
ロスシート）７で被われた台部２に銀ペーストにより固
着されている。格子状網目薄板７は台部２より下方に１
００μｍ〜５００μｍ程度（台部下方樹脂厚の約３分１
から２分１）、ワイヤボンディング後にたれ下がるよう
になっている。その後、エポキシ樹脂からなる樹脂封止
体６により封止される。プリント基板実装時に発生する
樹脂クラックは、台部２端而より発生するものが多いた
め、本実施例のように台部２端面を格子状網目薄板７で
被うことにより応力の集中、従ってクラック発生を緩和
し、あるいはクラック発生を台部７と格子状網目薄板７
の間でのみに限定することができる。FIGS. 1(a) and 1(b) are a plan view and a sectional view, respectively, of a first embodiment of the present invention. The semiconductor element 1 has a thickness of 5μ
It is fixed with silver paste to a base part 2 covered with a lattice-like mesh thin plate (glass cloth sheet impregnated with epoxy resin fibers) 7 made of glass epoxy resin fibers with a diameter of about m to 60 μm. The lattice mesh thin plate 7 is located below the base part 2.
Approximately 00μm to 500μm (approximately 1/3 of the resin thickness below the stand)
2 minutes 1), it begins to sag after wire bonding. Thereafter, it is sealed with a resin sealing body 6 made of epoxy resin. Most of the resin cracks that occur when mounting a printed circuit board occur at the end of the base 2, so by covering the end face of the base 2 with the lattice mesh thin plate 7 as in this embodiment, stress concentration and therefore cracks can be prevented. The base part 7 and the lattice mesh thin plate 7 can reduce the occurrence of cracks or prevent the occurrence of cracks.
It can be limited only between.
第２図（ａ）、（ｂ）は、それぞれ本発明の第２の実施
例の平面図及び断面図である。格子状網目薄板７は、有
機性接着剤により半導体素子搭載台部の下面に固着され
、下方に１００μｍ〜５００μｍ程度（台部下方樹脂厚
の約３分の１から２分の１）たれ下がるようになってい
る。この実施例では、プリント基板実装時に発生する樹
脂クラックとほぼ同じ方向に格子状網目薄板７が形成さ
れるため、クラックが発生した場合でも格子内部でのマ
イクロクラックが優先的に発生し、パッケージ外部迄ク
ラックが到達せず、外部からの水分の侵入を有効に防止
する事ができる。FIGS. 2(a) and 2(b) are a plan view and a sectional view, respectively, of a second embodiment of the present invention. The lattice mesh thin plate 7 is fixed to the lower surface of the semiconductor element mounting base using an organic adhesive, and hangs downward by approximately 100 μm to 500 μm (approximately 1/3 to 1/2 of the resin thickness below the base). It has become. In this embodiment, the lattice mesh thin plate 7 is formed in almost the same direction as the resin cracks that occur when mounting the printed circuit board, so even if cracks occur, microcracks occur preferentially inside the lattice, and the outside of the package Cracks do not reach the surface until the cracks reach the surface, effectively preventing moisture from entering from the outside.
以上説明したように本発明は、半導体素子搭載部の下面
または上面から下方の樹脂部にかけて、格子状の網目を
有する薄膜を設けたことより、プリント基板実装時に発
生するクラックをこの格子部分に限定し、外部へのクラ
ックの進行を阻むことにより樹脂のクラックを防止でき
るので樹脂封止型半導体装置の歩留り及び信頼性の劣化
による不良発生を低減し、歩留り及び信頼性を改善でき
る効果がある。As explained above, the present invention provides a thin film having a lattice-like mesh from the lower or upper surface of the semiconductor element mounting part to the lower resin part, thereby limiting cracks that occur during printed circuit board mounting to this lattice part. However, since cracks in the resin can be prevented by inhibiting the propagation of cracks to the outside, it is possible to reduce the occurrence of defects due to deterioration in yield and reliability of resin-sealed semiconductor devices, and to improve yield and reliability.
なお、便宜上、平面図において樹脂封止体６内のものを
表わすのに実線を用い、断面図において、半導体素子１
．半導体素子搭載台部２．リードらの切欠部に斜線は施
していない。For convenience, solid lines are used to represent the inside of the resin sealing body 6 in the plan view, and solid lines are used to represent the inside of the semiconductor element 1 in the cross-sectional view.
．． Semiconductor element mounting base 2. There are no diagonal lines in the cutout portion of the leads.
又、格子状網目薄板はガラスエポキシ樹脂Ｓａ＃！Ｉｉ
に限らず、金属メツシュでもよく、要は、半導体素子搭
載台部の端部又はエツジに応力が集中するのを避けて、
網目薄板に分散されて歪エネルギーを開放すればよいの
である。In addition, the lattice mesh thin plate is made of glass epoxy resin Sa#! Ii
It is not limited to this, but metal mesh may also be used.The key is to avoid concentration of stress on the ends or edges of the semiconductor element mounting base.
All it has to do is release the strain energy by dispersing it in the mesh thin plate.
第１図（ａ）は本発明の第１の実施例の平面図、第１図
（ｂ）は第１図（ａ）のｘ−ｘ’線断面図、第２図（ａ
）は本発明の第２の実施例２の平面図、第２図（ｂ）は
第２図（ａ）のｘ−ｘ’線断面図、第３図（ａ）は従来
の例の平面図、第３図（ｂ）は第３図（ａ）のｘ−ｘ’
線断面図である。
１・・・半導体素子、２・・・半導体素子搭載台部、３
・・・ボンディングワイヤ、４・・・半導体素子電極、
５・・・リード、６・・・樹脂封止体、７・・・格子状
網目薄板。FIG. 1(a) is a plan view of the first embodiment of the present invention, FIG. 1(b) is a sectional view taken along line xx' in FIG. 1(a), and FIG.
) is a plan view of the second embodiment of the present invention, FIG. 2(b) is a sectional view taken along line xx' in FIG. 2(a), and FIG. 3(a) is a plan view of the conventional example. , FIG. 3(b) is xx' in FIG. 3(a)
FIG. 1... Semiconductor element, 2... Semiconductor element mounting base, 3
...Bonding wire, 4...Semiconductor element electrode,
5... Lead, 6... Resin sealing body, 7... Grid-like mesh thin plate.
Claims (1)
部にかけて、格子状の網目を有する薄板を設けてなるこ
とを特徴とする樹脂封止型半導体装置。1. A resin-sealed semiconductor device comprising a thin plate having a lattice-like mesh extending from the lower or upper surface of a semiconductor element mounting base to a lower resin portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62094373A JPS63260057A (en) | 1987-04-16 | 1987-04-16 | Resin sealed type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62094373A JPS63260057A (en) | 1987-04-16 | 1987-04-16 | Resin sealed type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63260057A true JPS63260057A (en) | 1988-10-27 |
Family
ID=14108512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62094373A Pending JPS63260057A (en) | 1987-04-16 | 1987-04-16 | Resin sealed type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63260057A (en) |
-
1987
- 1987-04-16 JP JP62094373A patent/JPS63260057A/en active Pending
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