JPS6325766Y2 - - Google Patents
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- Publication number
- JPS6325766Y2 JPS6325766Y2 JP3862380U JP3862380U JPS6325766Y2 JP S6325766 Y2 JPS6325766 Y2 JP S6325766Y2 JP 3862380 U JP3862380 U JP 3862380U JP 3862380 U JP3862380 U JP 3862380U JP S6325766 Y2 JPS6325766 Y2 JP S6325766Y2
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- JP
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- Prior art keywords
- amplifier
- current
- positive
- ground point
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 230000003321 amplification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
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- Amplifiers (AREA)
Description
【考案の詳細な説明】
この考案は、正負電源電圧の供給を受けて動作
する増幅回路において、電源電流を一定化して音
質の向上を計つた増幅回路に関する。[Detailed Description of the Invention] This invention relates to an amplification circuit that operates on the supply of positive and negative power supply voltages and improves sound quality by making the power supply current constant.
従来一般のオーデイオシステム等に用いられる
増幅回路においては、負荷に流れる電流に応じて
電源回路の電流値が変化し、これに伴い電源イン
ピーダンスに応じて電源電圧の変動を招来し、こ
の電源電圧の変動に起因して歪率特性の悪化をも
たらす問題があつた。 Conventionally, in amplifier circuits used in general audio systems, etc., the current value of the power supply circuit changes according to the current flowing through the load, which causes fluctuations in the power supply voltage according to the power supply impedance, and the power supply voltage There was a problem in which distortion characteristics deteriorated due to fluctuations.
そこで近年になつて、上述した問題を解決する
方法として、負荷に流れる信号電流の如何に関わ
らず、電源回路に流れる電流を一定化した増幅回
路が注目されている。 Therefore, in recent years, as a method for solving the above-mentioned problems, an amplifier circuit that makes the current flowing through the power supply circuit constant regardless of the signal current flowing through the load has been attracting attention.
第１図は、この種の増幅回路の１例を示すもの
である。この増幅回路は、入力端子１ａ，１ｂ間
に印加された入力信号に応じて出力端子２ａ，２
ｂ間に介挿された負荷３を駆動する増幅器４と、
この増幅器４に定電流回路５ａ，５ｂを経由して
電源電圧を供給する正負電源６ａ，６ｂと、前記
増幅器４と定電流回路５ａ，５ｂとの接続点７
ａ，７ｂと前記出力端子２ｂとの間に各々介挿さ
れた定電圧回路８ａ，８ｂとからなるもので、正
負電源６ａ，６ｂが各々定電流回路５ａ，５ｂを
経由して各々定電圧回路８ａ，８ｂおよび増幅器
４に一定電流を供給し、増幅器４から負荷３に流
れる電流を定電圧回路８ａ，８ｂによつて吸収す
るようにしたものである。 FIG. 1 shows an example of this type of amplifier circuit. This amplifier circuit has output terminals 2a and 2 according to an input signal applied between input terminals 1a and 1b.
an amplifier 4 that drives a load 3 inserted between b;
Positive and negative power supplies 6a and 6b supplying power supply voltage to this amplifier 4 via constant current circuits 5a and 5b, and a connection point 7 between the amplifier 4 and constant current circuits 5a and 5b.
It consists of constant voltage circuits 8a and 8b inserted between the output terminals a and 7b and the output terminal 2b, respectively, and the positive and negative power supplies 6a and 6b are connected to the constant voltage circuits through constant current circuits 5a and 5b, respectively. A constant current is supplied to 8a, 8b and the amplifier 4, and the current flowing from the amplifier 4 to the load 3 is absorbed by the constant voltage circuits 8a, 8b.
ところで、この増幅回路においては、大電流を
流し得る定電流回路５ａ，５ｂおよび定電圧回路
８ａ，８ｂを構成することが困難であり、また正
負電源６ａ，６ｂの接続点６ｃと出力端子２ｂ間
（接地線）には、定電流回路５ａ，５ｂの設定電
流i1a，i1bの不揃に起因する電流（i1a−i1b）と、
定電圧回路８ａ，８ｂに負荷３に流れる電流を吸
収し得なかつた電流i2が流れる。この場合定電流
回路５ａ，５ｂの設定電流の不揃に起因する電流
（i1a−i1b）は、接地線のインピーダンスに応じ
てこの接地線と任意設定し得る接地点とに所定の
電位を生じ、この増幅回路を他の回路と切換接続
する際に両回路の接地電位の差に基づいて不快音
を生ずる等の問題を有していた。また定電圧回路
８ａ，８ｂによつて吸収し得なかつた電流i2は、
接地線の接地点を経由して入力端子１ｂ側に回り
込み、これによつてクロストーク等の歪が発生し
て増幅回路の性能および音質の劣化を招来する問
題を有していた。更に定電流回路５ａ，５ｂが増
幅器４と正負電源６ａ，６ｂとの間に各々介挿さ
れていることから、電源電圧利用効率が低下し、
この増幅器４の最大出力等が下がつてしまう欠点
があつた。 By the way, in this amplifier circuit, it is difficult to configure constant current circuits 5a, 5b and constant voltage circuits 8a, 8b that can flow large currents, and it is difficult to configure constant current circuits 5a, 5b and constant voltage circuits 8a, 8b that can flow large currents. (Grounding wire) contains a current (i 1 a - i 1 b) due to the unevenness of the set currents i 1 a, i 1 b of the constant current circuits 5a, 5b,
A current i 2 that cannot absorb the current flowing through the load 3 flows through the constant voltage circuits 8a and 8b. In this case, the current (i 1 a - i 1 b) caused by the unevenness of the set currents of the constant current circuits 5a and 5b is distributed between the ground wire and a grounding point that can be arbitrarily set according to the impedance of the ground wire. When this amplifier circuit is switched and connected to another circuit, an unpleasant sound is generated due to the difference in ground potential between the two circuits. In addition, the current i 2 that could not be absorbed by the constant voltage circuits 8a and 8b is
There is a problem in that the noise goes around to the input terminal 1b side via the grounding point of the grounding wire, thereby causing distortion such as crosstalk, resulting in deterioration of the performance of the amplifier circuit and the sound quality. Furthermore, since the constant current circuits 5a and 5b are interposed between the amplifier 4 and the positive and negative power supplies 6a and 6b, the power supply voltage usage efficiency decreases.
There was a drawback that the maximum output of the amplifier 4 was lowered.
この考案は上記事情に鑑み、簡単な回路構成で
電源インピーダンスおよび接地線のインピーダン
スに起因する諸問題を解決した増幅回路を提供す
るもので、入力端子と仮想接地点との間に印加さ
れる入力信号に応じてその出力端子と仮想接地点
との間に介装された負荷を駆動する第１の増幅器
と、この第１の増幅器に正負電源電圧を供給する
少なくとも１組の正負電源と、この正負電源から
正負電源電圧の供給を受け当該正負電源の接地点
に正入力端が接続され負入力端および出力端が前
記第１の増幅器の前記仮想接地点に接続されてな
る第２の増幅器とを具備してなることを特徴とす
る。 In view of the above circumstances, this invention provides an amplifier circuit that solves various problems caused by power supply impedance and grounding wire impedance with a simple circuit configuration. a first amplifier that drives a load interposed between its output terminal and a virtual ground point according to a signal; at least one set of positive and negative power supplies that supply positive and negative power supply voltages to the first amplifier; a second amplifier that receives positive and negative power supply voltages from a positive and negative power source, has a positive input terminal connected to a ground point of the positive and negative power source, and has a negative input terminal and an output terminal connected to the virtual ground point of the first amplifier; It is characterized by comprising the following.
以下、この考案の実施例を図面を参照して説明
する。 Hereinafter, embodiments of this invention will be described with reference to the drawings.
第２図は、この考案による増幅回路の一実施例
の構成を示す回路図である。 FIG. 2 is a circuit diagram showing the configuration of one embodiment of the amplifier circuit according to this invention.
この図に示す増幅回路は、入力端子１１ａ，１
１ｂ間に印加された入力信号が第１の増幅器１２
によつて電力増幅された後、この出力が出力端子
１３と仮想接地点１４との間に介挿された負荷１
５に供給される。一方、この第１の増幅器１２に
電源電圧を供給する正負電源１６ａ，１６ｂが設
けられており、またこれら正負電源１６ａ，１６
ｂから前記第１の増幅器１２の電源側の接続点１
７ａ，１７ｂを経由して電源電圧の供給を受ける
第２の増幅器１８が設けられている。この第２の
増幅器１８は、入力端１９に正負電源１６ａ，１
６ｂの接地点１６ｃの電位が印加され、仮想接地
点１４に接続された出力端側より負荷１５に流れ
る電流を吸収しながら仮想接地点１４の電位を略
零とするように動作するものである。また入力端
子１１ｂが仮想接地点１４と接続されている。な
おこの実施例において、第１、第２の増幅器１
２，１８のアイドル電流、I1，I2は、これらの増
幅器がＡ級動作するように設定されるものとす
る。更に第２の増幅器１８のアイドル電流I2が第
１の増幅器１２のアイドル電流I1より高目に設定
されるものとする。 The amplifier circuit shown in this figure has input terminals 11a, 1
The input signal applied between 1b and 1b is transmitted to the first amplifier 12.
After the power is amplified by the output terminal 13 and the virtual ground point 14, the output is amplified by the load 1 inserted between the output terminal 13 and the virtual ground point 14.
5. On the other hand, positive and negative power supplies 16a and 16b are provided to supply power supply voltage to the first amplifier 12, and these positive and negative power supplies 16a and 16
b to connection point 1 on the power supply side of the first amplifier 12
A second amplifier 18 is provided which receives power supply voltage via 7a and 17b. This second amplifier 18 has positive and negative power supplies 16a, 1 at the input end 19.
6b is applied, and operates to reduce the potential of the virtual ground point 14 to approximately zero while absorbing the current flowing to the load 15 from the output end side connected to the virtual ground point 14. . Further, the input terminal 11b is connected to the virtual ground point 14. Note that in this embodiment, the first and second amplifiers 1
It is assumed that the idle currents I 1 and I 2 of 2 and 18 are set so that these amplifiers operate in class A mode. Furthermore, it is assumed that the idle current I 2 of the second amplifier 18 is set higher than the idle current I 1 of the first amplifier 12.
次に、この増幅回路の動作について説明する。 Next, the operation of this amplifier circuit will be explained.
まず、入力端子１１ａ，１１ｂ間に印加される
入力信号が零の場合には出力端子１３と仮想接地
点１４との間の電位差（すなわち出力信号）が零
となり負荷１５に電流が流れない。すなわち第１
の増幅器１２には接地点１７ａ側および接地点１
７ｂ側のいずれの側でもI1なるアイドル電流が供
給され、また第２の増幅器１８には接地点１７ａ
側および接地点１７ｂ側のいずれの側でもI2なる
アイドル電流が供給される。この場合、第１、第
２の増幅器１２，１８に供給される電流の和は、
I1＋I2となり、一定となる。 First, when the input signal applied between the input terminals 11a and 11b is zero, the potential difference (that is, the output signal) between the output terminal 13 and the virtual ground point 14 becomes zero, and no current flows to the load 15. That is, the first
The amplifier 12 has a ground point 17a side and a ground point 1 side.
An idle current of I 1 is supplied to either side of the 7b side, and the second amplifier 18 is supplied with an idle current of I 1 to the ground point 17a.
An idle current of I 2 is supplied to both the ground point 17b side and the ground point 17b side. In this case, the sum of the currents supplied to the first and second amplifiers 12 and 18 is:
I 1 + I 2 and remains constant.
次に、入力端子１１ａ，１１ｂ間に正の入力信
号が印加された場合には、第１の増幅器１２を経
由して負荷１５にΔIなる電流が流れる。すなわ
ち第１の増幅器１２においては、この増幅器１２
がＡ級動作することから、接続点１７ａ側からI1
＋ΔI／２なる電流が供給され、また接続点１７ｂ側
からI1−ΔI／２なる電流が供給される。一方第２の
増幅器１８は、入力端１９が正負電源１６ａ，１
６ｂの接地点１６ｃと接続されているから、出力
端に接続された仮想接地点１４の電位を略零にす
るようにＡ級動作する。この場合、仮想接地点１
４の電位を零とするということは、負荷１５に流
れる電流ΔIに対して第２の増幅器１８側が−ΔI
の出力電流を供給するということと等価になる。
すなわち、第２の増幅器１８が前記第１の増幅器
１２の出力電流ΔIを過不足なく吸収することが
仮想接地点の電位を安定に保つ条件であり、これ
が満足されて同仮想接地点の電位は安定状態、つ
まり第２の増幅器１８の入力電位である正負電源
１６ａ，１６ｂの接地点１６ｃの電位となるわけ
である。かくして、第２の増幅器１８で電流−
ΔIを供給することとなり、そのためには、接続
点１７ａ側からI2−ΔI／２なる電流が供給され、ま
た接続点１７ｂ側からI2＋ΔI／２なる電流が供給さ
れる。 Next, when a positive input signal is applied between the input terminals 11a and 11b, a current of ΔI flows to the load 15 via the first amplifier 12. That is, in the first amplifier 12, this amplifier 12
Since it operates in class A, I 1 from the connection point 17a side
A current of +ΔI/2 is supplied, and a current of I 1 -ΔI/2 is supplied from the connection point 17b side. On the other hand, the second amplifier 18 has an input terminal 19 connected to the positive and negative power supplies 16a, 1
Since it is connected to the ground point 16c of the output terminal 6b, class A operation is performed so that the potential of the virtual ground point 14 connected to the output end is brought to approximately zero. In this case, virtual ground point 1
4 means that the potential on the second amplifier 18 side is -ΔI with respect to the current ΔI flowing through the load 15.
This is equivalent to supplying an output current of .
That is, the condition for keeping the potential of the virtual ground point stable is that the second amplifier 18 absorbs just the output current ΔI of the first amplifier 12, and when this is satisfied, the potential of the virtual ground point becomes This results in a stable state, that is, the potential at the ground point 16c of the positive and negative power supplies 16a and 16b, which is the input potential of the second amplifier 18. Thus, in the second amplifier 18 the current -
ΔI is to be supplied, and for this purpose, a current of I 2 −ΔI/2 is supplied from the connection point 17a side, and a current of I 2 +ΔI/2 is supplied from the connection point 17b side.
したがつて、正負電源１６ａ，１６ｂから第１
の増幅器１２および第２の増幅器１８に供給され
る電流の和は、各々両者の増幅器１２，１８のア
イドル電流の和（I1＋I2）となり、一定となる。
なお、上記の説明から明らかなように第２の増幅
器１８の出力電流容量は、第１の増幅器１２の出
力電流容量と同程度であれば理想的であるが、仮
に第２の増幅器１８の出力電流容量が小さくても
その出力電流容量までは充分その所期の効果を奏
するものである。 Therefore, the first
The sum of the currents supplied to the second amplifier 12 and the second amplifier 18 is the sum (I 1 +I 2 ) of the idle currents of the two amplifiers 12 and 18, respectively, and is constant.
As is clear from the above description, it is ideal if the output current capacity of the second amplifier 18 is about the same as the output current capacity of the first amplifier 12. However, if the output current capacity of the second amplifier 18 is Even if the current capacity is small, the desired effect can be sufficiently achieved up to the output current capacity.
また、入力端子１１ａ，１１ｂ間に負の入力信
号が印加された場合にも、上記と同様の作用効果
が得られる。 Further, even when a negative input signal is applied between the input terminals 11a and 11b, the same effect as described above can be obtained.
第３図は、第２図に示す増幅回路の具体的構成
例を示す図であり、この図において、第２図の各
部と対応する部分には同一の符号が付してある。 FIG. 3 is a diagram showing a specific example of the configuration of the amplifier circuit shown in FIG. 2. In this diagram, parts corresponding to those in FIG. 2 are given the same reference numerals.
この図に示す増幅回路は、第１、第２の増幅器
１２，１８を各々演算増幅器と、相補形に構成さ
れた出力段トランジスタとで構成してなるもので
ある。 In the amplifier circuit shown in this figure, the first and second amplifiers 12 and 18 each include an operational amplifier and complementary output stage transistors.
すなわち、第１の増幅器１２は、入力端子１１
ａ，１１ｂ間に印加される入力信号を演算増幅器
２１によつて電圧増幅した後、バイアス電源２２
ａ，２２ｂを介してトランジスタ２３ａ，２３ｂ
の各ベースに印加し、これらトランジスタ２３
ａ，２３ｂによつて電力増幅した出力をトランジ
スタ２３ａ，２３ｂの共通エミツタ側の出力端子
１３から負荷１５に供給するようにしたものであ
る。また演算増幅器２１の非反転入力端と各入力
端子１１ｂ、出力端子１３との間には各々負帰還
用抵抗２４，２５が介挿されており、これにより
第１の増幅器１２が所定の増幅度を得るようにし
たものである。 That is, the first amplifier 12 has an input terminal 11
After voltage amplifying the input signal applied between a and 11b by the operational amplifier 21, the bias power supply 22
Transistors 23a and 23b via a and 22b
are applied to the bases of each of these transistors 23
The output power amplified by transistors 23a and 23b is supplied to a load 15 from an output terminal 13 on the common emitter side of transistors 23a and 23b. Further, negative feedback resistors 24 and 25 are inserted between the non-inverting input terminal of the operational amplifier 21 and each input terminal 11b and output terminal 13, respectively, so that the first amplifier 12 has a predetermined amplification degree. It was designed to obtain the following.
また第２の増幅器１８は、演算増幅器３１の非
反転入力端に正負電源１６ａ，１６ｂの接地点１
６ｃの電位を印加し、その出力をバイアス電源３
２ａ，３２ｂを介して各々トランジスタ３３ａ，
３３ｂの各ベースを印加し、これらトランジスタ
３３ａ，３３ｂの共通エミツタ側より得られた電
圧を前記演算増幅器３１の反転入力端に100％負
帰還するようにしたもので、接地線１６ｃの電位
を基準として、仮想接地点１４の電位を略零にす
るように電流増幅するようにしたものである。 Further, the second amplifier 18 connects the ground point 1 of the positive and negative power supplies 16a and 16b to the non-inverting input terminal of the operational amplifier 31.
6c potential is applied and its output is biased to the bias power supply 3.
Transistors 33a, 2a, 32b respectively.
33b, and the voltage obtained from the common emitter side of these transistors 33a and 33b is 100% negatively fed back to the inverting input terminal of the operational amplifier 31, and the potential of the ground line 16c is referenced. In this case, the current is amplified so that the potential of the virtual ground point 14 becomes approximately zero.
上記の構成からなる増幅回路においては、接地
点１６ｃから演算増幅器３１の非反転入力端に供
給される接地電流が、従来の増幅回路と比べて
100db以下（測定不能）となつた。なお、この回
路においてもバイアス電源２２ａ，２２ｂは、第
１の増幅器１２がＡ級動作するようにその値が設
定され、またバイアス電源３２ａ，３２ｂは第２
の増幅器１８が第１の増幅器１２よりアイドル電
流が多くなるように設定される。この場合、第２
の増幅器１８はＡ級動作する。 In the amplifier circuit having the above configuration, the ground current supplied from the ground point 16c to the non-inverting input terminal of the operational amplifier 31 is higher than that in the conventional amplifier circuit.
It became less than 100db (unmeasurable). In this circuit as well, the values of the bias power supplies 22a and 22b are set so that the first amplifier 12 operates in class A, and the values of the bias power supplies 32a and 32b are set so that the first amplifier 12 performs class A operation.
The second amplifier 18 is set to have a higher idle current than the first amplifier 12. In this case, the second
The amplifier 18 operates in class A mode.
かくして、この増幅回路においても第２図に示
す増幅回路と同様の作用効果が得られる。 In this way, the same effects as the amplifier circuit shown in FIG. 2 can be obtained in this amplifier circuit as well.
なお、以上の実施例では、第１、第２の増幅器
１２，１８をＡ級動作させるものとして説明した
が、要は一方の出力電流の吸収作用が他方に生ず
れば充分であるから基本的には動作級にかかわり
なく、AB級動作、Ｂ級動作のいずれでも同等の
効果を奏するものである。 In the above embodiments, the first and second amplifiers 12 and 18 were explained as being operated in class A mode, but the point is that it is sufficient that the absorption effect of the output current of one occurs in the other. Regardless of the class of motion, both AB class motion and B class motion produce the same effect.
以上説明したように、この考案によれば、入力
端子と仮想接地点との間に印加される入力信号に
応じてその出力端子と仮想接地点との間に介装さ
れた負荷を駆動する第１の増幅器と、この第１の
増幅器に正負電源電圧を供給する少なくとも１組
の正負電源と、この正負電源から正負電源電圧の
供給を受け当該正負電源の接地点に正入力端が接
続され負入力端および出力端が前記第１の増幅器
の前記仮想接地点に接続されてなる第２の増幅器
とを具備したので、簡単な回路構成で電源電圧利
用効率の低下を防止することができ、電源回路に
用いられるダイオード等の非線形素子による電源
電圧の変動を防止することができ、電源インピー
ダンスおよび接地線のインピーダンスに起因する
諸問題を解決する効果が得られる。 As explained above, according to this invention, the load interposed between the output terminal and the virtual ground point is driven according to the input signal applied between the input terminal and the virtual ground point. 1 amplifier, at least one set of positive and negative power supplies that supply positive and negative power supply voltages to the first amplifier; Since the second amplifier is provided with an input end and an output end connected to the virtual ground point of the first amplifier, it is possible to prevent the power supply voltage usage efficiency from decreasing with a simple circuit configuration, and the power supply It is possible to prevent fluctuations in the power supply voltage due to nonlinear elements such as diodes used in the circuit, and it is possible to obtain the effect of solving various problems caused by the impedance of the power supply and the ground line.
第１図は従来の増幅回路の一例を示す回路図、
第２図はこの考案による増幅回路の一実施例の構
成を示す回路図第３図は第２図に示す増幅回路の
具体的構成を示す回路図である。
１２……第１の増幅器、１３……出力端子、１
４……仮想接地点、１５……負荷、１６ａ，１６
ｂ……正負電源、１６ｃ……接地点、１８……第
２の増幅器。
Figure 1 is a circuit diagram showing an example of a conventional amplifier circuit.
FIG. 2 is a circuit diagram showing the configuration of an embodiment of the amplifier circuit according to this invention. FIG. 3 is a circuit diagram showing a specific configuration of the amplifier circuit shown in FIG. 2. 12...First amplifier, 13...Output terminal, 1
4...Virtual ground point, 15...Load, 16a, 16
b... Positive and negative power supplies, 16c... Grounding point, 18... Second amplifier.
Claims (1)
信号に応じてその出力端子と仮想接地点との間に
介装された負荷を駆動する第１の増幅器と、この
第１の増幅器に正負電源電圧を供給する少なくと
も１組の正負電源と、この正負電源から正負電源
電圧の供給を受け当該正負電源の接地点に正入力
端が接続され負入力端および出力端が前記第１の
増幅器の前記仮想接地点に接続されてなる第２の
増幅器とを具備してなることを特徴とする増幅回
路。 a first amplifier that drives a load interposed between the output terminal and the virtual ground point according to an input signal applied between the input terminal and the virtual ground point; At least one set of positive and negative power supplies supplying power supply voltages, the positive input terminal is connected to the grounding point of the positive and negative power supplies, and the positive input terminal is connected to the ground point of the positive and negative power supplies, and the negative input terminal and the output terminal are connected to the first amplifier. and a second amplifier connected to the virtual ground point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3862380U JPS6325766Y2 (en) | 1980-03-24 | 1980-03-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3862380U JPS6325766Y2 (en) | 1980-03-24 | 1980-03-24 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56140216U JPS56140216U (en) | 1981-10-23 |
| JPS6325766Y2 true JPS6325766Y2 (en) | 1988-07-13 |
Family
ID=29634121
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3862380U Expired JPS6325766Y2 (en) | 1980-03-24 | 1980-03-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6325766Y2 (en) |
-
1980
- 1980-03-24 JP JP3862380U patent/JPS6325766Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56140216U (en) | 1981-10-23 |
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