JPS6324408A - Power-on resetting circuit - Google Patents
Power-on resetting circuitInfo
- Publication number
- JPS6324408A JPS6324408A JP61168530A JP16853086A JPS6324408A JP S6324408 A JPS6324408 A JP S6324408A JP 61168530 A JP61168530 A JP 61168530A JP 16853086 A JP16853086 A JP 16853086A JP S6324408 A JPS6324408 A JP S6324408A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- condition
- microprocessor
- impressing
- applied voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 10
- 238000007493 shaping process Methods 0.000 claims abstract description 9
- 238000007599 discharging Methods 0.000 claims abstract description 6
- 238000012544 monitoring process Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000000630 rising effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
C概要〕
パワーオンリセット回路において、マイクロプロセッサ
の印加電圧が設定電圧■1以下になった時に強制的にこ
のマイクロプロセッサのリセット端子をLの状態にし、
前記の印加電圧が立上った時には引き続き所定時間、L
の状態を保持させた後にHの状態に変化させ、この印加
電圧に瞬断があってもマイクロプロセッサの暴走の可能
性を少なくする様にしたものである。[Detailed Description of the Invention] C Summary] In a power-on reset circuit, when the voltage applied to the microprocessor becomes less than the set voltage ■1, the reset terminal of the microprocessor is forcibly set to the L state,
When the applied voltage rises, L continues for a predetermined period of time.
After the state is maintained, it is changed to the H state to reduce the possibility of the microprocessor running out of control even if there is a momentary interruption in the applied voltage.
本発明はパワーオンリセット回路、特にマイクロプロセ
ッサに電圧を印加した際にマイクロプロセッサのリセッ
ト端子を所定時間、Lの状態にするパワーオンリセット
回路の改良に関するものである。The present invention relates to an improvement in a power-on reset circuit, and particularly to a power-on reset circuit that keeps a reset terminal of a microprocessor in an L state for a predetermined period of time when a voltage is applied to the microprocessor.
近年、装置の小型化、経済化、高機能化に伴い種々の装
置にマイクロプロセッサが用いられているが、これを正
常に動作させるには電圧を印加した際にパワーオンリセ
ット回路を用いてリセット端子を所定時間、Lの状態に
しなければならないが、印加電圧が瞬断して立上る際に
もリセット端子を上記と同じ状態にして暴走の可能性を
少なくすることが必要である。In recent years, microprocessors have been used in various devices as devices have become smaller, more economical, and more sophisticated.In order for these devices to operate properly, they must be reset using a power-on reset circuit when voltage is applied. Although the terminal must be in the L state for a predetermined period of time, it is necessary to reduce the possibility of runaway by keeping the reset terminal in the same state as above even when the applied voltage is momentarily cut off and then rising.
第4図は従来例のブロック図、第5図は第4図のタイム
チャー1・を示す。以下、マイクロプロセッサば8ピノ
I・とじて第5図を参照して第4図の動作を説明する。FIG. 4 is a block diagram of a conventional example, and FIG. 5 shows a time chart 1 of FIG. Hereinafter, the operation of FIG. 4 will be explained with reference to FIG. 5, including the microprocessor.
尚、L及びHの状態とは’r ’l’ L レベル(例
えば、しは0.8v以下、11は4■以上)で規定され
るレベルである。Note that the L and H states are levels defined by the 'r'l' L level (for example, HI is 0.8V or less, 11 is 4■ or more).
先ず、第5図−〇に示す(美にパワーオンリセット回路
1の端子に印加電圧V(例えば、5■)が時間T1だけ
印加されたとすると、抵抗1iSRとコンデンサCとで
構成された積分R112を通ることにより積分されて第
5図−■に示す様に緩い立上り。First, as shown in FIG. As shown in Figure 5-■, it is integrated by passing through the curve and shows a gradual rise.
立下り部分を持つ波形が得られ、これをC−MO5型ト
ランジスタで構成された波形整形器11に通すと゛しき
い値“Vい以上の入力レベルはl[に、以下はLになっ
て第5図−〇のni?半に示す様に立上り点が第5図−
〇の波形の立上り点よりも所定時間T、遅延した波形が
マイクロプロセッサのリセット端子に加えられる。A waveform with a falling part is obtained, and when this is passed through the waveform shaper 11 composed of C-MO5 type transistors, the input level above the "threshold value" V becomes L[, and below it becomes L]. Figure 5- As shown in the ni? half of 〇, the rising point is Figure 5-
A waveform that is delayed by a predetermined time T from the rising point of the waveform marked 〇 is applied to the reset terminal of the microprocessor.
ここで、上記の様に所定時間T、遅延させる理由は下記
の様である。Here, the reason for delaying the predetermined time T as described above is as follows.
マイクロプロセッサ2が正常に動作する為にはこの中の
プログラムカウンタ(図示せず)に例えばF F li
Li及びFFFFがロードされる。そこで、この番地
に飛ぶと、ここには例えばROM (図示せず)内のプ
ログラムされた命令があるので、マイクロプロセッサは
その命令を読んで初期状態にした後、制御命令に従って
装置の制御が正しく行われる。In order for the microprocessor 2 to operate normally, a program counter (not shown) therein must be programmed with, for example, F F li
Li and FFFF are loaded. Therefore, when jumping to this address, there is a programmed instruction in, for example, a ROM (not shown), so the microprocessor reads that instruction and sets it to the initial state, and then correctly controls the device according to the control instruction. It will be done.
即ち、プログラムカウンタにFFFE及びF F l’
)iがロードされないとマイクロプロセッサは動作し
ないが、これをロードする為に所定時間1゛、リセット
端子をLの状態にする必要がある。That is, FFFE and F F l' are stored in the program counter.
) If i is not loaded, the microprocessor will not operate, but in order to load it, it is necessary to keep the reset terminal in the L state for a predetermined time of 1.
しかし、第5図−〇の後半に示す様に印加電圧にCRの
時定数よりも短い瞬断が発生すると、積分器の出力は第
5図−■の後半に示す様に凹むが、この凹みは波形整形
器の“しきい値”VLhより高いのでリセット端子は1
1の状態を保持する。However, if an instantaneous interruption occurs in the applied voltage that is shorter than the CR time constant as shown in the second half of Figure 5-○, the output of the integrator will be depressed as shown in the second half of Figure 5-■. is higher than the “threshold value” VLh of the waveform shaper, so the reset terminal is set to 1.
The state of 1 is maintained.
一方、印加電圧が瞬断したのでマイクロプロセッサ・内
部のプログラムカウンタやRAM (図示せず)の状態
が不定になるが、リセット端子がLの状態にならないの
でマイクU、!プロセッサはリセット動11ができず、
プログラム通りの正常動作が不可能となり所謂、暴走す
るが、これを正常動作させるには人手によってマイクロ
プロセッサの印加電圧を一度断にして、リセット端子を
所定時間りの状態にしなければならない。On the other hand, due to a momentary interruption of the applied voltage, the states of the microprocessor, internal program counter, and RAM (not shown) become unstable, but the reset terminal does not go into the L state, so the microphone U! The processor cannot perform the reset operation 11,
Normal operation according to the program becomes impossible and a so-called runaway occurs, but in order to restore normal operation, the voltage applied to the microprocessor must be manually cut off once and the reset terminal must be kept in a state for a predetermined period of time.
即ち、印加電圧が瞬断した際にはマイクロブロセ、す・
は暴走する可能性が高いと云う問題点がある。In other words, when the applied voltage is interrupted momentarily, the microblossom
The problem is that there is a high possibility that it will go out of control.
上記の問題点は第1図に示す様に、印加電圧■が設定電
圧■1以上か以下かを監視する印加電圧監視手段3と、
該印Jjll電圧を積分する積分手段12と、該積分手
段の出力を波形整形した後にマ・イクロブロセノサ2に
加える波形整形手段■1と、該印加電圧が設定電圧以下
の時に該積分手段を構成するコンテンツCに貯えられた
電荷を強制的にJil、電させる放電手段4とから構成
された本発明のパワーオンリモノ1−回路により解決さ
れる。The above problem, as shown in FIG.
An integrating means 12 that integrates the Jjll voltage, a waveform shaping means (1) which applies waveform shaping to the output of the integrating means and then applies it to the microprocessor 2, and the integrating means when the applied voltage is below a set voltage. This problem is solved by the power-only mono 1-circuit of the present invention, which is constituted by a discharging means 4 for forcibly discharging the charge stored in the content C.
本発明は、積分手段L2のコンデンサCの電荷を急速に
放電することにより、印加電圧に瞬断が発生した際にも
リセット端子がLの状1虚になる礒にして暴走の可能性
を少なくした。即ち、印加電圧監視手段3で印加電圧V
が設定電圧V1以上か以下かを監視し、印加電圧が設定
電工以上の時は積分手段12及び波形整形手段11によ
り所定時間′Pの間、マイクロプロセッサ2のリセット
端子がLの状態に保持される。In the present invention, by rapidly discharging the charge in the capacitor C of the integrating means L2, the reset terminal becomes L-shaped even when a momentary interruption occurs in the applied voltage, thereby reducing the possibility of runaway. did. That is, the applied voltage monitoring means 3
monitors whether the applied voltage is above or below the set voltage V1, and when the applied voltage is above the set voltage V1, the reset terminal of the microprocessor 2 is held in the L state for a predetermined time 'P by the integrating means 12 and the waveform shaping means 11. Ru.
しかし、印加電圧が設定電圧以下になった時は印加電圧
監視手段で駆動された放電手段4により5積分手段の中
のコンデンサCに貯えられた電荷を強制的に放電させて
波形整形手段の入力レベルを低下させてリセット端子を
Lの状態にする。そこで、印加電圧が立上っ゛ζ設定電
圧以上になった時は上記と同じくリセット端子を所定時
間T、 Lの状態に保持することが可能となり、瞬断
が生じてもマイクロプロセッサが暴走する可能性が少な
くなる。However, when the applied voltage falls below the set voltage, the electric charge stored in the capacitor C in the integrating means is forcibly discharged by the discharging means 4 driven by the applied voltage monitoring means and input to the waveform shaping means. The level is lowered to bring the reset terminal into the L state. Therefore, when the applied voltage exceeds the rising ζ setting voltage, it is possible to hold the reset terminal in the T or L state for a predetermined time as described above, and even if a momentary power outage occurs, the microprocessor will not run out of control. less likely.
第2図は本発明の実施例の回路図、第3図は第2図のタ
イムチャートを示す。尚、企図を通じて同一符号は同一
対象物を示す。又、抵抗器11+−1h及びトランジス
タυ1は印加電圧監視手段3、ダイオードD2.抵抗器
R,,C−MOSインバータ4は放電手段4、抵抗器R
,コンデンサCは積分手段12の構成部分である。以下
、条件は従来例と同一として第3図を参照して第2図の
動作を説明する。FIG. 2 shows a circuit diagram of an embodiment of the present invention, and FIG. 3 shows a time chart of FIG. Note that the same reference numerals refer to the same objects throughout the plan. Further, the resistor 11+-1h and the transistor υ1 are connected to the applied voltage monitoring means 3, the diode D2. Resistor R,,C-MOS inverter 4 is discharge means 4, resistor R
, capacitor C is a component of the integrating means 12. Hereinafter, the operation shown in FIG. 2 will be explained with reference to FIG. 3, assuming that the conditions are the same as in the conventional example.
先ず、抵抗器R9及びR2の値は印加電圧が設定電圧ν
1以上の時はトランジスタOIがオンになり、■。First, the values of resistors R9 and R2 are such that the applied voltage is the set voltage ν
When the value is 1 or more, the transistor OI is turned on, and ■.
以下の時はオフになる様に設定される。It is set to turn off in the following cases.
前者の場合、1−ランジスタロ、がオンになってコレク
タの電位がLの状態になるので、C−MOSインバータ
4′の出力はHの状態になりコンデンサCの両端の電位
はHの状態となり従来と同じになる(第3図−〇、■、
■の前半参照)。In the former case, the transistor 1 is turned on and the collector potential becomes L, so the output of C-MOS inverter 4' becomes H, and the potential across capacitor C becomes H, unlike the conventional will be the same as (Figure 3 - ○, ■,
(See the first half of ■).
後者の場合、トランジスタしかオフとなって0゜のコレ
クタ電位がHの状態となり、C−MOSインパーク4′
の出力側がLの状態になるので、コンデンサCはダイオ
ード02.を氏抗器I?4.. C−MOSインバータ
4′を通ってアースされるので、コンデンサC−の電荷
は強制的に瞬間に放電される(第3図−■1■、■の後
半参照)。In the latter case, only the transistor is turned off and the 0° collector potential becomes H, causing the C-MOS impark 4'
Since the output side of 02. is in the L state, capacitor C is connected to diode 02. Is it a resistance vessel? 4. .. Since it is grounded through the C-MOS inverter 4', the charge on the capacitor C- is forcibly discharged instantaneously (see the second half of 1 and 2 in FIG. 3).
次に、印加電圧が立上るとトランジスタしかオンになり
、上記と同様に所定時間T、Lの状態になった後、立上
った波形がリセット端子に印加される(第3図−■、■
1■後半参照)。これにより、印加電圧に瞬断が発生し
てもリセット端子には所定時間T、Lの状態を保てるの
でマイクロプロセッサは正常に動作することができる。Next, when the applied voltage rises, only the transistor turns on, and after being in the T and L states for a predetermined period of time in the same way as above, the rising waveform is applied to the reset terminal (Fig. 3-■, ■
(See the second half of 1). As a result, even if a momentary interruption occurs in the applied voltage, the reset terminal can maintain the T and L states for a predetermined period of time, allowing the microprocessor to operate normally.
尚、ダイオードD、及びコンデンサC1は印加電圧が多
少変動してもその変動を吸収してC−MOSインバータ
4’、 11に印加するためである。Note that the diode D and the capacitor C1 are used to absorb any slight fluctuations in the applied voltage and apply it to the C-MOS inverters 4' and 11.
以上詳細に説明した様に本発明によれば、印加電圧の瞬
断に対して、マイクロプロセッサの暴走の可能性を少な
くなると云う効果がある。As described above in detail, the present invention has the effect of reducing the possibility of the microprocessor running out of control in response to a momentary interruption of the applied voltage.
第1図は本発明の原理ブロック図、゛ 第2図は本発明の実施例の回路図、 第3図は第2図のタイムチャー1・、 第4図は従来例の回路図、 第5図は第4図のタイムチャー1・を示ず。 図において、 2はマイクロプロセッサ、 3ば印加電圧監視手段、 4は放電手段、 11は波形整形手段、 12は積分手段を示す。 子 3 圓 Figure 1 is a block diagram of the principle of the present invention. FIG. 2 is a circuit diagram of an embodiment of the present invention, Figure 3 shows the time chart 1 in Figure 2. Figure 4 is a circuit diagram of a conventional example. FIG. 5 does not show the time chart 1 of FIG. In the figure, 2 is a microprocessor, 3. Applied voltage monitoring means; 4 is a discharge means; 11 is a waveform shaping means; 12 indicates an integrating means. child 3 yen
Claims (1)
加電圧監視手段(3)と、該印加電圧を積分する積分手
段(12)と、 該積分手段の出力を波形整形した後にマイクロプロセッ
サ(2)に加える波形整形手段(11)と、該印加電圧
が設定電圧以下の時には該積分手段を構成するコンデン
サCに貯えられた電荷を強制的に放電させる放電手段(
4)とから構成されたことを特徴とするパワーオンリセ
ット回路。[Claims] Applied voltage monitoring means (3) for monitoring whether the applied voltage V is higher than or equal to the set voltage V_1, an integrating means (12) for integrating the applied voltage, and waveform shaping of the output of the integrating means. waveform shaping means (11) that applies the waveform shaping means (11) to the microprocessor (2) after the applied voltage is lower than the set voltage; and discharging means (11) that forcibly discharges the charge stored in the capacitor C constituting the integrating means when the applied voltage is below the set voltage.
4) A power-on reset circuit comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61168530A JPS6324408A (en) | 1986-07-17 | 1986-07-17 | Power-on resetting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61168530A JPS6324408A (en) | 1986-07-17 | 1986-07-17 | Power-on resetting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6324408A true JPS6324408A (en) | 1988-02-01 |
Family
ID=15869730
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61168530A Pending JPS6324408A (en) | 1986-07-17 | 1986-07-17 | Power-on resetting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6324408A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2021059795A1 (en) * | 2019-09-26 | 2021-04-01 |
-
1986
- 1986-07-17 JP JP61168530A patent/JPS6324408A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2021059795A1 (en) * | 2019-09-26 | 2021-04-01 | ||
WO2021059795A1 (en) * | 2019-09-26 | 2021-04-01 | 日立Astemo株式会社 | Electronic control device |
US11726794B2 (en) | 2019-09-26 | 2023-08-15 | Hitachi Astemo, Ltd. | Preventing supply of power to a microcomputer of an electronic control device until capacitors are discharged |
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