JPS6324408A - Power-on resetting circuit - Google Patents

Abstract

PURPOSE:To minimize the possibility of the run-away of a microprocessor even when a voltage is turned instantaneously interrupted by making forcibly a resetting terminal into an L condition when the impressing voltage of the microprocessor comes to be a set voltage or below and changing it to an H condition after the L condition is held continuously for a prescribed time when the impressing voltage is led. CONSTITUTION:The charge of a capacitor C of an integrating means 12 is quickly discharged, even when the instantaneous interruption occurs at an impressing voltage, a resetting terminal is made into an L condition and the possibility of the run-away is minimized. Namely, an impressing voltage supervising means 3 supervises whether or not an impressing voltage V is a set voltage V1 or above, when the impressing voltage comes to be the set voltage or below, a discharging means 4 driven by the impressing voltage supervising means discharges forcibly the charge stored at the capacitor C in the integrating means, the input level of a waveform shaping means is reduced and the resetting terminal is made into the L condition. When the impressing voltage is led and goes to be the set voltage or above, the resetting terminal can be held to the T and L condition for a prescribed time, and even when the instantaneous interruption occurs, the possibility that the microprocessor runs away is minimized.

Description

【発明の詳細な説明】 Ｃ概要〕 パワーオンリセット回路において、マイクロプロセッサ
の印加電圧が設定電圧■１以下になった時に強制的にこ
のマイクロプロセッサのリセット端子をＬの状態にし、
前記の印加電圧が立上った時には引き続き所定時間、Ｌ
の状態を保持させた後にＨの状態に変化させ、この印加
電圧に瞬断があってもマイクロプロセッサの暴走の可能
性を少なくする様にしたものである。[Detailed Description of the Invention] C Summary] In a power-on reset circuit, when the voltage applied to the microprocessor becomes less than the set voltage ■1, the reset terminal of the microprocessor is forcibly set to the L state,
When the applied voltage rises, L continues for a predetermined period of time.
After the state is maintained, it is changed to the H state to reduce the possibility of the microprocessor running out of control even if there is a momentary interruption in the applied voltage.

〔産業上の利用分野〕[Industrial application field]

本発明はパワーオンリセット回路、特にマイクロプロセ
ッサに電圧を印加した際にマイクロプロセッサのリセッ
ト端子を所定時間、Ｌの状態にするパワーオンリセット
回路の改良に関するものである。The present invention relates to an improvement in a power-on reset circuit, and particularly to a power-on reset circuit that keeps a reset terminal of a microprocessor in an L state for a predetermined period of time when a voltage is applied to the microprocessor.

近年、装置の小型化、経済化、高機能化に伴い種々の装
置にマイクロプロセッサが用いられているが、これを正
常に動作させるには電圧を印加した際にパワーオンリセ
ット回路を用いてリセット端子を所定時間、Ｌの状態に
しなければならないが、印加電圧が瞬断して立上る際に
もリセット端子を上記と同じ状態にして暴走の可能性を
少なくすることが必要である。In recent years, microprocessors have been used in various devices as devices have become smaller, more economical, and more sophisticated.In order for these devices to operate properly, they must be reset using a power-on reset circuit when voltage is applied. Although the terminal must be in the L state for a predetermined period of time, it is necessary to reduce the possibility of runaway by keeping the reset terminal in the same state as above even when the applied voltage is momentarily cut off and then rising.

〔従来の技術〕[Conventional technology]

第４図は従来例のブロック図、第５図は第４図のタイム
チャー１・を示す。以下、マイクロプロセッサば８ピノ
Ｉ・とじて第５図を参照して第４図の動作を説明する。FIG. 4 is a block diagram of a conventional example, and FIG. 5 shows a time chart 1 of FIG. Hereinafter, the operation of FIG. 4 will be explained with reference to FIG. 5, including the microprocessor.

尚、Ｌ及びＨの状態とは’ｒ　’ｌ’　Ｌ　レベル（例
えば、しは０．８ｖ以下、１１は４■以上）で規定され
るレベルである。Note that the L and H states are levels defined by the 'r'l' L level (for example, HI is 0.8V or less, 11 is 4■ or more).

先ず、第５図−〇に示す（美にパワーオンリセット回路
１の端子に印加電圧Ｖ（例えば、５■）が時間Ｔ１だけ
印加されたとすると、抵抗１ｉＳＲとコンデンサＣとで
構成された積分Ｒ１１２を通ることにより積分されて第
５図−■に示す様に緩い立上り。First, as shown in FIG. As shown in Figure 5-■, it is integrated by passing through the curve and shows a gradual rise.

立下り部分を持つ波形が得られ、これをＣ−ＭＯ５型ト
ランジスタで構成された波形整形器１１に通すと゛しき
い値“Ｖい以上の入力レベルはｌ［に、以下はＬになっ
て第５図−〇のｎｉ？半に示す様に立上り点が第５図−
〇の波形の立上り点よりも所定時間Ｔ、遅延した波形が
マイクロプロセッサのリセット端子に加えられる。A waveform with a falling part is obtained, and when this is passed through the waveform shaper 11 composed of C-MO5 type transistors, the input level above the "threshold value" V becomes L[, and below it becomes L]. Figure 5- As shown in the ni? half of 〇, the rising point is Figure 5-
A waveform that is delayed by a predetermined time T from the rising point of the waveform marked 〇 is applied to the reset terminal of the microprocessor.

ここで、上記の様に所定時間Ｔ、遅延させる理由は下記
の様である。Here, the reason for delaying the predetermined time T as described above is as follows.

マイクロプロセッサ２が正常に動作する為にはこの中の
プログラムカウンタ（図示せず）に例えばＦ　Ｆ　ｌｉ
　Ｌｉ及びＦＦＦＦがロードされる。そこで、この番地
に飛ぶと、ここには例えばＲＯＭ　（図示せず）内のプ
ログラムされた命令があるので、マイクロプロセッサは
その命令を読んで初期状態にした後、制御命令に従って
装置の制御が正しく行われる。In order for the microprocessor 2 to operate normally, a program counter (not shown) therein must be programmed with, for example, F F li
Li and FFFF are loaded. Therefore, when jumping to this address, there is a programmed instruction in, for example, a ROM (not shown), so the microprocessor reads that instruction and sets it to the initial state, and then correctly controls the device according to the control instruction. It will be done.

即ち、プログラムカウンタにＦＦＦＥ及びＦ　Ｆ　ｌ’
　）ｉがロードされないとマイクロプロセッサは動作し
ないが、これをロードする為に所定時間１゛、リセット
端子をＬの状態にする必要がある。That is, FFFE and F F l' are stored in the program counter.
) If i is not loaded, the microprocessor will not operate, but in order to load it, it is necessary to keep the reset terminal in the L state for a predetermined time of 1.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、第５図−〇の後半に示す様に印加電圧にＣＲの
時定数よりも短い瞬断が発生すると、積分器の出力は第
５図−■の後半に示す様に凹むが、この凹みは波形整形
器の“しきい値”ＶＬｈより高いのでリセット端子は１
１の状態を保持する。However, if an instantaneous interruption occurs in the applied voltage that is shorter than the CR time constant as shown in the second half of Figure 5-○, the output of the integrator will be depressed as shown in the second half of Figure 5-■. is higher than the “threshold value” VLh of the waveform shaper, so the reset terminal is set to 1.
The state of 1 is maintained.

一方、印加電圧が瞬断したのでマイクロプロセッサ・内
部のプログラムカウンタやＲＡＭ　（図示せず）の状態
が不定になるが、リセット端子がＬの状態にならないの
でマイクＵ、！プロセッサはリセット動１１ができず、
プログラム通りの正常動作が不可能となり所謂、暴走す
るが、これを正常動作させるには人手によってマイクロ
プロセッサの印加電圧を一度断にして、リセット端子を
所定時間りの状態にしなければならない。On the other hand, due to a momentary interruption of the applied voltage, the states of the microprocessor, internal program counter, and RAM (not shown) become unstable, but the reset terminal does not go into the L state, so the microphone U! The processor cannot perform the reset operation 11,
Normal operation according to the program becomes impossible and a so-called runaway occurs, but in order to restore normal operation, the voltage applied to the microprocessor must be manually cut off once and the reset terminal must be kept in a state for a predetermined period of time.

即ち、印加電圧が瞬断した際にはマイクロブロセ、す・
は暴走する可能性が高いと云う問題点がある。In other words, when the applied voltage is interrupted momentarily, the microblossom
The problem is that there is a high possibility that it will go out of control.

〔問題点を解決する為の手段〕[Means for solving problems]

上記の問題点は第１図に示す様に、印加電圧■が設定電
圧■１以上か以下かを監視する印加電圧監視手段３と、
該印Ｊｊｌｌ電圧を積分する積分手段１２と、該積分手
段の出力を波形整形した後にマ・イクロブロセノサ２に
加える波形整形手段■１と、該印加電圧が設定電圧以下
の時に該積分手段を構成するコンテンツＣに貯えられた
電荷を強制的にＪｉｌ、電させる放電手段４とから構成
された本発明のパワーオンリモノ１−回路により解決さ
れる。The above problem, as shown in FIG.
An integrating means 12 that integrates the Jjll voltage, a waveform shaping means (1) which applies waveform shaping to the output of the integrating means and then applies it to the microprocessor 2, and the integrating means when the applied voltage is below a set voltage. This problem is solved by the power-only mono 1-circuit of the present invention, which is constituted by a discharging means 4 for forcibly discharging the charge stored in the content C.

〔作用〕[Effect]

本発明は、積分手段Ｌ２のコンデンサＣの電荷を急速に
放電することにより、印加電圧に瞬断が発生した際にも
リセット端子がＬの状１虚になる礒にして暴走の可能性
を少なくした。即ち、印加電圧監視手段３で印加電圧Ｖ
が設定電圧Ｖ１以上か以下かを監視し、印加電圧が設定
電工以上の時は積分手段１２及び波形整形手段１１によ
り所定時間′Ｐの間、マイクロプロセッサ２のリセット
端子がＬの状態に保持される。In the present invention, by rapidly discharging the charge in the capacitor C of the integrating means L2, the reset terminal becomes L-shaped even when a momentary interruption occurs in the applied voltage, thereby reducing the possibility of runaway. did. That is, the applied voltage monitoring means 3
monitors whether the applied voltage is above or below the set voltage V1, and when the applied voltage is above the set voltage V1, the reset terminal of the microprocessor 2 is held in the L state for a predetermined time 'P by the integrating means 12 and the waveform shaping means 11. Ru.

しかし、印加電圧が設定電圧以下になった時は印加電圧
監視手段で駆動された放電手段４により５積分手段の中
のコンデンサＣに貯えられた電荷を強制的に放電させて
波形整形手段の入力レベルを低下させてリセット端子を
Ｌの状態にする。そこで、印加電圧が立上っ゛ζ設定電
圧以上になった時は上記と同じくリセット端子を所定時
間Ｔ、　　Ｌの状態に保持することが可能となり、瞬断
が生じてもマイクロプロセッサが暴走する可能性が少な
くなる。However, when the applied voltage falls below the set voltage, the electric charge stored in the capacitor C in the integrating means is forcibly discharged by the discharging means 4 driven by the applied voltage monitoring means and input to the waveform shaping means. The level is lowered to bring the reset terminal into the L state. Therefore, when the applied voltage exceeds the rising ζ setting voltage, it is possible to hold the reset terminal in the T or L state for a predetermined time as described above, and even if a momentary power outage occurs, the microprocessor will not run out of control. less likely.

〔実施例〕〔Example〕

第２図は本発明の実施例の回路図、第３図は第２図のタ
イムチャートを示す。尚、企図を通じて同一符号は同一
対象物を示す。又、抵抗器１１＋−１ｈ及びトランジス
タυ１は印加電圧監視手段３、ダイオードＤ２．抵抗器
Ｒ，，Ｃ−ＭＯＳインバータ４は放電手段４、抵抗器Ｒ
，コンデンサＣは積分手段１２の構成部分である。以下
、条件は従来例と同一として第３図を参照して第２図の
動作を説明する。FIG. 2 shows a circuit diagram of an embodiment of the present invention, and FIG. 3 shows a time chart of FIG. Note that the same reference numerals refer to the same objects throughout the plan. Further, the resistor 11+-1h and the transistor υ1 are connected to the applied voltage monitoring means 3, the diode D2. Resistor R,,C-MOS inverter 4 is discharge means 4, resistor R
, capacitor C is a component of the integrating means 12. Hereinafter, the operation shown in FIG. 2 will be explained with reference to FIG. 3, assuming that the conditions are the same as in the conventional example.

先ず、抵抗器Ｒ９及びＲ２の値は印加電圧が設定電圧ν
１以上の時はトランジスタＯＩがオンになり、■。First, the values of resistors R9 and R2 are such that the applied voltage is the set voltage ν
When the value is 1 or more, the transistor OI is turned on, and ■.

以下の時はオフになる様に設定される。It is set to turn off in the following cases.

前者の場合、１−ランジスタロ、がオンになってコレク
タの電位がＬの状態になるので、Ｃ−ＭＯＳインバータ
４′の出力はＨの状態になりコンデンサＣの両端の電位
はＨの状態となり従来と同じになる（第３図−〇、■、
■の前半参照）。In the former case, the transistor 1 is turned on and the collector potential becomes L, so the output of C-MOS inverter 4' becomes H, and the potential across capacitor C becomes H, unlike the conventional will be the same as (Figure 3 - ○, ■,
(See the first half of ■).

後者の場合、トランジスタしかオフとなって０゜のコレ
クタ電位がＨの状態となり、Ｃ−ＭＯＳインパーク４′
の出力側がＬの状態になるので、コンデンサＣはダイオ
ード０２．を氏抗器Ｉ？４．．　Ｃ−ＭＯＳインバータ
４′を通ってアースされるので、コンデンサＣ−の電荷
は強制的に瞬間に放電される（第３図−■１■、■の後
半参照）。In the latter case, only the transistor is turned off and the 0° collector potential becomes H, causing the C-MOS impark 4'
Since the output side of 02. is in the L state, capacitor C is connected to diode 02. Is it a resistance vessel? 4. ．． Since it is grounded through the C-MOS inverter 4', the charge on the capacitor C- is forcibly discharged instantaneously (see the second half of 1 and 2 in FIG. 3).

次に、印加電圧が立上るとトランジスタしかオンになり
、上記と同様に所定時間Ｔ、Ｌの状態になった後、立上
った波形がリセット端子に印加される（第３図−■、■
１■後半参照）。これにより、印加電圧に瞬断が発生し
てもリセット端子には所定時間Ｔ、Ｌの状態を保てるの
でマイクロプロセッサは正常に動作することができる。Next, when the applied voltage rises, only the transistor turns on, and after being in the T and L states for a predetermined period of time in the same way as above, the rising waveform is applied to the reset terminal (Fig. 3-■, ■
(See the second half of 1). As a result, even if a momentary interruption occurs in the applied voltage, the reset terminal can maintain the T and L states for a predetermined period of time, allowing the microprocessor to operate normally.

尚、ダイオードＤ、及びコンデンサＣ１は印加電圧が多
少変動してもその変動を吸収してＣ−ＭＯＳインバータ
４’、　１１に印加するためである。Note that the diode D and the capacitor C1 are used to absorb any slight fluctuations in the applied voltage and apply it to the C-MOS inverters 4' and 11.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明した様に本発明によれば、印加電圧の瞬
断に対して、マイクロプロセッサの暴走の可能性を少な
くなると云う効果がある。As described above in detail, the present invention has the effect of reducing the possibility of the microprocessor running out of control in response to a momentary interruption of the applied voltage.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の原理ブロック図、゛ 第２図は本発明の実施例の回路図、 第３図は第２図のタイムチャー１・、 第４図は従来例の回路図、 第５図は第４図のタイムチャー１・を示ず。 図において、 ２はマイクロプロセッサ、 ３ば印加電圧監視手段、 ４は放電手段、 １１は波形整形手段、 １２は積分手段を示す。 子　３　圓 Figure 1 is a block diagram of the principle of the present invention. FIG. 2 is a circuit diagram of an embodiment of the present invention, Figure 3 shows the time chart 1 in Figure 2. Figure 4 is a circuit diagram of a conventional example. FIG. 5 does not show the time chart 1 of FIG. In the figure, 2 is a microprocessor, 3. Applied voltage monitoring means; 4 is a discharge means; 11 is a waveform shaping means; 12 indicates an integrating means. child 3 yen

Claims (1)

【特許請求の範囲】 印加電圧Ｖが設定電圧Ｖ＿１以上か以下かを監視する印
加電圧監視手段（３）と、該印加電圧を積分する積分手
段（１２）と、 該積分手段の出力を波形整形した後にマイクロプロセッ
サ（２）に加える波形整形手段（１１）と、該印加電圧
が設定電圧以下の時には該積分手段を構成するコンデン
サＣに貯えられた電荷を強制的に放電させる放電手段（
４）とから構成されたことを特徴とするパワーオンリセ
ット回路。[Claims] Applied voltage monitoring means (3) for monitoring whether the applied voltage V is higher than or equal to the set voltage V_1, an integrating means (12) for integrating the applied voltage, and waveform shaping of the output of the integrating means. waveform shaping means (11) that applies the waveform shaping means (11) to the microprocessor (2) after the applied voltage is lower than the set voltage; and discharging means (11) that forcibly discharges the charge stored in the capacitor C constituting the integrating means when the applied voltage is below the set voltage.
4) A power-on reset circuit comprising: