JPS63236405A - Fm receiver - Google Patents
Fm receiverInfo
- Publication number
- JPS63236405A JPS63236405A JP6885387A JP6885387A JPS63236405A JP S63236405 A JPS63236405 A JP S63236405A JP 6885387 A JP6885387 A JP 6885387A JP 6885387 A JP6885387 A JP 6885387A JP S63236405 A JPS63236405 A JP S63236405A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- amplitude
- output
- circuit
- loop amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims abstract description 15
- 230000010355 oscillation Effects 0.000 claims description 2
- 230000000087 stabilizing effect Effects 0.000 claims 1
- 230000035945 sensitivity Effects 0.000 description 18
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000009412 basement excavation Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は位相同期ループ(PIGJF# Laockm
ti Loop以下PLLと略す)によって周波数変調
(FM)信号を受信し復調するA受信機に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a phase-locked loop (PIGJF#Laockm
The present invention relates to an A receiver that receives and demodulates a frequency modulation (FM) signal using a ti Loop (hereinafter abbreviated as PLL).
従来、PLLによるFM復調回路で選局と復調を同時に
行うへ受信機は、実開昭58−176414号公報に記
載のように、へ復調回路の電圧制御発振器を構成する可
変容量ダイオードに選局電圧を印加し、電圧制御発振器
の自走発振周波数を可変することで選局を行いかつ同じ
PLLによりFM復調するものである。Conventionally, a receiver that simultaneously performs tuning and demodulation using a PLL-based FM demodulation circuit uses a variable capacitance diode that constitutes a voltage-controlled oscillator of the demodulation circuit to select a tune, as described in Japanese Utility Model Application No. 58-176414. Tuning is performed by applying a voltage and varying the free-running oscillation frequency of the voltage controlled oscillator, and FM demodulation is performed using the same PLL.
PLLの電圧制御発振器の周波数KMII4感度は、復
調動作を行う信号帯域内でははば一定とみなせるが、受
信帯域9例えば衛星放送の1〜1.5GHz(第1中間
周波数)の広い範囲で考えると必ずしも一定でなく異な
る。PLLのループ利得には、位相比較器の感度をAK
、(V/rad〕、電圧制御発振器の周波数変調感度を
へ(ra←X〕、ループ増幅器の利得をに、とすると、
次式で表わされる。The frequency KMII4 sensitivity of the voltage controlled oscillator of the PLL can be considered to be constant within the signal band in which demodulation operation is performed, but when considered over a wide range of the receiving band 9, for example 1 to 1.5 GHz (first intermediate frequency) of satellite broadcasting, Not necessarily constant but different. For the PLL loop gain, the sensitivity of the phase comparator is
, (V/rad), the frequency modulation sensitivity of the voltage controlled oscillator is (ra←X), and the gain of the loop amplifier is
It is expressed by the following formula.
K = AK、 a K、 * Ka(1)式+11よ
り電圧制御発掘器の周波数変調感度が変化するとPLL
のループ利得が変化することになり、受信チャンネルに
よってPLLのループ条件が異なる問題があった。また
、PLLの復調信号の振幅は電圧制御発振器の周波数変
調感度に反比例することから、同じ周波数偏移の信号を
復調しても受信チャンネルによって復調信号の像幅が異
なる間粗があった。K = AK, a K, * Ka (1) From equation +11, when the frequency modulation sensitivity of the voltage-controlled excavator changes, the PLL
This results in a change in the loop gain of the PLL, resulting in a problem that the PLL loop conditions differ depending on the receiving channel. Further, since the amplitude of the demodulated signal of the PLL is inversely proportional to the frequency modulation sensitivity of the voltage controlled oscillator, even if signals with the same frequency shift are demodulated, the image width of the demodulated signal varies depending on the receiving channel.
本発明の目的は電圧制御発振器の周波数変調感度が変化
しても安定なQIvI4を提供することにある。An object of the present invention is to provide stable QIvI4 even if the frequency modulation sensitivity of the voltage controlled oscillator changes.
上記目的は、PLL内のループ増幅器の入力側より出力
した復調信号の振幅を検出する振幅検出回路と、振幅検
出回路の出力を入力し設定した振幅。The above object is an amplitude detection circuit that detects the amplitude of a demodulated signal output from the input side of a loop amplifier in a PLL, and an amplitude set by inputting the output of the amplitude detection circuit.
値と比較し誤差電圧を出方する振幅比較器を備え、奈幅
比収器の出力により七上記ループ増幅器の利得を制御す
るループを形成する構成と、受信チャンネルの選局期間
と受信信号の欠落期間は上記ループ増幅器の利得を固定
しほぼ最大利得とすることにより達成される。−
〔作 用〕
PLLにより復調された信号の振幅は、電圧制御発振器
の周波数変調感度に反比例するため、復調信号内の振幅
が変化しない信号、例えば映像信号の同期信号等の振幅
をみることにより、電圧制御発振器の周波数変調感度が
変化したかどうか知ることができる。いま、電圧制御発
掘器の周波数変調感度が2倍に変化したとすると、PL
Lのループ内の復調信号振幅は+となる。このときPL
Lのループ利得は式+11より2倍となる。したがって
ループ増幅器の利得を十に制御すれば、ループ利得は電
圧制御発振器の周波数変調感度が変化する前に戻すこと
ができる。ここで、ループ増幅器の前後の信号振幅に着
目すれば、電圧制御発振器に接続される側、すなわちル
ープ増幅器の出力側の信号振幅は電圧制御発振器の周波
数変調感度により元の+のままである。しかし、ループ
増幅器の入力側はループ増幅器の利得を+に制御したこ
とから変化する前の値に戻る。以上よりループ増幅器の
入力側から復調信号を出力し、この復調信号内で振幅が
変化しない特定の信号を振幅検出回路で検出し、振幅比
較器であらかじめ設定した振幅値と比較を行ない、振幅
比較器で得られた誤差電圧でPLLループ内のループ増
幅器の利得を制御し、ループ増幅器前の信号増幅すなわ
ち上記の特定の信号振幅が一定となるよう制御されるた
め、PLLのループ利得は一定となり、またループ増幅
器の入力側から出力される復調信号の振幅は、′電圧制
御発掘器の周波数変調感度の変化に関係な(一定の復調
感度で得られる。また、受信チャンネルの選局期間と受
信信号の欠落期間はループ増幅器の利得を固定し、はば
最大利得とすることにより、上記制御の誤動作を防止す
るとともに、同期間のPLLの引込み動作において引込
み周波数幅の拡大と高速化が得られる。It is equipped with an amplitude comparator that outputs an error voltage by comparing the amplitude comparator with the amplitude comparator, and forms a loop that controls the gain of the above-mentioned loop amplifier using the output of the amplitude collector, and also controls the tuning period of the receiving channel and the receiving signal. The dropout period is achieved by fixing the gain of the loop amplifier to approximately the maximum gain. - [Function] The amplitude of the signal demodulated by the PLL is inversely proportional to the frequency modulation sensitivity of the voltage controlled oscillator. , you can know whether the frequency modulation sensitivity of the voltage controlled oscillator has changed. Now, if the frequency modulation sensitivity of the voltage-controlled excavator doubles, the PL
The demodulated signal amplitude in the L loop becomes +. At this time, PL
The loop gain of L is twice according to equation +11. Therefore, if the gain of the loop amplifier is controlled sufficiently, the loop gain can be returned to the level before the frequency modulation sensitivity of the voltage controlled oscillator changes. Here, if we focus on the signal amplitude before and after the loop amplifier, the signal amplitude on the side connected to the voltage controlled oscillator, that is, the output side of the loop amplifier, remains the original + due to the frequency modulation sensitivity of the voltage controlled oscillator. However, since the gain of the loop amplifier is controlled to +, the input side of the loop amplifier returns to the value before the change. From the above, a demodulated signal is output from the input side of the loop amplifier, a specific signal whose amplitude does not change within this demodulated signal is detected by the amplitude detection circuit, and is compared with a preset amplitude value by the amplitude comparator to compare the amplitude. The gain of the loop amplifier in the PLL loop is controlled using the error voltage obtained by the circuit, and the signal amplification before the loop amplifier, that is, the specific signal amplitude mentioned above, is controlled to be constant, so the loop gain of the PLL is constant. , and the amplitude of the demodulated signal output from the input side of the loop amplifier is related to the change in the frequency modulation sensitivity of the voltage-controlled excavator (obtained with a constant demodulation sensitivity. Also, the amplitude of the demodulated signal output from the input side of the loop amplifier is related to the change in frequency modulation sensitivity of the voltage-controlled excavator (obtained with a constant demodulation sensitivity. By fixing the gain of the loop amplifier during the signal drop period and setting it to the maximum gain, it is possible to prevent the above-mentioned control malfunction, and to expand the pull-in frequency width and speed up the PLL pull-in operation during the same period. .
以下、本発明の一実施例を図により説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第2図は、本発明の基本構成を示す図で、電圧制御発振
器1と位相比較器2とローパスフィルタ5とループ増幅
器4とでPLLを嘴成し、位相比較器2の他方の入力に
はバンドパスフィルタ5検波器20が接続され、バンド
パスフィルタ5の入力にはAGC21が接続され検波器
20の出力で制御され、PLLの復調信号はループ増幅
器4の入力側より出力され、出力された復調信号は分岐
され、復調信号内で振幅の変わらない特定の信号を検出
する振幅検出回路6に入力され、振幅検出回路6の出力
と振幅設定回路7の出力は振幅比較器8へ入力され、振
幅比較器8の出力と固定電圧発生器25の出力がスイッ
チ22に入力されスイッチ22の出力はループ増幅器4
に接続され、スイッチ22は選局回賊(図示せず)から
の選局中信号と検波器20の出力が入力されるしきい値
回路24の出力との論理和を出力するOR回路25の出
力で選択出力する。振幅検出回路6で復調信号内の振幅
が変化しない特定の信号、例えば状像信号の同期信号等
を検出し七の振幅値が出力し、振幅設定回路7の出力と
振幅比較器8で比較され、その差がループ増幅器4へ帰
還される。振幅比較器8は差動増幅回路で簡単に構成で
きる。また検波器20の出力があるしきい値以下すなわ
ち無信号時あるいは受信機の電源投入時、選局途中では
スイッチ22により固定電圧発生器25の出力がループ
増幅器に印加される。スイッチ22の制御は、無信号時
にはしきい値回路24の出力が1となり受信機の電源投
入時、選局 中では選局回路より出力される選局中信号
が1となり、それらをOR回路25により論理和をとり
、OR回路25の出力が1のとき固定電圧発生器25が
選択される。FIG. 2 is a diagram showing the basic configuration of the present invention, in which a PLL is formed by a voltage controlled oscillator 1, a phase comparator 2, a low-pass filter 5, and a loop amplifier 4, and the other input of the phase comparator 2 is A band pass filter 5 is connected to a detector 20, an AGC 21 is connected to the input of the band pass filter 5 and is controlled by the output of the detector 20, and the demodulated signal of the PLL is output from the input side of the loop amplifier 4. The demodulated signal is branched and inputted to an amplitude detection circuit 6 that detects a specific signal whose amplitude does not change within the demodulated signal, and the output of the amplitude detection circuit 6 and the output of the amplitude setting circuit 7 are inputted to an amplitude comparator 8. The output of the amplitude comparator 8 and the output of the fixed voltage generator 25 are input to the switch 22, and the output of the switch 22 is input to the loop amplifier 4.
The switch 22 is connected to the OR circuit 25 which outputs the logical sum of the channel selection signal from the channel selection pirate (not shown) and the output of the threshold circuit 24 to which the output of the detector 20 is input. Output selectively with output. The amplitude detection circuit 6 detects a specific signal whose amplitude does not change in the demodulated signal, such as a synchronization signal of the image signal, and outputs an amplitude value of 7, which is compared with the output of the amplitude setting circuit 7 by the amplitude comparator 8. , the difference is fed back to the loop amplifier 4. The amplitude comparator 8 can be easily constructed using a differential amplifier circuit. Further, the output of the fixed voltage generator 25 is applied to the loop amplifier by the switch 22 when the output of the detector 20 is below a certain threshold value, that is, when there is no signal, or when the power of the receiver is turned on, or during channel selection. The control of the switch 22 is such that when there is no signal, the output of the threshold circuit 24 is 1, and when the receiver is powered on, the tuning signal output from the tuning circuit becomes 1 while tuning is in progress, and these are output by the OR circuit 25. When the output of the OR circuit 25 is 1, the fixed voltage generator 25 is selected.
第1図は、本発明の別の実施例を示す図で、選局回路9
を設け、電圧制御発振器の自走発掘周波数とバンドパス
フィルタの中心周波数を一致して可変させ希望信号を受
信する構成である。FIG. 1 is a diagram showing another embodiment of the present invention, in which a tuning circuit 9
The configuration is such that the free-running excavation frequency of the voltage controlled oscillator and the center frequency of the bandpass filter are varied to match and receive a desired signal.
第5図は本発明の別の実施例で、選局回路9が選局電圧
発生回路10と離調検出回路11と選局電圧発生回路1
0の出力と虐調検出回路11の出方は加算され電圧制御
発振器に入力される。離調検出回路はPLLの復調出力
の平均直流電圧あるいは特定の信号の直流成分によって
離調の方向と大きさを検出しその出力を選局電圧に帰還
することでAFC回路を構成している。FIG. 5 shows another embodiment of the present invention, in which a tuning circuit 9 includes a tuning voltage generation circuit 10, a detuning detection circuit 11, and a tuning voltage generation circuit 1.
The output of 0 and the output of the abuse detection circuit 11 are added and input to the voltage controlled oscillator. The detuning detection circuit constitutes an AFC circuit by detecting the direction and magnitude of detuning based on the average DC voltage of the demodulated output of the PLL or the DC component of a specific signal, and feeding back the output to the tuning voltage.
第4図は本発明の別の実施例で、選局回路9は基準周波
数を発生する基準周波数発生器12と電圧制御発振器の
出力を分周するプログラマブル・ディバイダ15と第2
のローパスフィルタ14と第2の位相比較器を設は電圧
制御発振器を共用したPLL選局回路とバンドパスフィ
ルタ5の中心周波数をプログラマブル・ディバイダ15
に入力されるプログラムコードに対応して制御する制御
回路16から構成される。FIG. 4 shows another embodiment of the present invention, in which the tuning circuit 9 includes a reference frequency generator 12 that generates a reference frequency, a programmable divider 15 that divides the output of a voltage controlled oscillator, and a second
A programmable divider 15 is provided with a low-pass filter 14 and a second phase comparator to set the center frequency of a PLL tuning circuit that shares a voltage-controlled oscillator and a band-pass filter 5.
The control circuit 16 is configured to perform control according to a program code input to the control circuit 16.
第5図は本発明の別の実施例で、スクランブル方式の衛
星放送や高精細放送の信号のように信号が抑圧あるいは
不規側であり、振幅検出回路6に入力する特定の信号が
簡単に分離できない場合、復調信号を処理する信号処理
回路17より特定の信号のタイミングパルスを出力し、
そのタイミングパルスにより、復調信号内の振幅の変わ
らない特定の信号を検出できる。FIG. 5 shows another embodiment of the present invention, in which the signal is suppressed or irregular, such as scrambled satellite broadcasting or high-definition broadcasting, and the specific signal input to the amplitude detection circuit 6 is easily If separation is not possible, a timing pulse of a specific signal is output from the signal processing circuit 17 that processes the demodulated signal,
The timing pulse allows detection of a specific signal whose amplitude does not change within the demodulated signal.
本発明によれば、PLL内の電圧制御発振器の周波数変
調感度が受信チャンネルごとに異なってもPLLのルー
プ利得は一定で変化せず安定したループ条件でFM復調
が行える。また、PLL内のループ増幅器の入力側より
出力した復調信号の振幅は、PLL内の電圧制御発振器
の周波数変調感度の変化にかかわらず一定の復調感度で
得られ安定した信号処理が行える。また、受信チャンネ
ルの選局期間と受信信号の欠落期間ではPLLの引込み
動作の周波数幅が拡大され、高速化される効果がある。According to the present invention, even if the frequency modulation sensitivity of the voltage controlled oscillator in the PLL differs depending on the receiving channel, the loop gain of the PLL remains constant and does not change, and FM demodulation can be performed under stable loop conditions. Further, the amplitude of the demodulated signal output from the input side of the loop amplifier in the PLL is obtained with constant demodulation sensitivity regardless of changes in the frequency modulation sensitivity of the voltage controlled oscillator in the PLL, and stable signal processing can be performed. Furthermore, during the reception channel selection period and the reception signal dropout period, the frequency width of the PLL pull-in operation is expanded, which has the effect of speeding up the operation.
第1図は本発明の一実施例を示すブロック図、第2図は
本発明の基本構成を示すブロック図、第5図は本発明の
別の実施例を示すブロック図、第4図は本発明の別の実
施例を示すブロック図、第5図は本発明の別の実施例を
示すブロック図である。
1・・・電圧制御発振器
2・・・位相比較器
5・・・ローパスフィルタ
4・・・ループ増幅器
5・・・バンドパスフィルタ
6・・・振幅検出回路
7・・・振幅設定回路
8・・・振幅比較器
9・・・選局回路
20・・・検波器
21・・・AGC回路
22・・・スイッチ
25・・・固定電圧発生器
24・・・しきい値回路
25・・・OR回路FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing the basic configuration of the present invention, FIG. 5 is a block diagram showing another embodiment of the present invention, and FIG. 4 is a block diagram showing the basic configuration of the present invention. Block Diagram Showing Another Embodiment of the Invention FIG. 5 is a block diagram showing another embodiment of the invention. 1...Voltage controlled oscillator 2...Phase comparator 5...Low pass filter 4...Loop amplifier 5...Band pass filter 6...Amplitude detection circuit 7...Amplitude setting circuit 8...・Amplitude comparator 9...Tuition selection circuit 20...Detector 21...AGC circuit 22...Switch 25...Fixed voltage generator 24...Threshold circuit 25...OR circuit
Claims (1)
ループ増幅器から成る位相同期回路と上記位相比較器の
入力に接続されたバンドパスフィルタとで構成されたF
M受信機において、選局と選局周波数安定化の手段を備
えた選局回路により上記電圧制御発振器の自走発振周波
数と上記バンドパスフィルタの中心周波数を一致して可
変させ希望信号を受信する構成と、上記ループ増幅器の
入力側より出力した復調信号を入力し復調信号の振幅を
検出する振幅検出回路と振幅検出回路の出力を入力し設
定振幅値と比較する振幅比較器と振幅比較器の出力と固
定電圧を選択出力するスイッチを備えスイッチの出力に
よって上記ループ増幅器の利得を制御する手段と選局期
間あるいは受信信号が無い期間はスイッチの出力を固定
電圧にする手段を設けたことを特徴とするFM受信機。1. Phase comparator, voltage controlled oscillator, low pass filter,
F, which is composed of a phase locked circuit consisting of a loop amplifier and a bandpass filter connected to the input of the phase comparator.
In the M receiver, a desired signal is received by varying the free-running oscillation frequency of the voltage-controlled oscillator and the center frequency of the band-pass filter to coincide with each other using a tuning circuit equipped with means for tuning and stabilizing the tuning frequency. The configuration includes an amplitude detection circuit that inputs the demodulated signal output from the input side of the loop amplifier and detects the amplitude of the demodulated signal, and an amplitude comparator that inputs the output of the amplitude detection circuit and compares it with a set amplitude value. It is characterized by comprising a switch for selectively outputting an output and a fixed voltage, means for controlling the gain of the loop amplifier according to the output of the switch, and means for setting the output of the switch to a fixed voltage during a tuning period or a period when there is no received signal. FM receiver.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6885387A JPS63236405A (en) | 1987-03-25 | 1987-03-25 | Fm receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6885387A JPS63236405A (en) | 1987-03-25 | 1987-03-25 | Fm receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63236405A true JPS63236405A (en) | 1988-10-03 |
Family
ID=13385644
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6885387A Pending JPS63236405A (en) | 1987-03-25 | 1987-03-25 | Fm receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63236405A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07202573A (en) * | 1993-09-29 | 1995-08-04 | Sgs Thomson Microelectron Ltd | Fm carrier wave demodulation method and demodulating circuit |
-
1987
- 1987-03-25 JP JP6885387A patent/JPS63236405A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07202573A (en) * | 1993-09-29 | 1995-08-04 | Sgs Thomson Microelectron Ltd | Fm carrier wave demodulation method and demodulating circuit |
US6160444A (en) * | 1993-09-29 | 2000-12-12 | Stmicroelectronics Of The United Kingdom | Demodulation of FM audio carrier |
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