JPS63236313A - Compound semiconductor integrated circuit - Google Patents
Compound semiconductor integrated circuitInfo
- Publication number
- JPS63236313A JPS63236313A JP6881787A JP6881787A JPS63236313A JP S63236313 A JPS63236313 A JP S63236313A JP 6881787 A JP6881787 A JP 6881787A JP 6881787 A JP6881787 A JP 6881787A JP S63236313 A JPS63236313 A JP S63236313A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- patterns
- selective growth
- compound semiconductor
- growth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 150000001875 compounds Chemical class 0.000 title claims abstract description 11
- 230000012010 growth Effects 0.000 claims abstract description 30
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000013078 crystal Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 230000002093 peripheral effect Effects 0.000 abstract description 4
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 230000007773 growth pattern Effects 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は化合物半導体によるＭＥＳＦＥＴに係わり、特
にＧ ａ Ａ ｓ ＭＥＳＦＥＴとこれらを中心に集
積した半導体装置及びその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to MESFETs using compound semiconductors, and more particularly to GaAs MESFETs, semiconductor devices integrated therewith, and methods of manufacturing the same.
従来のＧ ａ Ａ ｓ ＭＥ！５ＦＥＴはゲート電極
とソース電極の直列抵抗Ｒｓｔを極力小さくして性能を
向上させるため、高゛耐熱ゲート電極（例えばタングス
テンシリサイド、ＷＳｉｘ）を用いたセルファライン形
構造で作られていた。ｎ十−低抵抗層をゲート電極の周
辺にセルファラインで形成するため、Ｓｉイオン打込み
技術および選択成長技術が使われている。選択成長層は
Ｓｉイオン打込みで作った層より、■高濃度不純物濃度
が得やすいので低抵抗化できる、■イオン打込みではア
ニール温度が７５０℃以上必要であるが１選択成長層度
は約６００〜７００℃と低くできるので、ゲート電極の
ショットキ接合の劣化は少ない、などの利点がある。し
かし選択成長にも欠点がある。例えば単位ＦＥＴや、少
規模集積回路では、特に問題にならなかったことが、中
、大規模集積回路で顕在化した。すなわち、選択成長に
パターンの粗・密依存性があり、Ｇ ａ Ａ ｓ成長層
の膜厚が孤立パターン群では厚く、密集パターン群では
薄くなるという問題である。Conventional G a As ME! In order to improve performance by minimizing the series resistance Rst between the gate electrode and the source electrode, the 5FET was made with a self-line structure using a highly heat-resistant gate electrode (for example, tungsten silicide, WSix). Si ion implantation technology and selective growth technology are used to form the n+-low resistance layer around the gate electrode in a self-lined manner. The selective growth layer is better than the layer made by Si ion implantation: ■ It is easier to obtain a high impurity concentration, so the resistance can be lowered. ■ Ion implantation requires an annealing temperature of 750°C or higher, but the selective growth layer degree is approximately 600°C or higher. Since the temperature can be as low as 700° C., there are advantages such as less deterioration of the Schottky junction of the gate electrode. However, selective growth also has drawbacks. For example, what was not a particular problem in unit FETs and small-scale integrated circuits has become apparent in medium- and large-scale integrated circuits. That is, there is a problem in that selective growth is dependent on pattern sparseness and density, and the thickness of the GaAs growth layer is thicker in isolated pattern groups and thinner in dense pattern groups.
この膜厚は、ＬＳＩを作る上で許容限界を越えて５例え
ば密集部では３００ｎｍの膜厚のものが、孤立部では６
００〜８００ｎｍとなった。また厚く成長する孤立パタ
ーンの領域では、５ｉＯｚ膜やＷ Ｓ ｉ ｘ膜上の成
長不用部に結晶粒が析出し、外観不良となった。これは
配線工程の歩留りを著しく低下させ、ＬＳＩ化を回置な
ものとしていた。This film thickness exceeds the permissible limit for making LSIs.
The wavelength ranged from 00 to 800 nm. In addition, in the region of the isolated pattern that grows thickly, crystal grains precipitate in unnecessary growth areas on the 5iOz film and the WSi x film, resulting in poor appearance. This significantly lowered the yield of the wiring process and made LSI implementation a deferred process.
なおｎ十選択成長で得られたＦＥＴは、ジャパニーズ・
ジャーナルオブアプライドフイジックス２３ 、５ （
１９８４年）第Ｌ３４２から第Ｌ３４５Ｊａｐａｎｅｓ
ｅ Ｊｏｕｒｎａｌ ｏｆ Ａｐｐｌｉｅｄ Ｐｈｙｓ
ｉｃｓ、 Ｖｏｌ。Note that the FET obtained by n-ten selective growth is Japanese
Journal of Applied Physics 23, 5 (
1984) No. L342 to L345 Japanese
e Journal of Applied Phys.
ics, Vol.
２３ 、 ＮＱ５ （１９８４） ＰＰＬ３４２−３４
５）に記載されている。23, NQ5 (1984) PPL342-34
5).
上記従来技術はＬＳＩ化には配慮がされておらず、選択
成長膜厚にパターンの粗・密依存性がある問題があった
。The above-mentioned conventional technology does not take into consideration LSI implementation, and there is a problem in that the thickness of the selectively grown film depends on the coarseness and density of the pattern.
本発明の目的は上述した欠点を解決し、ＬＳＩ化に適し
た選択成長技術で素子及び回路を製造することにある。An object of the present invention is to solve the above-mentioned drawbacks and to manufacture elements and circuits using a selective growth technique suitable for LSI.
Ｓ ｉ Ｏｘ ’ｅ’Ｗｓ ｉｘ材の表面をさけてＧ
ａ Ａ ｓ表面だけにＧ ａ Ａ ｓを選択的に成長さ
せる技術には主にＭＯＣＶＤと呼ばれる成長法が用いら
れる。実験の結果、成長膜厚にパターンの粗・密依存性
があることがわかった。S i Ox 'e'Ws ix G, avoiding the surface of the material.
A growth method called MOCVD is mainly used as a technique for selectively growing GaAs only on the aAs surface. As a result of experiments, it was found that the thickness of the grown film depends on the coarseness and density of the pattern.
実験では第４図の如き孤立パターンＡと距離Ｑで分けら
れた周辺パターンＢを用いて、Ｑを零から十分前して変
化させたときのパターンＡに成長したＧ ａ Ａ ｓ層
の厚さｄを求めた。パターンＡ。In the experiment, an isolated pattern A and a peripheral pattern B separated by a distance Q as shown in Fig. 4 were used, and the thickness of the G a A s layer grown in pattern A when Q was changed sufficiently from zero. I found d. Pattern A.
ＢはＧ ａ Ａ ｓ表面が呪われており、両者は５ｉＯ
ｚ４０で分離されている９この結果を第５図に示す。B has a cursed G a A s surface, and both are 5iO
The results are shown in FIG.
上記成長層の厚さｄは、Ωが小さいときには、全面成長
厚さと同じ厚さｃｔｏ となるが、Ｑが約１００μｍを
こえると急激に厚く成長し、Ｑが約２５０μｍ以上から
は厚さが飽和する傾向を有している。When Ω is small, the thickness d of the growth layer is the same as the overall growth thickness cto, but when Q exceeds about 100 μm, it rapidly grows thicker, and when Q exceeds about 250 μm, the thickness becomes saturated. have a tendency to
しかも成長条件（温度、流量、ガス比など）でパターン
の粗・密によらぬ選択成長を行なわしめることは回置で
ある結論が得られた。これを解決するには、成長層のパ
ターンを一様に密とするようなダミーパターンを粗の領
域に形成して、ダミーパターンにも結晶成長を行なうこ
とが好ましいことがわかった。また本パターンとダミー
・パターンの距離は少なくとも１００μｍ以内で配置す
る必要があることが第５図かられかった。またダミーパ
ターンは半絶縁性Ｇ ａ Ａ ｓ上に成長するものであ
るから、これによって集積回路の性能を低下することが
ないよう配慮して２通常ダミーパターンはメモリセル内
に用いている分割したパターン群を並べたものを利用す
るようにした。これによって配線層がダミーパターン上
を通る場合でも、ダミーパターンのない従来のものと比
べて配線容量が増えることはなくなった。Moreover, it was concluded that selective growth regardless of whether the pattern is coarse or dense under growth conditions (temperature, flow rate, gas ratio, etc.) is inversion. In order to solve this problem, it has been found that it is preferable to form a dummy pattern in a coarse region so that the pattern of the growth layer is uniformly dense, and to perform crystal growth on the dummy pattern as well. Furthermore, it was found from FIG. 5 that the distance between the main pattern and the dummy pattern must be at least 100 μm. In addition, since the dummy pattern is grown on the semi-insulating GaAs, in order to prevent this from degrading the performance of the integrated circuit, the dummy pattern is usually grown on the divided layer used in the memory cell. I started using a list of pattern groups. As a result, even when the wiring layer passes over the dummy pattern, the wiring capacitance does not increase compared to the conventional structure without the dummy pattern.
本パターンに近接して、ダミーパターンを設けることに
よって選択成長の厚さはウェーハのどの位置でも均一に
することができる。By providing a dummy pattern close to the main pattern, the thickness of the selective growth can be made uniform at any position on the wafer.
以下、本発明の一実施例を以下により説明する。 An embodiment of the present invention will be described below.
ＧａＡｓ ＬＳＩのキーデバイスであるＦＥＴをｎ＋
Ｇ ａ Ａ ｓの選択成長層でセルファラインして
形成した場合の素子断面構造を第３図に示す。FET, which is a key device of GaAs LSI, is
FIG. 3 shows a cross-sectional structure of an element formed by self-lining with a selectively grown layer of GaAs.
ゲート電極１０，１１はＷ Ｓ ｉ ｘの耐熱性ショッ
トバリアであり、このゲートをはさんで両側にソース、
ドレイン用の窓をＳｉＯ２膜に明け、ＭＯＣＶＤによる
選択成長でｎ＋ −Ｇ ａ Ａ ｓ層２０，３０をえる
。成長不用の部分は５ｉＯｚ膜４０，５ｉＯｚ側壁５０
及びＷ Ｓ ｉ ｘゲート電極１１上である。The gate electrodes 10 and 11 are heat-resistant shot barriers of WSi x, and there are sources on both sides of the gate, and
A drain window is opened in the SiO2 film, and n+ -GaAs layers 20 and 30 are obtained by selective growth using MOCVD. The parts that do not require growth are the 5iOz film 40 and the 5iOz sidewall 50.
and on the W Si x gate electrode 11 .
このようなＦＥＴを沢山使用して、ＳＲＡＭのようなメ
モリ回路かえられている。Memory circuits such as SRAM are being modified by using many such FETs.
選択成長用のＦＥＴ１コのパターンは第３図に示した如
くであるが、メモリ回路では、第１図（ａ）に示すよう
な密度の高いパターン領域がチップ内に局在して配置さ
れている。同図（ａ）のハツチング部はメモリセル部パ
ターン群２００と周辺回路部パターン群１０１，１０２
を表わしている、同図（ａ）のままのパターンでｎ＋
−ＧａＡｓ層を選択成長すると密集パターンの周辺部で
異常に厚い成長層となってＬＳＩとして使用できない。The pattern of one FET for selective growth is as shown in Fig. 3, but in a memory circuit, a high-density pattern area as shown in Fig. 1(a) is arranged locally within the chip. There is. The hatched portion in FIG.
n+ with the same pattern as shown in (a) in the figure
- If the GaAs layer is selectively grown, the grown layer becomes abnormally thick around the dense pattern and cannot be used as an LSI.
そこで第１図（ｂ）の如く、成長パターンが従来不用で
あった領域にダミーパターン群３００を配置して第１図
の（、）と（ｂ）のパターンを重ねてウェーハ上に形成
して選択成長を行なうようにした。Therefore, as shown in FIG. 1(b), a dummy pattern group 300 is placed in a region where a growth pattern is not needed conventionally, and the patterns in FIG. 1 (,) and (b) are overlapped and formed on the wafer. Selective growth is now possible.
第２図は第１図（ａ）と（ｂ）のパターンを重ねたとき
の本パターン３００とダミーパターン４００の境界部を
拡大して表示したものである。FIG. 2 is an enlarged view of the boundary between the main pattern 300 and the dummy pattern 400 when the patterns of FIGS. 1(a) and 1(b) are overlapped.
この図に示した距ＩｉＱは本パターンの特性に悪影響を
及ぼさぬ限り接近させた方がよく、通常は５〜５０μｍ
の範囲内で決められる。第２図の如くダミーパターンの
模様は本パターンのそれに同じか近いことが好ましく、
通常はメモリセル部２００のくり返しパターン模様を用
いている。The distance IiQ shown in this figure should be kept close to each other as long as it does not adversely affect the characteristics of this pattern, and is usually 5 to 50 μm.
It can be determined within the range of As shown in Figure 2, it is preferable that the pattern of the dummy pattern is the same as or close to that of the main pattern.
Usually, a repeating pattern of the memory cell portion 200 is used.
本発明の実施例をＧａＡｓ ＳＲＡＭパターンで述べ
たが、単体ＦＥＴを含んだ種々の機能回路でも同様な趣
旨によるダミーパターンを用いることで、選択成長によ
る成長膜厚を均一に得られるようになることは言うに及
ばない。Although the embodiment of the present invention has been described using a GaAs SRAM pattern, by using a dummy pattern with a similar purpose in various functional circuits including single FETs, it is possible to obtain a uniform film thickness by selective growth. Needless to say.
本発明によれば、ＧａＡｓ ＬＳＩがｎ＋ −Ｇ ａ
Ａ ｓ選択成長技術を用いて製作できるようになった
ので、従来イオン打込みで形成したいたｎ十層の抵抗に
比べて、約１／１０の低抵抗比が達成でき、これによっ
てＦＥＴの直列抵抗は約１１５と改善できた。そのため
従来より約２倍高速なメモリ素子をえることができた。According to the present invention, the GaAs LSI is n+ -Ga
Since it has become possible to fabricate using As selective growth technology, it is possible to achieve a low resistance ratio of about 1/10 compared to the n-layer resistor that was conventionally formed by ion implantation. was improved to about 115. As a result, it was possible to obtain a memory element that is approximately twice as fast as the conventional one.
また、これはｎ＋ −ＧａＡｓ選択成長層のセルファラ
インによって改善されたＦＥＴの特性であるが、従来の
イオン打込みでは８００℃の熱処理によって短ゲート効
果の劣化、ショットキバリアの劣化がみられていたもの
がなくなって、著しく性能を向上させることができた。Additionally, this is a FET characteristic that has been improved by the self-line of the n+ -GaAs selectively grown layer, but with conventional ion implantation, the short gate effect and Schottky barrier deteriorated due to heat treatment at 800°C. was eliminated, and the performance was significantly improved.
第１図は本発明の一実施例の（ａ）本パターン（ｂ）ダ
ミーパターンの上面図、第２図は本パターンとダミーパ
ターンの境界部における拡大図、第３図はＦＥＴの素子
図、第４図は選択成長で粗・密依存性を調べたパターン
、第５図は第４図を用いて実験した結果である。
１・・・Ｇ ａ Ａ ｓ基板結晶、１０１．１０２・・
・周辺回路部パターン、２００・・・メモリセル部パタ
ーン、３００・・・ダミーパターン。FIG. 1 is a top view of (a) a main pattern (b) a dummy pattern of an embodiment of the present invention, FIG. 2 is an enlarged view of the boundary between the main pattern and the dummy pattern, and FIG. 3 is an element diagram of an FET. Fig. 4 shows a pattern in which the coarse/dense dependence was investigated in selective growth, and Fig. 5 shows the results of an experiment using Fig. 4. 1...G a As substrate crystal, 101.102...
- Peripheral circuit pattern, 200...Memory cell pattern, 300...Dummy pattern.
Claims (1)
ＷＳｉ＿ｘなどからなる材質で構成されている半導体基
板結晶を用いて、化合物半導体表面のみに選択的に成長
層を形成して集積回路を構成する工程において、本パタ
ーンの近傍にダミーパターンを設けて、どちらのパター
ンにも化合物半導体を選択成長させたことを特徴とする
化合物半導体集積回路。 ２、化合物半導体としてＧａＡｓを用いることを特徴と
する第１項記載の化合物半導体集積回路。 ３、上記本パターンに近傍するダミーパターンは少なく
とも１００μｍ以内で配置されていることを特徴とする
第１項、第２項記載の化合物半導体集積回路。[Claims] 1. The surface of the compound semiconductor is a compound semiconductor, SiO_2
In the process of forming an integrated circuit by selectively forming a growth layer only on the surface of a compound semiconductor using a semiconductor substrate crystal made of a material such as WSi_x, a dummy pattern is provided near the main pattern, A compound semiconductor integrated circuit characterized in that a compound semiconductor is selectively grown in both patterns. 2. The compound semiconductor integrated circuit according to item 1, characterized in that GaAs is used as the compound semiconductor. 3. The compound semiconductor integrated circuit according to items 1 and 2, wherein the dummy patterns adjacent to the main pattern are arranged within at least 100 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62068817A JP2828974B2 (en) | 1987-03-25 | 1987-03-25 | Method for manufacturing compound semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62068817A JP2828974B2 (en) | 1987-03-25 | 1987-03-25 | Method for manufacturing compound semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63236313A true JPS63236313A (en) | 1988-10-03 |
| JP2828974B2 JP2828974B2 (en) | 1998-11-25 |
Family
ID=13384643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62068817A Expired - Fee Related JP2828974B2 (en) | 1987-03-25 | 1987-03-25 | Method for manufacturing compound semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2828974B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01228186A (en) * | 1988-03-09 | 1989-09-12 | Sumitomo Electric Ind Ltd | Semiconductor selective growth method |
| US5782979A (en) * | 1993-04-22 | 1998-07-21 | Mitsubishi Denki Kabushiki Kaisha | Substrate holder for MOCVD |
| KR100504940B1 (en) * | 2000-12-29 | 2005-08-03 | 주식회사 하이닉스반도체 | Method of forming a selective monocrystal silicon film in a semiconductor device |
| US7554139B2 (en) | 2004-04-30 | 2009-06-30 | Panasonic Corporation | Semiconductor manufacturing method and semiconductor device |
| WO2010103792A1 (en) * | 2009-03-11 | 2010-09-16 | 住友化学株式会社 | Semiconductor substrate, method for manufacturing semiconductor substrate, electronic device and method for manufacturing electronic device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57196542A (en) * | 1981-05-28 | 1982-12-02 | Fujitsu Ltd | Semiconductor integrated circuit device and manufacture thereof |
-
1987
- 1987-03-25 JP JP62068817A patent/JP2828974B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57196542A (en) * | 1981-05-28 | 1982-12-02 | Fujitsu Ltd | Semiconductor integrated circuit device and manufacture thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01228186A (en) * | 1988-03-09 | 1989-09-12 | Sumitomo Electric Ind Ltd | Semiconductor selective growth method |
| US5782979A (en) * | 1993-04-22 | 1998-07-21 | Mitsubishi Denki Kabushiki Kaisha | Substrate holder for MOCVD |
| KR100504940B1 (en) * | 2000-12-29 | 2005-08-03 | 주식회사 하이닉스반도체 | Method of forming a selective monocrystal silicon film in a semiconductor device |
| US7554139B2 (en) | 2004-04-30 | 2009-06-30 | Panasonic Corporation | Semiconductor manufacturing method and semiconductor device |
| WO2010103792A1 (en) * | 2009-03-11 | 2010-09-16 | 住友化学株式会社 | Semiconductor substrate, method for manufacturing semiconductor substrate, electronic device and method for manufacturing electronic device |
| JP2010239130A (en) * | 2009-03-11 | 2010-10-21 | Sumitomo Chemical Co Ltd | Semiconductor substrate, method for manufacturing semiconductor substrate, electronic device, and method for manufacturing electronic device |
| US8823141B2 (en) | 2009-03-11 | 2014-09-02 | Sumitomo Chemical Company, Limited | Semiconductor wafer, method of producing semiconductor wafer, electronic device, and method of producing electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2828974B2 (en) | 1998-11-25 |
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