JPS63232458A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS63232458A JPS63232458A JP62067383A JP6738387A JPS63232458A JP S63232458 A JPS63232458 A JP S63232458A JP 62067383 A JP62067383 A JP 62067383A JP 6738387 A JP6738387 A JP 6738387A JP S63232458 A JPS63232458 A JP S63232458A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- groove
- substrate
- type
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 239000003990 capacitor Substances 0.000 claims abstract description 11
- 238000003860 storage Methods 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 4
- 239000010408 film Substances 0.000 description 22
- 238000009792 diffusion process Methods 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052810 boron oxide Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
- H01L29/945—Trench capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体記憶装置に関し、特にシリコン等の半導
体基板表面に凹凸を設けて基板表面積を実効的に増加し
た三次元構造をもったダイナミックメモリー半導体記憶
装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, and in particular to a dynamic memory having a three-dimensional structure in which unevenness is provided on the surface of a semiconductor substrate such as silicon to effectively increase the substrate surface area. This invention relates to semiconductor memory devices.
従来のダイナミックメモリー半導体記憶装置として、例
えば、半導体基板表面に設けられた微細な溝表面に絶縁
膜を設け、その上から溝内部に充填した電極材を電荷蓄
積部としながら、溝内部の基板表面を蓄積モードで動作
させるものがある。In a conventional dynamic memory semiconductor storage device, for example, an insulating film is provided on the surface of a fine groove provided on the surface of a semiconductor substrate, and an electrode material filled inside the groove is used as a charge storage part, and the substrate surface inside the groove is There are some that operate in storage mode.
この半導体記憶装置によれば、基板表面の不純物濃度を
高くすることにより、基板表面の空乏層のひろがりによ
ってＭＯＳ容量が減少するのを防ぐようにしている。According to this semiconductor memory device, the impurity concentration on the substrate surface is increased to prevent the MOS capacitance from decreasing due to the expansion of the depletion layer on the substrate surface.
しかし、従来の半導体記憶装置によれば、基板表面の不
純物濃度を高くして使っているのでＭＯＳ Ｆ ＥＴの
基板電位特性が悪化する欠点がある。この場合、溝内壁
のみを高濃度化すればこの問題は起こらないが、実現す
るプロセスが難しい。However, the conventional semiconductor memory device uses a high impurity concentration on the substrate surface, which has the disadvantage of deteriorating the substrate potential characteristics of the MOS FET. In this case, this problem will not occur if only the inner wall of the groove is made highly concentrated, but the process for realizing this is difficult.
本発明は上記に鑑みてなされたものであり、基板電位特
性を悪化させないでＭＯＳ容量を増加させるため半導体
基板表面に二種類の溝を設ける。第一種の溝はその内側
表面の中間部に設けられた絶縁厚膜とチャンネルストッ
パーとからなる分離領域をはさんで底部側の内部表面に
基板、容量絶縁薄膜、及び良導体の容量電極からなり少
なくとも基板側の一部に基板と逆導電性の第一の埋込電
極を設けたＭＯＳ容量と、開口部側の内側表面乃至基板
表面にあって前記容量電極と電気的に接続された基板と
逆導電性の第一電極とを有する。The present invention has been made in view of the above, and two types of grooves are provided on the surface of a semiconductor substrate in order to increase the MOS capacitance without deteriorating the substrate potential characteristics. The first type of groove consists of a substrate, a capacitive insulating thin film, and a capacitive electrode of good conductivity on the bottom inner surface, sandwiching a separation region made of a thick insulating film and a channel stopper provided in the middle part of the inner surface. a MOS capacitor provided with a first buried electrode having conductivity opposite to that of the substrate on at least a part of the substrate side; and a substrate electrically connected to the capacitor electrode on the inner surface on the opening side or the substrate surface. and a first electrode of opposite conductivity.
第二種の溝は開口部付近の内壁表面乃至基板表面に基板
と逆導電性のソース・ドレインの一方としての第二の電
極、底部側に内部表面に接する基板と逆導電性のソース
・ドレインの他方としての第二の埋込電極、および溝内
壁表面に設けられたゲート絶縁薄膜及びゲート電極とし
ての良導体からなるｌ’１ＯｓＦＢＴを構成する。この
第一種及び第二種の溝はアレイ状に配置され、第−及び
第二の埋込電極は、基板と逆導電性の第三の埋込電極に
よって架橋されている。第一種の溝は容量電極を電荷蓄
積部とする一つの記憶ノードとなり、情報が第一電極を
通じて書き込み或いは読み出しされる。第二の溝はゲー
ト電極に
ＭＯＳＦＥＴを反転させる電位を印加し、第二の電極に
与えられた電位及び電荷をこの反転層、第二〇埋込電極
、及び第三〇埋込電極を介して第一の埋込電極に与える
ようになっている。The second type of groove has a second electrode as one of a source/drain with conductivity opposite to the substrate on the inner wall surface or the surface of the substrate near the opening, and a source/drain with conductivity opposite to the substrate in contact with the inner surface on the bottom side. A l'1OsFBT is constituted by a second buried electrode as the other, a gate insulating thin film provided on the surface of the inner wall of the trench, and a good conductor as the gate electrode. The first type and second type of grooves are arranged in an array, and the first and second buried electrodes are bridged by a third buried electrode having conductivity opposite to that of the substrate. The first type of groove serves as one storage node using the capacitor electrode as a charge storage section, and information is written or read through the first electrode. The second groove applies a potential to invert the MOSFET to the gate electrode, and transfers the potential and charge given to the second electrode through this inversion layer, the 20th buried electrode, and the 30th buried electrode. It is adapted to be applied to the first implanted electrode.
本発明の半導体記憶装置によれば、溝内の基板表面に反
転層を形成し、絶縁膜を介して構内部に埋められた電荷
蓄積部としての容量電極の対極に用いる。これによって
、基板表面の不純物濃度を高くすることなく、電荷蓄積
電極の使用電圧範囲でＭＯＳ容量を１００％使うことが
できる。この反転層に少数キャリアを供給するソースと
して、定電位に接続された基板と逆導電性の電極が、エ
ピタキシャル成長法あるいはウェル構造により基板深部
と表面の電気導電性を変え、溝がこの接合にまたがる深
さにまで達するようにして形成される。この場合に、ダ
イナミックＲＡＭメモリーセルのように、高密度にＭＯ
Ｓ Ｆ ＥＴ及びＭＯＳ容量を配した構造になるときは
、特性安定の為に必要なバックゲートバイアスを十分に
与えることができなくなる恐れがあるが、本発明では記
憶ノードとなる溝部分を格子点として格子状に連続した
埋込拡散層をソース電極とし、ＭＯＳ構造のバックゲー
トと基板深部とは同一導電性の半導体領域が連続するよ
うにしてこれを解決している。さらに、この場合、埋め
込み拡散層を定電位に接続する構造が必要になるが、本
発明では、溝内に埋め込まれた導伝物質をゲート電極と
し、溝底部付近に接するソース・ドレインの一方として
の埋込拡散層と基板表面に形成され定電位につながる基
板と逆導電性のソース・ドレインの他方としての領域に
またがる溝側壁部をゲート？Ｊ域とするＭＯＳ Ｆ Ｅ
Ｔとして形成された溝を用い、ゲート電極に定電位を印
加することによりゲート領域を反転して基板表面から埋
込拡散層に電位を供給する。According to the semiconductor memory device of the present invention, an inversion layer is formed on the surface of the substrate within the groove, and is used as a counter electrode of a capacitor electrode as a charge storage section buried within the structure with an insulating film interposed therebetween. As a result, 100% of the MOS capacity can be used within the operating voltage range of the charge storage electrode without increasing the impurity concentration on the substrate surface. As a source for supplying minority carriers to this inversion layer, an electrode with a conductivity opposite to the substrate connected to a constant potential changes the electrical conductivity between the deep part of the substrate and the surface by epitaxial growth or a well structure, and a groove spans this junction. It is formed in such a way that it reaches deep. In this case, like a dynamic RAM memory cell, MO
When creating a structure in which SFET and MOS capacitors are arranged, there is a risk that it will not be possible to provide a sufficient back gate bias to stabilize the characteristics. This problem is solved by using a buried diffusion layer that is continuous in a lattice shape as a source electrode, and that the back gate of the MOS structure and the deep part of the substrate are continuous semiconductor regions of the same conductivity. Furthermore, in this case, a structure is required to connect the buried diffusion layer to a constant potential, but in the present invention, the conductive material buried in the trench is used as a gate electrode, and one of the source and drain in contact with the bottom of the trench is used. A buried diffusion layer is formed on the substrate surface leading to a constant potential in the substrate and the trench sidewalls spanning the opposite conductive source/drain region as the other gate? MOS F E in J area
By applying a constant potential to the gate electrode using the trench formed as a T, the gate region is inverted and a potential is supplied from the substrate surface to the buried diffusion layer.
以下、本発明の半導体記憶装置を詳細に説明する。Hereinafter, the semiconductor memory device of the present invention will be explained in detail.
第１図より第１１図は本発明の一実施例による半導体記
憶装置を製造する工程を示す。1 to 11 show steps for manufacturing a semiconductor memory device according to an embodiment of the present invention.
晃ず、Ｐ型シリコン単結晶基板１の表面に、周知の技術
により、高濃度ボロンのチャンネルストッパー２、及び
膜厚４０００〜６０００人の二酸化硅素（Ｓｉｆｔ）
３からなる分離領域を作る。First, a channel stopper 2 of high concentration boron and silicon dioxide (Sift) with a film thickness of 4,000 to 6,000 are formed on the surface of a P-type silicon single crystal substrate 1 by a well-known technique.
Create a separation area consisting of 3.
次いで、基板表面の熱酸化により５００人程度のシリコ
ン酸化膜４、気相成長法により１μｍ厚のシリコン窒化
膜（ＳｉＪ４）５を全面に被着した後、周知の写真食刻
によりフォトレジスト６をマスクとして、窒化膜５、酸
化膜４及び基板ｌをエツチングし、基板１の表面から深
さ１．５μｍに達する第一の溝７を掘る。その後基板１
の法線に対して角度をつけたイオン注入法により、ボロ
ン８を？ｎ Ｔ内のみ、特に側壁部に重点的に導入する
（第１図）。Next, a silicon oxide film 4 with a thickness of approximately 500 layers is deposited by thermal oxidation of the substrate surface, and a silicon nitride film (SiJ4) 5 with a thickness of 1 μm is deposited on the entire surface by a vapor phase growth method, and then a photoresist 6 is deposited by well-known photolithography. Using a mask, the nitride film 5, oxide film 4, and substrate 1 are etched, and a first groove 7 reaching a depth of 1.5 μm is dug from the surface of the substrate 1. Then board 1
Boron 8 was implanted using an ion implantation method at an angle to the normal line of ? Introduce it only inside the nT, especially on the side wall (Fig. 1).
次に、溝７の側壁に素子分離領域を形成する。このため
、レジスト６を剥離除去してから基板表面の熱酸化を行
う。窒化膜５に覆われた基板表面は酸化されず、溝７の
壁面にだけ厚さ４０００〜８０００人の酸化膜９をつけ
ることができる。この段階で、周知の写真食刻によりフ
ォトレジスト１０をマスクとして、前工程と同様に、第
二の溝１１を深さ１．５μｍに形成する（第２図）。Next, an element isolation region is formed on the side wall of the groove 7. For this reason, thermal oxidation of the substrate surface is performed after the resist 6 is peeled off and removed. The substrate surface covered with the nitride film 5 is not oxidized, and an oxide film 9 having a thickness of 4,000 to 8,000 wafers can be formed only on the wall surface of the groove 7. At this stage, using the photoresist 10 as a mask, a second groove 11 with a depth of 1.5 μm is formed by well-known photolithography, as in the previous step (FIG. 2).
フォトレジスト１０を剥離除去した後、異方性のプラズ
マエツチングにより酸化膜を除去すると、第一の溝７の
内部の酸化膜９は底部のみ除去され、側壁部に残った形
にすることができる（第３図）。After the photoresist 10 is stripped and removed, the oxide film is removed by anisotropic plasma etching, so that only the bottom part of the oxide film 9 inside the first groove 7 is removed, leaving it on the sidewalls. (Figure 3).
この段階で、窒化膜５及び酸化膜９をマスクとして基板
１のエツチングを進め、第−及び第二の溝の両方を深さ
５μｍまで深くする。At this stage, the substrate 1 is etched using the nitride film 5 and the oxide film 9 as masks, and both the first and second grooves are deepened to a depth of 5 μm.
次に、溝の深さ方向に平行のイオン注入によって高濃度
のリン１２を溝の底部に導入する（第４図）。Next, high concentration phosphorus 12 is introduced into the bottom of the trench by ion implantation parallel to the depth direction of the trench (FIG. 4).
次に、不活性雰囲気中での熱処理によって、第一の溝７
と第二の溝１１間で、及び第一の溝７相互間で接続した
ひとつのｎ型拡散領域１３を形成する（第５図）。Next, the first groove 7 is formed by heat treatment in an inert atmosphere.
One n-type diffusion region 13 is formed between the second trench 11 and the first trench 7 (FIG. 5).
第一の溝７相髭の接続は、第６図に示すように、第一の
溝７を格子状に配置することによってなされる。このと
き、基板表面は深部から連続したＰ壁領域にすることが
できる。The connection of the first grooves 7 is achieved by arranging the first grooves 7 in a grid pattern, as shown in FIG. At this time, the substrate surface can be made into a continuous P wall region from the deep part.
次に、窒化膜°５を除去した後、熱酸化によって溝の内
壁部に厚さ２５０人の酸化膜４を形成する。これをＭＯ
Ｓ構造の絶縁膜として用いる。さらに、溝内にリンをド
ープした多結晶シリコン１５を埋め、これをＭＯＳ構造
の一方の電極として用いる。ここで写真食刻により、フ
ォトレジスト１６をマスクとしてヒ素１７を基板表面に
導入する（第７図）。Next, after removing the nitride film 5, an oxide film 4 with a thickness of 250 nm is formed on the inner wall of the trench by thermal oxidation. MO this
Used as an insulating film for S structure. Further, polycrystalline silicon 15 doped with phosphorus is filled in the trench and used as one electrode of the MOS structure. Here, arsenic 17 is introduced into the substrate surface by photolithography using the photoresist 16 as a mask (FIG. 7).
この後、第一の溝７内のポリシリコン１５とヒ素拡散層
１７とを接続するためフォトレジスト１８を用い写真食
刻により酸化膜４をエツチング除去する（第８図）。次
いで、リンをドープした膜厚５０００人のポリシリコン
１９を被着形成する（第９図）、これで、本発明の主要
部分が完成された。Thereafter, in order to connect the polysilicon 15 in the first trench 7 and the arsenic diffusion layer 17, the oxide film 4 is removed by photolithography using a photoresist 18 (FIG. 8). Next, a 5000 nm thick polysilicon layer 19 doped with phosphorus is deposited (FIG. 9), thus completing the main part of the present invention.
第一の溝７に於いては、溝内のポリシリコン１５が溝側
壁を環状にとり囲む分離領域８゜９によって溝底部の基
板表面と電気的に分離された表面のｎ型層と接続されて
いるが、第二の溝には分離領域がない。この第一の溝７
と第二の溝１１とは底部付近で、リンを拡散したｎ型拡
散領域１３により接続されている。In the first trench 7, the polysilicon 15 in the trench is connected to the n-type layer on the surface electrically isolated from the substrate surface at the bottom of the trench by an isolation region 8.9 that annularly surrounds the trench sidewall. However, there is no separation region in the second groove. This first groove 7
and the second groove 11 are connected near the bottom by an n-type diffusion region 13 in which phosphorus is diffused.
この後、次のようにして周知の技術により１トランジス
タ型メモリーセルができる。即ち、熱酸化により眉間絶
縁膜２０、及びゲート酸化膜２１を形成し、情報読み出
し書込用のトランスファーゲートのゲート電極２２を設
け（第１０図）、さらにソース・ドレイン２３を設け、
リンシリケートガラスの眉間膜２４、コンタクト孔２５
、及びアルミ薄膜の配線２６を設けて１トランジスタ型
ダイナミツクメモリーを完成する（第１１図）。第１１
図において、埋込電極１３は第１、第２、及び第３の埋
込電極１３ａ、１３ｂ、１３ｃより成っている。Thereafter, a one-transistor type memory cell is produced using a well-known technique as follows. That is, a glabellar insulating film 20 and a gate oxide film 21 are formed by thermal oxidation, a gate electrode 22 of a transfer gate for reading and writing information is provided (FIG. 10), and a source/drain 23 is further provided.
Phosphorsilicate glass glabellar membrane 24, contact hole 25
, and aluminum thin film wiring 26 are provided to complete a one-transistor type dynamic memory (FIG. 11). 11th
In the figure, the buried electrode 13 consists of first, second, and third buried electrodes 13a, 13b, and 13c.
以上説明したように、本発明の半導体記憶装置によれば
、電荷蓄積部に於て反転層を対極とすることにより電気
容量を増大でき、キャリア供給用の電極を網状の埋込拡
散層とすることにより基板表面にバックゲートを伝える
ことができ、埋込拡散層に電位を供給する部分を電荷蓄
積部と類似の溝構造とすることで製造プロセスを簡略化
できる効果がある。As explained above, according to the semiconductor memory device of the present invention, the electric capacity can be increased by using the inversion layer as a counter electrode in the charge storage section, and the carrier supplying electrode is formed as a network-shaped buried diffusion layer. This makes it possible to transmit the back gate to the substrate surface, and has the effect of simplifying the manufacturing process by making the part that supplies the potential to the buried diffusion layer a groove structure similar to the charge storage part.
第１図より第５図及び第７図より第１１図は本発明の一
実施例による半導体記憶装置の製造工程を示す縦断面図
、第６図は同じく平面図である。
符号の説明
１−・−・シリコン基板
２．８・−・−ポロン拡散層
３．４．９．１４．２０．２１−・・−酸化膜５・−一
一一一一窒化膜
６．１０．１６．１８・−・−フォトレジスト７．１ｔ
−−−ｍ＝・−溝 １２．１３− ・−リン拡散
層１５．１９．２２−・−・−ポリシリコン１７．２３
−−−−−一・セ素拡散層
２４−−−−−−・Ｐ Ｓ Ｇ ２５−−−−
−−・コンタクト２６・−・・−・−アルミ1 to 5 and FIGS. 7 to 11 are longitudinal sectional views showing the manufacturing process of a semiconductor memory device according to an embodiment of the present invention, and FIG. 6 is a plan view. Explanation of symbols 1--Silicon substrate 2.8--Poron diffusion layer 3.4.9.14.20.21--Oxide film 5--11111 Nitride film 6.10 .16.18--Photoresist 7.1t
---m=・-Groove 12.13- ・-Phosphorus diffusion layer 15.19.22--Polysilicon 17.23
------1.Cell diffusion layer 24-----P S G 25----
−−・Contact 26・−・・−・−Aluminum
Claims (1)
ノードとしての電極を有する第一種の溝と、前記第一種
の溝によって構成されるアレイ状のパターンの一部とし
て、或いはその外縁部に配置して設けられたＭＯＳＦＥ
Ｔを有する第二種の溝と、前記第一種の溝の ＭＯＳ容量部の少なくとも一部分に接して前記半導体基
板内部で網状にひろがり、前記第二種の溝のＭＯＳＦＥ
Ｔのソース・ドレインの一方に連続する前記半導体基板
と逆導電性の埋込電極とからなり、 前記第一種の溝は前記ＭＯＳ容量を溝底部 側に、前記電位ノードとしての電極を溝開口部側乃至開
口部近傍の基板表面に、絶縁厚膜及び前記半導体基板と
同導電性のチャンネルストッパーとからなる前記分離領
域を溝中間部にそれぞれ有し、前記ＭＯＳ容量の容量電
極は前記電位ノードとしての電極と電気的に接続されて
電荷蓄積部を構成し、 前記第二種の溝は前記ＭＯＳＦＥＴのソー ス・ドレインの一方となる電位供給端子を溝開口部側乃
至開口部近傍の基板表面に、前記埋込電極と連結してソ
ース・ドレインの他方の電極となる埋込電極を溝底部側
にそれぞれ有し、 前記ＭＯＳＦＥＴを強反転状態にする電位 を前記ＭＯＳＦＥＴのゲートに印加して前記電位供給端
子の電位を前記埋込電極に伝達させた動作状態に於て、
アレイ状に配置された前記第一種の溝の前記電位ノード
としての電極に対して電位の書き込み・読み出しを行う
ことを特徴とする半導体記憶装置。[Scope of Claims] A first type of groove provided in an array in a semiconductor substrate and having a MOS capacitor, an isolation region, and an electrode as a potential node having conductivity opposite to that of the semiconductor substrate; and the first type of groove. MOSFEs provided as part of an array pattern formed by or arranged at the outer edge of the array pattern
a second type of groove having a T, and a MOSFE of the second type of groove extending in a net shape inside the semiconductor substrate in contact with at least a portion of the MOS capacitor portion of the first type of groove;
The semiconductor substrate and a buried electrode of opposite conductivity are continuous to one of the source and drain of the T, and the first type trench has the MOS capacitor on the trench bottom side and the electrode as the potential node in the trench opening. The isolation region, which is made of an insulating thick film and a channel stopper having the same conductivity as the semiconductor substrate, is provided on the surface of the substrate near the opening or in the middle of the groove, and the capacitor electrode of the MOS capacitor is connected to the potential node. The second type of trench is electrically connected to an electrode of the MOSFET to form a charge storage section, and the second type trench connects a potential supply terminal, which becomes one of the source and drain of the MOSFET, to the substrate surface on the trench opening side or in the vicinity of the opening. , each having a buried electrode connected to the buried electrode to serve as the other source/drain electrode on the bottom side of the trench, and applying a potential that brings the MOSFET into a strongly inverted state to the gate of the MOSFET to change the potential. In an operating state in which the potential of the supply terminal is transmitted to the embedded electrode,
A semiconductor memory device characterized in that a potential is written to and read from an electrode as the potential node of the first type groove arranged in an array.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62067383A JP2668873B2 (en) | 1987-03-20 | 1987-03-20 | Semiconductor storage device |
| DE3851649T DE3851649T2 (en) | 1987-03-20 | 1988-03-18 | Dynamic random access memory device composed of a plurality of single transistor cells. |
| EP88104391A EP0283964B1 (en) | 1987-03-20 | 1988-03-18 | Dynamic random access memory device having a plurality of improved one-transistor type memory cells |
| US07/171,094 US4969022A (en) | 1987-03-20 | 1988-03-21 | Dynamic random access memory device having a plurality of improved one-transistor type memory cells |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62067383A JP2668873B2 (en) | 1987-03-20 | 1987-03-20 | Semiconductor storage device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63232458A true JPS63232458A (en) | 1988-09-28 |
| JP2668873B2 JP2668873B2 (en) | 1997-10-27 |
Family
ID=13343432
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62067383A Expired - Fee Related JP2668873B2 (en) | 1987-03-20 | 1987-03-20 | Semiconductor storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2668873B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5363327A (en) * | 1993-01-19 | 1994-11-08 | International Business Machines Corporation | Buried-sidewall-strap two transistor one capacitor trench cell |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58213464A (en) * | 1982-06-04 | 1983-12-12 | Nec Corp | Semiconductor device |
| JPS62208662A (en) * | 1986-03-07 | 1987-09-12 | Sony Corp | Semiconductor memory |
| JPS63136559A (en) * | 1986-11-28 | 1988-06-08 | Hitachi Ltd | Semiconductor memory and manufacture thereof |
-
1987
- 1987-03-20 JP JP62067383A patent/JP2668873B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58213464A (en) * | 1982-06-04 | 1983-12-12 | Nec Corp | Semiconductor device |
| JPS62208662A (en) * | 1986-03-07 | 1987-09-12 | Sony Corp | Semiconductor memory |
| JPS63136559A (en) * | 1986-11-28 | 1988-06-08 | Hitachi Ltd | Semiconductor memory and manufacture thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5363327A (en) * | 1993-01-19 | 1994-11-08 | International Business Machines Corporation | Buried-sidewall-strap two transistor one capacitor trench cell |
| US5571743A (en) * | 1993-01-19 | 1996-11-05 | International Business Machines Corporation | Method of making buried-sidewall-strap two transistor one capacitor trench cell |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2668873B2 (en) | 1997-10-27 |
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