JPS6322462B2 - - Google Patents

Info

Publication number
JPS6322462B2
JPS6322462B2 JP56088662A JP8866281A JPS6322462B2 JP S6322462 B2 JPS6322462 B2 JP S6322462B2 JP 56088662 A JP56088662 A JP 56088662A JP 8866281 A JP8866281 A JP 8866281A JP S6322462 B2 JPS6322462 B2 JP S6322462B2
Authority
JP
Japan
Prior art keywords
bonding pad
present
film
base ribbon
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56088662A
Other languages
Japanese (ja)
Other versions
JPS57202750A (en
Inventor
Mototaka Kamoshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP56088662A priority Critical patent/JPS57202750A/en
Publication of JPS57202750A publication Critical patent/JPS57202750A/en
Publication of JPS6322462B2 publication Critical patent/JPS6322462B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8536—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/85375—Bonding interfaces of the semiconductor or solid state body having an external coating, e.g. protective bond-through coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に係わり、特に
高湿度に耐え得る半導体装置の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device that can withstand high humidity.

従来、半導体装置の耐湿性を向上させるために
は、例えば、チツプ上の表面保護膜を高耐湿性材
料にする方法等がとられている。これは、例え
ば、昭和53年11月27日に日経マグロウヒル社より
発行された「日径エレクトロニクス」誌、第200
号、第173頁からの特集記事「LSIの信頼性を向
上させる半導体プロセス技術―パシベーシヨン技
術を中心に見る―」にて、特に第176〜177頁の表
１に詳細にまとめられている。即ち同表によると
例えばスパツタ法で付着せしめた二酸化珪素膜と
か、プラズマ気相成長法で付着させた窒化硅素膜
等が該高耐湿性の保護膜パツシベーシヨン材料と
して知られている。 Conventionally, in order to improve the moisture resistance of semiconductor devices, methods have been adopted, such as using a highly moisture resistant material as a surface protective film on a chip. This is, for example, the 200th issue of "Nippon Electronics" magazine published by Nikkei McGraw-Hill on November 27, 1978.
The special feature article ``Semiconductor process technology to improve LSI reliability - Focusing on passivation technology'' from page 173 of the issue provides a detailed summary, especially in Table 1 on pages 176-177. That is, according to the table, for example, a silicon dioxide film deposited by a sputtering method, a silicon nitride film deposited by a plasma vapor deposition method, etc. are known as highly moisture-resistant protective film passivation materials.

然るにこのような高耐湿性材料をチツプの表面
保護膜に使用しても、保護されている部分はこれ
で良いが、チツプから外部へリード線を接続する
ボンデイングパツド部は金属配線部が露出されて
いるので、ボンデイングパツド部の耐湿性を向上
させる所迄は至らない。そのため一般には、湿度
に対して無防備なモールド材料を水分が透湿し、
水分とボンデイングパツド部を構成する金属とが
反応し、断線等の事故に至るという欠点があつ
た。 However, even if such a highly moisture-resistant material is used as a surface protection film for a chip, the protected part is fine, but the metal wiring part of the bonding pad that connects the lead wire from the chip to the outside is exposed. Therefore, it is not possible to improve the moisture resistance of the bonding pad portion. Therefore, in general, moisture permeates through the mold material, which is unprotected against humidity.
The drawback was that moisture reacted with the metal forming the bonding pad, leading to accidents such as wire breakage.

本発明の目的はこのような欠点を解消し、耐湿
性の高い半導体装置の製造方法を提供することに
ある。 An object of the present invention is to eliminate such drawbacks and provide a method for manufacturing a semiconductor device with high moisture resistance.

本発明の特徴はボンデイングパツドにリード線
を接続した後、ボンデイングパツドを構成する金
属面を陽極酸化法により酸化する工程を含むこと
にある。 A feature of the present invention is that it includes a step of oxidizing the metal surface constituting the bonding pad by anodizing after connecting the lead wire to the bonding pad.

本発明の原理はボンデイングパツド金属上を該
金属の酸化物で被覆すると耐湿性が著しく改善さ
れるという新規な発見に基づく。 The principle of the present invention is based on the novel discovery that coating a bonding pad metal with an oxide of the metal significantly improves moisture resistance.

本発明により、半導体装置の耐湿性に顕著な改
善が見られる。例えば、通常のモールド樹脂封止
したアルミニウム配線によるシリコンプレーナ集
積回路にて、本発明に適用により、温度85℃、湿
度85％の環境試験にて200時間内に不合格となる
集積回路の発生率が激減した。 According to the present invention, significant improvement can be seen in the moisture resistance of semiconductor devices. For example, by applying the present invention to silicon planar integrated circuits made of aluminum wiring sealed with ordinary molded resin, the incidence of integrated circuits that fail within 200 hours in an environmental test at a temperature of 85°C and a humidity of 85%. decreased sharply.

次に本発明の実施例を図面を参照して説明す
る。 Next, embodiments of the present invention will be described with reference to the drawings.

先ず比較のため、第１図に従来のシリコン集積
回路の一部の断面図を示した。即ち従来品では、
例えば、シリコン基板１０１に所望のpn接合１
０２を形成した後、絶縁膜１０３を介して電極配
線材料を付着し、選択的にエツチング加工して配
線１０４を形成し、然る後に保護膜、例えばプラ
ズマ中での化学反応を利用した気相成長法による
窒化シリコン膜１０５を付着させる。その後、配
線１０４と外部端子との接続部であるボンデイン
グパツド部１０６の上の窒化硅素膜１０５を選択
的に除去し、そこにリード線１０７を接続する。
この従来品ではボンデイングパツド部１０６の上
には保護膜が無いので、外部からの水分と配線材
料との反応が起こり易い。 First, for comparison, FIG. 1 shows a cross-sectional view of a part of a conventional silicon integrated circuit. In other words, with conventional products,
For example, a desired pn junction 1 is placed on the silicon substrate 101.
After forming 02, an electrode wiring material is deposited through an insulating film 103, selectively etched to form a wiring 104, and then a protective film is formed, for example, in a vapor phase using a chemical reaction in plasma. A silicon nitride film 105 is deposited by a growth method. Thereafter, the silicon nitride film 105 on the bonding pad portion 106, which is the connecting portion between the wiring 104 and the external terminal, is selectively removed, and a lead wire 107 is connected thereto.
Since this conventional product does not have a protective film on the bonding pad portion 106, a reaction between moisture from the outside and the wiring material is likely to occur.

それに対し第２図は本発明の一実施例の工程を
示す断面図である。即ち第２図Ａの通り、通常の
如くｐ型シリコン基板２０１を用意し、その上に
絶縁膜、例えば二酸化シリコン膜２０２を形成
し、選択的に孔をあけてｎ型不純物をｐ型シリコ
ン基板２０１内に添加してpn接合２０３を形成
した後、酸化を続け、ｎ型不純物を添加した領域
のシリコン基板２０１の表面を再度二酸化シリコ
ン膜２０４で被覆する。必要に応じてこの一連の
工程を数回繰り返し、所望の構成の半導体集積回
路のチツプ内部加工を終了させる。然る後に、所
望のコンタクト用孔２０５を開け、電極配線材
料、例えばアルミニウムを蒸着法で付着せしめ、
選択エツチング加工を施し、配線２０６を形成す
る。その後酸素プラズマ法によりアルミニウムの
配線２０６上に約300〜1000Åのアルミナ膜２０
７を形成し然る後にこれもプラズマ法によりシラ
ンとアンモニアの化学反応による気相成長法を用
いて窒化シリコン膜２０８を形成する。その後ボ
ンデイングパツド部２０９上の窒化シリコン膜２
０８を除去する。次いで第２図Ｂのように先のア
ルミナ膜２０７を突き破つてリード線２１０をボ
ンデイングパツドに接続する。第１図の場合と異
なりボンデイングパツド部２０９のアルミニウム
上にアルミナ膜２０７が残つている点が特徴であ
る。 On the other hand, FIG. 2 is a sectional view showing the steps of an embodiment of the present invention. That is, as shown in FIG. 2A, a p-type silicon substrate 201 is prepared as usual, an insulating film, for example, a silicon dioxide film 202 is formed on it, and holes are selectively formed to inject n-type impurities into the p-type silicon substrate. After doping into the silicon substrate 201 to form a pn junction 203, oxidation is continued, and the surface of the silicon substrate 201 in the region to which the n-type impurity has been added is again covered with a silicon dioxide film 204. This series of steps is repeated several times as necessary to complete the internal processing of the chip of the semiconductor integrated circuit having the desired configuration. After that, a desired contact hole 205 is opened, and an electrode wiring material, such as aluminum, is deposited by vapor deposition.
Selective etching is performed to form wiring 206. After that, an alumina film 20 of approximately 300 to 1000 Å is coated on the aluminum wiring 206 using an oxygen plasma method.
After forming 7, a silicon nitride film 208 is formed using a vapor phase growth method using a chemical reaction between silane and ammonia, also using a plasma method. After that, the silicon nitride film 2 on the bonding pad portion 209 is
Remove 08. Next, as shown in FIG. 2B, the lead wire 210 is connected to the bonding pad by breaking through the alumina film 207. Unlike the case shown in FIG. 1, this embodiment is characterized in that the alumina film 207 remains on the aluminum of the bonding pad portion 209.

第３図は本発明の実施のため、先述の工程を変
更した例である。即ちここではボンデイングパツ
ド部３０１上の窒化シリコン膜３０２を除去し、
アルミニウム配線３０３の表面をボンデイングパ
ツド部３０１では従来通り露出した状態でリード
線３０４をボンデイング接続し、然る後にベース
リボンと共に酸素プラズマ中に入れて、ボンデイ
ングパツドで露出していたアルミニウム配線３０
３の表面をアルミナ膜３０５に変換し、その後モ
ールド材料で封止を行う。ここでアルミナ膜に変
換するには通常の如く、圧力10-6Torrにした中
に酸素を10-3Torrほど導入し、ベースリボンに
陽極電圧を印加してプラズマを発生させ、陽極酸
化を行えばよい。この段階のベースリボンは全体
が同電圧になつている半導体チツプに電圧が印加
されることなくボンデイングパツドの露出してい
るアルミニウムのみ容易にアルミナに変換でき
る。 FIG. 3 shows an example in which the above-described steps are modified to implement the present invention. That is, here, the silicon nitride film 302 on the bonding pad portion 301 is removed, and
The lead wire 304 is bonded to the bonding pad portion 301 with the surface of the aluminum wiring 303 exposed as before, and then placed in oxygen plasma together with the base ribbon to remove the aluminum wiring 30 that was exposed at the bonding pad.
3 is converted into an alumina film 305, and then sealed with a molding material. To convert this into an alumina film, as usual, approximately 10 -3 Torr of oxygen is introduced into a pressure of 10 -6 Torr, an anodic voltage is applied to the base ribbon to generate plasma, and anodization is performed. That's fine. At this stage, only the exposed aluminum of the bonding pad can be easily converted into alumina without applying a voltage to the semiconductor chip whose entire base ribbon is at the same voltage.

第４図は本発明の半導体装置を自動的に製造す
る装置を模式的に示すものである。即ち通常の如
き自動マウンター部４０１から自動ボンデイング
部４０２に、ベースリボンキヤリア４０３からベ
ースリボン４０４がベルト４０５で順次運ばれ、
自動ボンデイングを終了したベースリボン４０６
は真空ベルジヤー４０７に移され、そこで真空ポ
ンプ４０８で排気され一度高真空（10-6Torr）
にされたあと、酸素４０９を10-3Torrほど導入
し１分間ほど陽極酸化されて出て来るという構造
になつている。真空になるベルジヤー４０７の体
積は微小なのでこの加工は一つのベースリボンが
自動ボンデイングされている内に終了するため、
時間的には従来の自動ボンデイング工程が律速
し、一工程の増加は加工時間の増大につながらな
くて済む。 FIG. 4 schematically shows an apparatus for automatically manufacturing a semiconductor device according to the present invention. That is, a base ribbon 404 is sequentially conveyed from a base ribbon carrier 403 to an automatic bonding section 402 from a conventional automatic mounter section 401 by a belt 405.
Base ribbon 406 after automatic bonding
is transferred to a vacuum bell gear 407, where it is evacuated by a vacuum pump 408 and once brought to a high vacuum (10 -6 Torr).
After that, oxygen 409 is introduced at about 10 -3 Torr, and the structure is such that it is anodized for about 1 minute and then comes out. Since the volume of the bell gear 407 that becomes evacuated is minute, this processing is completed while one base ribbon is automatically bonded.
In terms of time, the conventional automatic bonding process is rate-limiting, and the addition of one process does not lead to an increase in processing time.

第５図は本発明の実施例によ温度85℃、湿度85
％に於ける環境試験後のpn接合の逆方向電流を
測定したものである。従来品Ａでは約100時間後
に逆方向電流が増加していたが、本発明品Ｂでは
300〜350時間後になる迄耐えており耐湿性の向上
が著しい。 Figure 5 shows an embodiment of the present invention at a temperature of 85°C and a humidity of 85°C.
This is a measurement of the reverse current of the p-n junction after an environmental test at %. In conventional product A, the reverse current increased after about 100 hours, but in product B of the present invention, the reverse current increased.
It withstood up to 300 to 350 hours, and the moisture resistance was significantly improved.

以上本発明の実施例としてシリコンの集積回路
について記述したが、これは砒化ガリウムなど他
の半導体素子でも有効であり、又、配線材料とし
てアルミニウムの場合を主に説明したが、本発明
は単にアルミニウム製ボンデイングパツドのみで
なく、アルミニウムにシリコンや銅などの不純物
が入つている材料でもよく、又、モリブデンやク
ロム、タングステンなどの金属でもよい。更に
又、硅化物の上に金属が重ねられている配線材料
でもよい。 Although a silicon integrated circuit has been described as an embodiment of the present invention, this is also effective for other semiconductor devices such as gallium arsenide, and although the case where aluminum is used as the wiring material has been mainly explained, the present invention is not limited to just aluminum. In addition to the bonding pad made of aluminum, it may also be made of aluminum containing impurities such as silicon or copper, or it may be made of metal such as molybdenum, chromium, or tungsten. Furthermore, a wiring material in which metal is layered on silicide may also be used.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は比較のために掲げた従来品の断面図、
第２図Ａ及Ｂは本発明の一実施例を工程順に説明
するための断面図、更に第３図は本発明の他の実
施例を説明するための断面図、第４図は本発明の
実施例を製造する装置の一例を示す図、第５図は
本発明の一実施例の効果を従来品と比較して説明
するための図である。 主な記号、１０１，２０１……シリコン基板、
１０２，２０３……pn接合、１０３……絶縁膜、
１０４，２０６，３０３……配線、１０５，２０
８，３０２……窒化シリコン膜、１０６，２０
９，３０１……ボンデイングパツド部、１０７，
２１０，３０４……リード線、２０２，２０４…
…二酸化シリコン膜、２０５……コンタクト用
孔、２０７，３０５……アルミナ膜、４０１……
自動マウンター部、４０２……自動ボンデイング
部、４０３……ベースリボンキヤリア、４０４，
４０６……ベースリボン、４０５……ベルト、４
０７……ベルジヤー。 Figure 1 is a cross-sectional view of the conventional product shown for comparison.
2A and 2B are cross-sectional views for explaining one embodiment of the present invention in the order of steps, FIG. 3 is a cross-sectional view for explaining another embodiment of the present invention, and FIG. 4 is a cross-sectional view for explaining another embodiment of the present invention. FIG. 5 is a diagram showing an example of an apparatus for manufacturing the embodiment, and is a diagram for explaining the effects of the embodiment of the present invention in comparison with a conventional product. Main symbols: 101, 201...silicon substrate,
102, 203... pn junction, 103... insulating film,
104,206,303...Wiring, 105,20
8,302...Silicon nitride film, 106,20
9,301...Bonding pad part, 107,
210, 304... Lead wire, 202, 204...
...Silicon dioxide film, 205...Contact hole, 207, 305...Alumina film, 401...
automatic mounter section, 402... automatic bonding section, 403... base ribbon carrier, 404,
406...Base ribbon, 405...Belt, 4
07...Berjiya.

Claims (1)

【特許請求の範囲】[Claims] １ 半導体チツプのボンデイングパツド上の絶縁
保護膜を選択的に除去する工程と、前記半導体チ
ツプをベースリボンに搭載する工程と、前記ボン
デイングパツドと前記ベースリボンのリード部と
をリード線で接続する工程と、前記リード線接続
部以外のボンデイングパツド部の表面を、前記ベ
ースリボンを陽極とする酸素プラズマ中の陽極酸
化法により酸化して酸化膜を形成する工程を含む
ことを特徴とする半導体装置の製造方法。1. A step of selectively removing an insulating protective film on a bonding pad of a semiconductor chip, a step of mounting the semiconductor chip on a base ribbon, and a step of connecting the bonding pad and the lead portion of the base ribbon with a lead wire. and forming an oxide film by oxidizing the surface of the bonding pad portion other than the lead wire connection portion by an anodic oxidation method in oxygen plasma using the base ribbon as an anode. A method for manufacturing a semiconductor device.
JP56088662A 1981-06-09 1981-06-09 Semiconductor device and manufacture thereof Granted JPS57202750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56088662A JPS57202750A (en) 1981-06-09 1981-06-09 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56088662A JPS57202750A (en) 1981-06-09 1981-06-09 Semiconductor device and manufacture thereof

Publications (2)

Publication Number Publication Date
JPS57202750A JPS57202750A (en) 1982-12-11
JPS6322462B2 true JPS6322462B2 (en) 1988-05-12

Family

ID=13949026

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56088662A Granted JPS57202750A (en) 1981-06-09 1981-06-09 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS57202750A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002184720A (en) * 2000-12-15 2002-06-28 Murata Mfg Co Ltd Method of manufacturing device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5480679A (en) * 1977-12-09 1979-06-27 Nec Corp Manufacture for semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5480679A (en) * 1977-12-09 1979-06-27 Nec Corp Manufacture for semiconductor device

Also Published As

Publication number Publication date
JPS57202750A (en) 1982-12-11

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