JPS63224334A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63224334A JPS63224334A JP5801387A JP5801387A JPS63224334A JP S63224334 A JPS63224334 A JP S63224334A JP 5801387 A JP5801387 A JP 5801387A JP 5801387 A JP5801387 A JP 5801387A JP S63224334 A JPS63224334 A JP S63224334A
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- semiconductor element
- groove
- width
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 6
- 239000000919 ceramic Substances 0.000 abstract description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052737 gold Inorganic materials 0.000 abstract description 5
- 239000010931 gold Substances 0.000 abstract description 5
- 239000000853 adhesive Substances 0.000 abstract description 3
- 230000001070 adhesive effect Effects 0.000 abstract description 3
- 229910052759 nickel Inorganic materials 0.000 abstract description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229910000676 Si alloy Inorganic materials 0.000 description 3
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- -1 gold-tin-aluminum Chemical compound 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に絶縁性基板上の金属層
に半導体素子を固着してなる半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a semiconductor element is fixed to a metal layer on an insulating substrate.
従来、この種の半導体装ｌは、第４図に平面図を示すよ
うに、絶縁性のセラミック基板１ｄに設けたキャビティ
２ｄと称する凹部底面に金属層（アイランド）３ｄを設
け、この上に半導体素子４を固着し、更に、半導体素子
４の電極５とセラミック基板上のポンディングパッド６
とをアルミニウム又は金を主成分とするワイヤ７で結線
し、キャビティ２ｄ全域をキャップ（図示せず）で気密
封止して作られていた。Conventionally, this type of semiconductor device 1, as shown in a plan view in FIG. The element 4 is fixed, and the electrode 5 of the semiconductor element 4 and the bonding pad 6 on the ceramic substrate are bonded together.
The cavity 2d is connected with a wire 7 mainly composed of aluminum or gold, and the entire cavity 2d is hermetically sealed with a cap (not shown).
半導体素子４を金属層３ｄに固着するには、いくつかの
方法がある。１つは、金・シリコン合金や金・錫・アル
ミニウム合金を半導体素子４の下に敷いて加熱しながら
こすり合わせることによる方法である。他の一つは、合
金の代わりにエポキシやポリイミド系の樹脂を挟んでこ
すりながら接着し、加熱して効果させる方法である。い
ずれの方法においても、重要なのは半導体素子４と金属
層３ｄの間に気泡を含まないように固着する点である。There are several methods for fixing the semiconductor element 4 to the metal layer 3d. One method is to place a gold-silicon alloy or a gold-tin-aluminum alloy under the semiconductor element 4 and rub them together while heating. Another method is to sandwich and rub epoxy or polyimide resin instead of the alloy, bond it while rubbing it, and heat it to make it effective. In either method, what is important is that the semiconductor element 4 and the metal layer 3d be bonded together so as not to contain air bubbles.
しかし、上述した従来の半導体装置では、金属層は単な
る平面であるので、気泡が逃げにくいという欠点がある
。特に、近年の半導体素子はその寸法が大きくなってい
るので、気泡を完全に無くすことは不可能になっており
、最悪の場合は半導体素子は割れるという欠点がある。However, in the conventional semiconductor device described above, since the metal layer is simply a flat surface, there is a drawback that bubbles are difficult to escape. In particular, since the dimensions of recent semiconductor devices have become larger, it has become impossible to completely eliminate bubbles, and in the worst case, the semiconductor device has the drawback of cracking.
本発明の半導体装置は、絶縁性基板の表面に形成した金
属層と、該金属層上に固着した半導体素子とを備える半
導体装置において、前記金属層に前記半導体素子より外
部に導出され前記金属層を電気的に分断しないように形
成された溝を有している。The semiconductor device of the present invention includes a metal layer formed on the surface of an insulating substrate and a semiconductor element fixed on the metal layer, wherein the metal layer is led out from the semiconductor element into the metal layer. It has a groove formed so as not to electrically separate the
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例の平面図である。FIG. 1 is a plan view of a first embodiment of the invention.
第１図の、実施例は本発明をラインセンサに適用したも
ので、第１図に示すように、金属層３ａは絶縁性のセラ
ミック基板１ａ上のキャビティ２ａの全域に設けられて
いて、破線で示す金属層３ａの一部の半導体素子搭載領
域４ａ上に半導体素子が搭載される。金属層３ａ上には
半導体素子搭載領域４ａの幅方向に平行に複数の溝９ａ
が設けられる。The embodiment shown in FIG. 1 is an application of the present invention to a line sensor, and as shown in FIG. A semiconductor element is mounted on a part of the semiconductor element mounting region 4a of the metal layer 3a shown by . A plurality of grooves 9a are formed on the metal layer 3a in parallel to the width direction of the semiconductor element mounting area 4a.
will be provided.
満９ａの長さは半導体素子搭載領域４ａの幅より長くな
っていて、半導体素子を金属層３ａに固着したとき溝９
ａの先端が開口するようになっている。従って、半導体
素子と金属層３ａとの間に挟まれた気泡は溝９ａを通っ
て外部に逃げ、溝以外の領域と半導体素子とが完全密着
する。又、溝９ａの長さは金属層３ａの幅より短かくし
であるので金属層３ａが電気的に分断されることはなく
、後述する金属層３ａ表面のニッケル及び金の電解めっ
きが全面に可能である。The length of the groove 9a is longer than the width of the semiconductor element mounting area 4a, so that when the semiconductor element is fixed to the metal layer 3a, the groove 9a is longer than the width of the semiconductor element mounting area 4a.
The tip of a is open. Therefore, the air bubbles sandwiched between the semiconductor element and the metal layer 3a escape to the outside through the groove 9a, and the area other than the groove and the semiconductor element are in complete contact with each other. Further, since the length of the groove 9a is shorter than the width of the metal layer 3a, the metal layer 3a is not electrically separated, and electrolytic plating of nickel and gold on the surface of the metal layer 3a, which will be described later, can be performed on the entire surface. It is.
金属層３ａはアルミナシート上にタングステン粒子を分
散させたインクをスクリーン印刷し焼成した後、ニッケ
ルと金をめっきして形成するので、溝９ａはこの印刷パ
ターンを変えるだけで容易にできる。従って、溝９ａの
部分は金属層が無いので前述の金・シリコン合金や金・
錫・アルミニウム合金で半導体素子を固着する場合は、
半導体素子が浮くことになるが、溝９Ａは均一に配置し
てあり半導体素子への歪は一様に分布するので、半導体
素子が割れることはない。又、エポキシなどの接着剤を
用いて固着する場合は金属層が無くても接着するので、
このような問題はない。The metal layer 3a is formed by screen printing an ink containing tungsten particles dispersed on an alumina sheet, baking it, and then plating it with nickel and gold, so the grooves 9a can be easily formed by simply changing this printing pattern. Therefore, since there is no metal layer in the groove 9a, the above-mentioned gold-silicon alloy or gold-silicon alloy or gold
When fixing semiconductor elements with tin/aluminum alloy,
Although the semiconductor element will float, since the grooves 9A are uniformly arranged and the strain on the semiconductor element is evenly distributed, the semiconductor element will not be cracked. Also, if you use an adhesive such as epoxy to adhere, it will adhere even if there is no metal layer, so
There are no such problems.
第２図は本発明の第２の実施例の平面図である。FIG. 2 is a plan view of a second embodiment of the invention.
第２図の実施例は本発明をＰＧＡ （ビン・グリッド・
アレイ）型のパッケージに適用した場合で、ＰＧＡ型の
パッケージは特に１００ピンを超える半導体装置が多く
、半導体素子の寸法も１０龍を超えることがしばしばあ
る。The embodiment of FIG.
When applied to an array (array) type package, many PGA type packages include semiconductor devices having more than 100 pins, and the dimensions of semiconductor elements often exceed 10 pins.
このように大きな半導体素子では、それを搭載する絶縁
性基板の反りや、半導体素子の面積に対する外周の長さ
が小さいことにより、気泡が抜けにくい。In such a large semiconductor element, bubbles are difficult to escape due to the warpage of the insulating substrate on which it is mounted and the small length of the outer circumference relative to the area of the semiconductor element.
第２図に示すように、セラミック基板ｌｂ上に形成した
金属層３ｂに十字上の７１！９ｂを設けている。溝９ｂ
の十字の縦及び横方向の長さは半導体素子の寸法よりも
大きくし、第２図に破線で示す半導体素子搭載領域４ｂ
に半導体素子を搭載した時に、十字の満９ｂの先端が外
部に開口する、いわゆる開放型となついる。As shown in FIG. 2, a cross shape 71!9b is provided on the metal layer 3b formed on the ceramic substrate lb. Groove 9b
The vertical and horizontal lengths of the cross are larger than the dimensions of the semiconductor element, and the semiconductor element mounting area 4b shown in broken lines in FIG.
When a semiconductor element is mounted on the board, the tip of the cross 9b opens to the outside, which is a so-called open type.
溝９ｂは半導体素子をほぼ４等分するように配置されて
おり、実質的に気泡の抜は易さは半導体素子の寸法が１
／２になったのと同等である。表面のめっきはめっき用
引出部２１を介して行われる。The grooves 9b are arranged so as to roughly divide the semiconductor element into four equal parts, and the ease with which air bubbles can be effectively removed depends on the size of the semiconductor element being 1.
It is equivalent to becoming /2. Plating of the surface is performed via the plating draw-out section 21.
第３図は本発明の第３の実施例の平面図である。FIG. 3 is a plan view of a third embodiment of the invention.
第３図に示すように、溝９ｃの長さをセラミック基板１
ｃ上のキャビティ２Ｃの寸法以上に伸ばすことも可能で
ある。アルミナセラミック上のタングステン層はその上
に更にアルミナセラミックを積層するこのが可能で、キ
ャビテイ２ｃ外部のセラミック層間で電気的に導通させ
ることができる。As shown in FIG. 3, the length of the groove 9c is
It is also possible to extend it beyond the dimension of the cavity 2C on c. The tungsten layer on the alumina ceramic can further be laminated with an alumina ceramic, and electrical continuity can be established between the ceramic layers outside the cavity 2c.
第３図では、煩雑を避ける為にキャビテイ２Ｃ周囲のボ
ディングパッドは図示を省略しており、破線は金属層３
Ｃがアルミナセラミックの下にあることを示す。In FIG. 3, the boarding pad around the cavity 2C is omitted to avoid complication, and the broken line indicates the metal layer 3.
C is shown below the alumina ceramic.
以上説明したように本発明の半導体装置は、金属層に溝
を設けることにより、半導体素子と金属層に挟まれる接
着面に気泡なく半導体素子を固着でき、更に、大型の半
導体素子の搭載も可能となるという効果がある。As explained above, in the semiconductor device of the present invention, by providing a groove in the metal layer, the semiconductor element can be fixed without bubbles on the adhesive surface sandwiched between the semiconductor element and the metal layer, and furthermore, it is possible to mount a large semiconductor element. There is an effect that
第１図乃至第３図はそれぞれ本発明の第１乃至第３の実
施例の平面図、第４図は従来の半導体装置の一例の平面
図である。
１ａ〜１ｄ・・・セラミック基板、２ａ〜２ｄ・・・キ
ャビティ、３ａ〜３ｄ・・・金属層、４・・・半導体素
子、４ａ、４ｂ・・・半導体素子搭載領域、５・・・電
極、６・・・ポンディングパッド、７・・・ワイヤ、８
・・・外部リード、９ａ〜９（／・・・溝。
第１ 図
第２ 図1 to 3 are plan views of first to third embodiments of the present invention, respectively, and FIG. 4 is a plan view of an example of a conventional semiconductor device. 1a to 1d... Ceramic substrate, 2a to 2d... Cavity, 3a to 3d... Metal layer, 4... Semiconductor element, 4a, 4b... Semiconductor element mounting area, 5... Electrode, 6...Ponding pad, 7...Wire, 8
... External leads, 9a to 9 (/... grooves. Fig. 1 Fig. 2
Claims (1)
着した半導体素子とを備える半導体装置において、前記
金属層に前記半導体素子より外部に導出され前記金属層
を電気的に分断しないように形成された溝を有すること
を特徴とする半導体装置。In a semiconductor device comprising a metal layer formed on the surface of an insulating substrate and a semiconductor element fixed on the metal layer, a metal layer is provided in the metal layer so as not to be led out from the semiconductor element and electrically disconnect the metal layer. 1. A semiconductor device comprising a groove formed in a groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5801387A JPS63224334A (en) | 1987-03-13 | 1987-03-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5801387A JPS63224334A (en) | 1987-03-13 | 1987-03-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63224334A true JPS63224334A (en) | 1988-09-19 |
Family
ID=13072083
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5801387A Pending JPS63224334A (en) | 1987-03-13 | 1987-03-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63224334A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008109059A (en) * | 2006-10-27 | 2008-05-08 | Shinko Electric Ind Co Ltd | Method of packaging electronic component on substrate and method of forming solder face |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58118641A (en) * | 1982-01-08 | 1983-07-14 | Toshiba Corp | Radiation sensitive positive type resist for forming fine pattern |
| JPS5961055A (en) * | 1982-09-29 | 1984-04-07 | Toshiba Corp | Semiconductor device |
-
1987
- 1987-03-13 JP JP5801387A patent/JPS63224334A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58118641A (en) * | 1982-01-08 | 1983-07-14 | Toshiba Corp | Radiation sensitive positive type resist for forming fine pattern |
| JPS5961055A (en) * | 1982-09-29 | 1984-04-07 | Toshiba Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008109059A (en) * | 2006-10-27 | 2008-05-08 | Shinko Electric Ind Co Ltd | Method of packaging electronic component on substrate and method of forming solder face |
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