JPS63224258A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS63224258A JPS63224258A JP5705187A JP5705187A JPS63224258A JP S63224258 A JPS63224258 A JP S63224258A JP 5705187 A JP5705187 A JP 5705187A JP 5705187 A JP5705187 A JP 5705187A JP S63224258 A JPS63224258 A JP S63224258A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- thin film
- layer
- film transistor
- resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 26
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000011521 glass Substances 0.000 claims abstract description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 3
- 239000010408 film Substances 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000004973 liquid crystal related substance Substances 0.000 claims description 2
- 239000011159 matrix material Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 5
- 229920002120 photoresistant polymer Polymers 0.000 claims 2
- 238000000034 method Methods 0.000 abstract description 15
- 238000011109 contamination Methods 0.000 abstract description 4
- 239000007788 liquid Substances 0.000 abstract description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract description 3
- 230000001681 protective effect Effects 0.000 abstract description 3
- 239000002689 soil Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 230000007547 defect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、例えばアクティブマトリックス液晶表示装置
を駆動するトランジスタとして用いられる薄膜トランジ
スタに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor used as a transistor for driving, for example, an active matrix liquid crystal display device.
第７図は例えば特開昭６１−１３９０６９号公報に示さ
れた従来の薄膜トランジスタを示す断面図である。FIG. 7 is a sectional view showing a conventional thin film transistor disclosed in, for example, Japanese Patent Application Laid-open No. 139069/1983.
この図において、１はガラス基板、２はゲート電極、３
はゲート絶縁膜、４はアモルファス２９３７１層、５は
ｎ十層、６は上部絶縁膜、７はソース電極、８はドレイ
ン電極である。In this figure, 1 is a glass substrate, 2 is a gate electrode, and 3 is a glass substrate.
4 is a gate insulating film, 4 is an amorphous 29371 layer, 5 is an n10 layer, 6 is an upper insulating film, 7 is a source electrode, and 8 is a drain electrode.
次に製造方法について述べる。Next, the manufacturing method will be described.
まず、透光性のガラス基板１上にゲート金属を形成した
後、これをフォトリソエツチングによりバターニングし
、ゲート電極２を形成する。First, a gate metal is formed on a transparent glass substrate 1, and then patterned by photolithography to form a gate electrode 2.
次いで、ゲート絶縁膜３．アモルファスシリコンｉ層４
．上部絶縁膜を形成した後、第８図（ａ）に示すように
ポジレジスト９を塗布し、基板１側から露光し、ゲート
電極２による像をポジレジスト９上に結像せしめ、セル
フアラインメントによる上部絶縁膜パターン６を形成す
る。Next, gate insulating film 3. Amorphous silicon i-layer 4
．． After forming the upper insulating film, a positive resist 9 is applied as shown in FIG. An upper insulating film pattern 6 is formed.
次いで、第８図（ｂｌに示すようにｎ土層５および金属
膜を着膜し、ポジレジスト９の除去とともにリフトオフ
法により上部絶縁膜６上のｎ”Ｆｊ５と金属膜を除去し
、ソース電極７およびドレイン電極８を形成する。Next, as shown in FIG. 8 (bl), an n-soil layer 5 and a metal film are deposited, and the positive resist 9 is removed and the n''Fj 5 and metal film on the upper insulating film 6 are removed by a lift-off method to form the source electrode. 7 and a drain electrode 8 are formed.
従来の薄膜トランジスタは以上のように構成されている
ので、リフトオフ時にレジスト除去液等がｎ十層や金Ｂ
膜により汚染され、基板を汚すという欠点があり、また
、レジスト除去液等が劣化しやすい等という問題点があ
った。Conventional thin film transistors are constructed as described above, so that resist removal liquid, etc. may be used to remove layers such as gold and gold during lift-off.
There are disadvantages in that the film contaminates the substrate, and there are also problems in that the resist removal liquid and the like tend to deteriorate.
また、リフトオフプロセスの再現性が悪く、リフトオフ
がなされないパターン欠陥が残りやすいという問題点が
あった。Further, there was a problem in that the reproducibility of the lift-off process was poor and pattern defects that were not lifted-off tend to remain.
この発明は上記のような問題点を解消するためになされ
たもので、リフトオフ工程をなくすことができるととも
にソースおよびドレイン電極の内側の端縁とゲート電極
の端縁とが一致する薄膜ｌ・ランジスタを得ることを目
的とする。This invention was made to solve the above-mentioned problems, and it is possible to eliminate the lift-off process and to create a thin film transistor in which the inner edges of the source and drain electrodes coincide with the edges of the gate electrode. The purpose is to obtain.
本発明に係る薄膜トランジスタは、ソース、ドレイン電
極となるメタル膜をゲート電極と若干の隙間をもつよう
に形成した後、ｎ十層をゲート電極をマスクとしたセル
フアラインメントを用いた方法によってエツチングし、
ソース、ドレイン電極の一部となるｎ十層を形成するよ
うにしたものである。In the thin film transistor according to the present invention, a metal film serving as the source and drain electrodes is formed with a slight gap from the gate electrode, and then the n-th layer is etched by a method using self-alignment using the gate electrode as a mask.
In this embodiment, n10 layers are formed to form part of the source and drain electrodes.
本発明においては、ソース、ドレイン電極の一部として
用いられるｎ＋層が、ゲート電極をマスクとしたセルフ
アラインメントを用いた方法によ゛って形成されること
により、ゲート電極とほとんど重なりを持たないソース
、ドレイン電極がリフトオフ法を用いないで精度よく形
成され、レジスト除去液等の汚染、劣化等を低減でき、
又、レジスト除去の不完全性に伴うパターン欠陥を防止
できる。In the present invention, the n+ layer used as part of the source and drain electrodes is formed by a method using self-alignment using the gate electrode as a mask, so that it has almost no overlap with the gate electrode. The source and drain electrodes are formed with high precision without using the lift-off method, reducing contamination and deterioration of the resist removal solution, etc.
Furthermore, pattern defects due to incomplete resist removal can be prevented.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は本実施例による薄膜トランジスタの断面図であ
る。FIG. 1 is a cross-sectional view of a thin film transistor according to this embodiment.
この薄膜トランジスタは、ガラス基板ｌ上に形成された
ゲート電極２上にゲート絶縁膜３とアモルファス９９３
７１層４とｎ土層５とが積層されており、ｎ＋ｒａ５は
ゲート電極２の上の部分のみがエツチングされている。This thin film transistor consists of a gate insulating film 3 and an amorphous 993 film formed on a gate electrode 2 formed on a glass substrate l.
The 71 layer 4 and the n-soil layer 5 are stacked, and only the portion above the gate electrode 2 of the n+ra 5 is etched.
ソース、ドレイン電掘７．８は、ゲート電極２との重な
りはなく、ギャップを有するようにフォトリソエツチン
グによりパターニングされている。The source and drain trenches 7.8 are patterned by photolithography so that they do not overlap with the gate electrode 2 and have a gap.
次に、第２図を用いてこの薄膜トランジスタの製造方法
について説明する。Next, a method for manufacturing this thin film transistor will be explained using FIG.
ｎ土層５のバターニングは、（ａ）に示すようにポジレ
ジスト９を塗布後ゲート電極２をマスクとしてガラス基
ｉｆ側から露光し、イメージリバース法を用い山）に示
すようにレジスト９を形成した後、ｎ土層５をエッチオ
フして行う。その後、レジスト９を除去し、保護膜６を
形成して第１図のトランジスタを完成する。The patterning of the n-soil layer 5 is carried out by coating the positive resist 9 as shown in (a), exposing it to light from the glass substrate if side using the gate electrode 2 as a mask, and using the image reverse method to pattern the resist 9 as shown in the crest). After the formation, the n-soil layer 5 is etched off. Thereafter, the resist 9 is removed and a protective film 6 is formed to complete the transistor shown in FIG.
上記ｎ十層バターニング工程ではセルフアラインメント
方式を用いており、ｎ土層５はゲート電極２とほとんど
オーバーラツプしないので、寄生容量が少ない。また、
レジスト除去の際、リフトオフではないので、湿式除去
の場合にはレジスト除去液を汚染することが少なく、ま
た乾式除去の場合には全く問題がない。The self-alignment method is used in the above-mentioned n-ten layer patterning process, and since the n-soil layer 5 hardly overlaps with the gate electrode 2, the parasitic capacitance is small. Also,
Since there is no lift-off when removing the resist, there is little contamination of the resist removal solution in the case of wet removal, and there is no problem at all in the case of dry removal.
なお、第３図はこの発明の第２の実施例による薄膜トラ
ンジスタを示す断面図、第４図はその製造工程を示す図
である。これらの図に示すように、不要なｎ”ｒｉｉｉ
５およびアモルファス９９３７１層４をエツチングした
後、ソース、ドレイン電極７゜８を形成しく第４図（ａ
ｔ） 、ｎ土層５をセルフアラインメント方式によって
エッチオフしく第４図＜ｂ））、第３図に示す薄膜トラ
ンジスタを形成することも可能である。Note that FIG. 3 is a sectional view showing a thin film transistor according to a second embodiment of the present invention, and FIG. 4 is a diagram showing the manufacturing process thereof. As shown in these figures, the unnecessary n”riii
5 and amorphous 99371 layer 4, source and drain electrodes 7°8 are formed as shown in FIG.
It is also possible to form the thin film transistor shown in FIG. 3 by etching off the n-soil layer 5 using a self-alignment method (FIG. 4<b)).
また、第５図はこの発明の第３の実施例によるＳ膜トラ
ンジスタを示す断面図、第６図はその製造工程を示す図
である。これらの図に示すように、ゲート絶縁膜３およ
びｎ十層５およびソース、ドレイン電極材料７．８を連
続形成後、フォトリソエツチングでソース、ドレイン電
極７，８をパターニングし、ｎ”１ｉｉ５をセルフアラ
インメント方式でエッチオフしく第６図（ａ））、レジ
スト除去後、アモルファスシリコンｉＮ４および保護Ｉ
ｔ！１６を形成しく第６図（ｂ））、第５図に示す薄膜
トランジスタを形成することも可能である。Further, FIG. 5 is a sectional view showing an S film transistor according to a third embodiment of the present invention, and FIG. 6 is a diagram showing the manufacturing process thereof. As shown in these figures, after successively forming the gate insulating film 3, the n''1i layer 5, and the source and drain electrode materials 7 and 8, the source and drain electrodes 7 and 8 are patterned by photolithography, and the n''1ii5 is self-contained. After removing the resist, amorphous silicon iN4 and protective I
T! It is also possible to form the thin film transistor shown in FIG. 6(b) and FIG. 5 by forming the thin film transistor 16.
以上のように、この発明に係る薄膜トランジスタによれ
ば、ソース、ドレイン電極となるメタル膜をその間隔が
ゲート電極幅より広くなるよう形成し、ソース、ドレイ
ン電極の一部となるｎ土層をセルフアラインメントによ
って形成するようにしたので、ゲート電極とソース、ド
レイン電極とのオーバーランプによる寄生容量がほとん
ど皆無である動作特性の良好な薄膜トランジスタをリフ
トオフ工程を用いずに得ることが可能となり、また、こ
れによりレジスト除去液の汚染、劣化による加工不良、
またパターン欠陥を少なくすることができる効果がある
。As described above, according to the thin film transistor of the present invention, the metal films that become the source and drain electrodes are formed so that the distance between them is wider than the width of the gate electrode, and the n-soil layer that becomes part of the source and drain electrodes is self-contained. Since it is formed by alignment, it is possible to obtain a thin film transistor with good operating characteristics, with almost no parasitic capacitance due to overlamp between the gate electrode and the source and drain electrodes, without using a lift-off process. This may cause contamination of the resist removal solution and processing defects due to deterioration.
It also has the effect of reducing pattern defects.
第１図は本発明の第１の実施例による薄膜トランジスタ
を示す断面図、第２図はその製造工程図、第３図は本発
明の第２の実施例による薄膜トランジスタを示す断面図
、第４図はその製造工程図、第５図は本発明の第３の実
施例による薄膜トランジスタを示す断面図、第６図はそ
の製造工程図、第７図は従来の薄膜トランジスタを示す
断面図、第８図はその製造工程図である。
１はガラス基板、２はゲート電極、３はゲート絶縁膜、
４はアモルファスシリコ７１層、５はｎ土層、６は上部
絶縁膜、７はソース電極、８はドレイン電極、９はポジ
レジスト。
なお、図中同一符号は、同−又は相当部分を示す。FIG. 1 is a sectional view showing a thin film transistor according to a first embodiment of the present invention, FIG. 2 is a manufacturing process diagram thereof, FIG. 3 is a sectional view showing a thin film transistor according to a second embodiment of the present invention, and FIG. 5 is a sectional view showing a thin film transistor according to a third embodiment of the present invention, FIG. 6 is a sectional view showing a manufacturing process thereof, FIG. 7 is a sectional view showing a conventional thin film transistor, and FIG. 8 is a sectional view showing a conventional thin film transistor. It is a manufacturing process diagram. 1 is a glass substrate, 2 is a gate electrode, 3 is a gate insulating film,
4 is an amorphous silicon 71 layer, 5 is an n-soil layer, 6 is an upper insulating film, 7 is a source electrode, 8 is a drain electrode, and 9 is a positive resist. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (3)
にゲート絶縁膜、半導体薄膜、ｎ＾＋半導体層とメタル
膜とからなるソース及びドレイン電極を形成してなる薄
膜トランジスタにおいて、上記ソース及びドレイン電極
はｎ＾＋半導体層上にメタル膜を形成した後、該メタル
膜をソース、ドレインとなる部分の間隔が上記ゲート電
極幅より広くなるようにパターン形成した後、フォトレ
ジストを塗布し、セルフアラインメント処理により上記
ゲート電極上の該フォトレジストを除去した後、上記ゲ
ート電極の直上の上記ｎ＾＋半導体層をエッチングによ
り除去して形成されたものであることを特徴とする薄膜
トランジスタ。(1) A thin film transistor in which a gate electrode is formed on a substrate such as glass, and source and drain electrodes made of a gate insulating film, a semiconductor thin film, an n^+ semiconductor layer, and a metal film are formed thereon. For the and drain electrodes, a metal film is formed on the n^+ semiconductor layer, the metal film is patterned so that the distance between the parts that will become the source and the drain is wider than the width of the gate electrode, and then a photoresist is applied. . A thin film transistor formed by removing the photoresist on the gate electrode by self-alignment treatment, and then removing the n^+ semiconductor layer directly above the gate electrode by etching.
らなるものであることを特徴とする特許請求の範囲第１
項記載の薄膜トランジスタ。(2) Claim 1, wherein the semiconductor thin film is made of hydrogenated amorphous silicon.
The thin film transistor described in Section 1.
るものであることを特徴とする特許請求の範囲第１項ま
たは第２項記載の薄膜トランジスタ。(3) The thin film transistor according to claim 1 or 2, which is used in an active matrix liquid crystal display device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5705187A JPS63224258A (en) | 1987-03-12 | 1987-03-12 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5705187A JPS63224258A (en) | 1987-03-12 | 1987-03-12 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63224258A true JPS63224258A (en) | 1988-09-19 |
Family
ID=13044647
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5705187A Pending JPS63224258A (en) | 1987-03-12 | 1987-03-12 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63224258A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004193248A (en) * | 2002-12-10 | 2004-07-08 | Hitachi Ltd | Image display device and its manufacturing method |
| JP2010141308A (en) * | 2008-11-13 | 2010-06-24 | Semiconductor Energy Lab Co Ltd | Semiconductor device and method for manufacturing the same |
-
1987
- 1987-03-12 JP JP5705187A patent/JPS63224258A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004193248A (en) * | 2002-12-10 | 2004-07-08 | Hitachi Ltd | Image display device and its manufacturing method |
| JP2010141308A (en) * | 2008-11-13 | 2010-06-24 | Semiconductor Energy Lab Co Ltd | Semiconductor device and method for manufacturing the same |
| US9054203B2 (en) | 2008-11-13 | 2015-06-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
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