JPS63222442A - High frequency integrated circuit - Google Patents
High frequency integrated circuitInfo
- Publication number
- JPS63222442A JPS63222442A JP5625887A JP5625887A JPS63222442A JP S63222442 A JPS63222442 A JP S63222442A JP 5625887 A JP5625887 A JP 5625887A JP 5625887 A JP5625887 A JP 5625887A JP S63222442 A JPS63222442 A JP S63222442A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- dielectric
- semiconductor substrate
- transmission line
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims abstract description 54
- 229910052751 metal Inorganic materials 0.000 claims abstract description 54
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 230000005540 biological transmission Effects 0.000 claims abstract description 25
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 150000002739 metals Chemical class 0.000 abstract 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 10
- 239000003989 dielectric material Substances 0.000 description 9
- 239000010931 gold Substances 0.000 description 9
- 229910052737 gold Inorganic materials 0.000 description 9
- 230000000694 effects Effects 0.000 description 6
- 238000004904 shortening Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 102200142793 rs35418374 Human genes 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、高周波集積回路に関し、さらに詳しくは、集
積回路内の伝送線路幅を細（出来ると共に伝送線路にお
ける波長短縮効果を抑制することが出来る高周波集積回
路に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to high frequency integrated circuits, and more specifically, to a high frequency integrated circuit that can reduce the width of a transmission line in an integrated circuit (as well as suppress the wavelength shortening effect in the transmission line). Concerning integrated circuits.
従来技術 従来の高周波集積回路として、例えばＧ、Ａ。Conventional technology Examples of conventional high frequency integrated circuits include G and A.
等の半導体を用いた高周波モノリシック築積回路が知ら
れている。High-frequency monolithic integrated circuits using semiconductors such as the following are known.
このような高周波モノリンク集積回路における伝送線路
は、半導体基板上に直接金属を層着することにより形成
されている。The transmission line in such a high frequency monolink integrated circuit is formed by directly depositing a metal layer on a semiconductor substrate.
例えば、特性インピーダンス５０Ωの伝送線路は、１０
０μｍ厚のＧ、Ａ、半導体基板上に約８０μｍ幅で金を
蒸着して形成されている。For example, a transmission line with a characteristic impedance of 50Ω is
It is formed by depositing gold to a width of about 80 μm on a G, A, and semiconductor substrate with a thickness of 0 μm.
第４図はその構造例を示すもので、１はＧ、Ａ。FIG. 4 shows an example of its structure, where 1 is G and A.
半導体基板、２はＭＢＳＦＥＴのソースのｎ＋層、３は
ドレインのｎ十層、４はチャネルの１層、５はソース電
極金属、１６はゲート電極配線金属、１７はドレイン電
極配線金属、１８は接地電極金属である。Semiconductor substrate, 2 is n+ layer of source of MBSFET, 3 is n10 layer of drain, 4 is 1 layer of channel, 5 is source electrode metal, 16 is gate electrode wiring metal, 17 is drain electrode wiring metal, 18 is ground It is an electrode metal.
伝送線路は、ゲート電極配線金属１６及びドレイン電極
配線金属１７によって形成されており、Ｇ、Ａ、半導体
基板１を挟んで接地電極金属１８と対向し、ストリップ
線路１５を形成している。The transmission line is formed by a gate electrode wiring metal 16 and a drain electrode wiring metal 17, and faces a ground electrode metal 18 with G, A, and semiconductor substrate 1 in between, forming a strip line 15.
従来技術の問題点
ところが、高周波モノリシック集積回路の動作周波数が
高くなるにつれて、高誘電率の半導体基板を使用する場
合、回路設計上次のような問題点が生じる。半導体とし
てＧ、Ａ、を例にとると、その比誘電率は約１３と比較
的大きいため、動作周波数が高くなるにつれて、誘電体
としてのＧ。Problems with the Prior Art However, as the operating frequency of high-frequency monolithic integrated circuits increases, the following problems arise in circuit design when using a semiconductor substrate with a high dielectric constant. Taking G and A as semiconductors as an example, their dielectric constant is relatively large at about 13, so as the operating frequency increases, the dielectric constant of G increases.
Ａ、による波長の短縮が著しくなり、例えば１００μｍ
厚の半絶縁性Ｇ、Ａ、基板上に形成した特性インピーダ
ンス５０Ωの伝送線路の線路幅は約８０μｍであり、そ
のときの実効比誘電率は約８である。従って、例えば２
０ＧＨｚの高周波信号（波長１５ｍ）が、前記伝送線路
を伝搬するときの波長は１ ／ ８ ′／２に短縮され
て約５．３ｆｉとなる。A, the wavelength is significantly shortened, for example by 100 μm.
The line width of the transmission line with a characteristic impedance of 50 Ω formed on thick semi-insulating G and A substrates is about 80 μm, and the effective dielectric constant at that time is about 8. Therefore, for example 2
When a 0 GHz high frequency signal (wavelength 15 m) propagates through the transmission line, the wavelength is shortened to 1/8'/2, which is approximately 5.3 fi.
そうすると、例えば第５図のような約８０μｍ幅の伝送
線路のＴ字型分岐点を考えると、Ａ点とＢ点間で約０．
０１５波長（−８０μｍ１５．３ｍ）の電気長となって
しまうが、この電気長はスミスチャート上で約１０“の
回転を与えるもので、回路設計上無視できなくなる。For example, if we consider a T-shaped branch point of a transmission line with a width of about 80 μm as shown in FIG. 5, the distance between points A and B is about 0.
This results in an electrical length of 0.015 wavelength (-80 μm 15.3 m), which gives a rotation of about 10" on the Smith chart and cannot be ignored in terms of circuit design.
このため、回路設計上、分岐点をＡ点からＢ点までの間
のどこに設定するかを厳しく判断しなければならないが
、この判断は困難で、多くの場合は実験的に求めざるを
得ないという問題点があっ発明の目的
本発明の目的とするところは、伝送線路の幅を細く出来
ると共に、波長短縮効果を小さく抑え、回路設計上の困
難性を軽減することが出来る高周波集積回路を提供する
ことにある。Therefore, in circuit design, it is necessary to make a strict judgment as to where to set the branch point between point A and point B, but this judgment is difficult and must be determined experimentally in many cases. SUMMARY OF THE INVENTION An object of the present invention is to provide a high-frequency integrated circuit that can reduce the width of a transmission line, suppress the wavelength shortening effect, and reduce difficulties in circuit design. It's about doing.
発明の構成
本発明の高周波集積回路は、半導体基板上に低抵抗率金
属により形成した接地電極と、前記接地電極上に形成し
た前記半導体基板より低誘電率の誘電体と、前記誘電体
上に形成した低抵抗率金属による伝送線路とにより形成
したストリップ線路を具備してなることを構成上の特徴
とするものである。Structure of the Invention The high frequency integrated circuit of the present invention includes: a ground electrode formed of a low resistivity metal on a semiconductor substrate; a dielectric having a dielectric constant lower than that of the semiconductor substrate formed on the ground electrode; The structure is characterized by comprising a transmission line formed of a low resistivity metal and a strip line formed of a low resistivity metal.
作用
本発明の高周波集積回路では、伝送線路を半導体基板上
に直接形成するのではなく、半導体基板上に形成した誘
電体上に形成する。そして、その誘電体をストリップ線
路の誘電体とする。Function: In the high frequency integrated circuit of the present invention, the transmission line is not formed directly on the semiconductor substrate, but on a dielectric material formed on the semiconductor substrate. Then, this dielectric material is used as a dielectric material of a strip line.
この誘電体厚は半導体基板厚よりも薄くできるので、同
じ特性インピーダンスをもたせるのに従来よりも線路幅
を細くすることができる。Since this dielectric thickness can be made thinner than the semiconductor substrate thickness, the line width can be made narrower than in the past to provide the same characteristic impedance.
また、この誘電体は半導体基板より低誘電率なので、波
長短縮効果を低減でき、分岐点の設定等の回路設計上の
困難性が解消される。Furthermore, since this dielectric material has a lower dielectric constant than the semiconductor substrate, the wavelength shortening effect can be reduced, and difficulties in circuit design such as setting branch points can be solved.
実施例
以下、図に示す実施例に基づいて、本発明を更に詳しく
説明する。ここに、第１図は本発明の一実施例の高周波
集積回路の要部断面図、第２ＴｙＪは本発明の一実施例
におけるＴ字型分岐点の平面図、第３図ｆａ） （ｂ）
（ｃｌ （ｄｌ ｆａｔは第１１！Ｉに示す高周波集
積回路の製造過程を示す要部断面図である。EXAMPLES Hereinafter, the present invention will be explained in more detail based on examples shown in the drawings. Here, FIG. 1 is a sectional view of a main part of a high-frequency integrated circuit according to an embodiment of the present invention, 2nd TyJ is a plan view of a T-shaped branch point according to an embodiment of the present invention, and FIG. 3 fa) (b)
(cl (dl fat) is a sectional view of a main part showing the manufacturing process of the high frequency integrated circuit shown in No. 11!I.
第１図に示す高周波集積回路５０において、Ｇ。In the high frequency integrated circuit 50 shown in FIG.
Ａ、半導体基板１に、ＭＥＳＦＥＴのソースのｎ″Ｉｗ
２と、ドレインのｎ今層３と、チャネルのｎ屓４とが形
成されている。A, MESFET source n″Iw on semiconductor substrate 1
2, a drain n-layer 3, and a channel n-layer 4 are formed.
ソースのｎ”Ｆｉ２上にはソース電極金属５、ドレイン
のｎ十層３上にはドレイン電極金［７、チャネルの０層
４上にはゲート電極金属６が形成されている。A source electrode metal 5 is formed on the source n'' Fi2, a drain electrode gold [7] is formed on the drain n'' layer 3, and a gate electrode metal 6 is formed on the channel 0 layer 4.
Ｇ、Ａ、半導体基板ｌ上には接地電極金属８が形成され
、その接地電極金１７１８はバイアホール等により形成
した接地金属９と接続されている。G, A, a ground electrode metal 8 is formed on the semiconductor substrate l, and the ground electrode metal 1718 is connected to the ground metal 9 formed by a via hole or the like.
接地電極金属８上には非晶質のシリコン酸化膜を誘電体
１０として形成している。An amorphous silicon oxide film is formed as a dielectric 10 on the ground electrode metal 8 .
誘電体１０上には、ゲート配線金属１１とドレ −イ
ン配線金属１４とが形成され、これらは各々ゲート電極
金属６．ドレイン電極金Ｉ７！７と接続されている。A gate wiring metal 11 and a drain wiring metal 14 are formed on the dielectric 10, each of which is connected to the gate electrode metal 6. It is connected to the drain electrode gold I7!7.
ゲート配線金属１１．ドレイン配線金属１４が伝送線路
であり、これらは誘電体１０を介して接地電極金属８と
対向し、ストリップ線路１５を形成している。Gate wiring metal 11. The drain wiring metal 14 is a transmission line, which faces the ground electrode metal 8 via the dielectric 10 to form a strip line 15.
さて、非晶質のシリコン酸化膜の誘電体１０は、例えば
３μｍ厚程度に薄く形成できる。そうすると、特性イン
ピーダンス５０Ωを得るための伝送線路幅は約６．５μ
ｍとなり、従来のＧ１１Ａ、半導体基板上の伝送線路幅
約８０μｍの約１／１２となる。Now, the dielectric 10 made of an amorphous silicon oxide film can be formed as thin as, for example, about 3 μm. Then, the transmission line width to obtain a characteristic impedance of 50Ω is approximately 6.5μ.
m, which is approximately 1/12 of the transmission line width on the semiconductor substrate of the conventional G11A, which is approximately 80 μm.
また、伝送線路における実効比誘電率は約２．５であり
、２０ＧＨｚ高周波信号（波長１５ｍｍ）が伝搬すると
きの波長は１／２．５′／２に短縮されて約９゜５１と
なる。これは従来のＧ ｔ Ａ−半導体基板上の伝送線
路における波長約５．３ ｍｍより波長短縮効果が小さ
くなっている。Further, the effective dielectric constant of the transmission line is approximately 2.5, and the wavelength when a 20 GHz high frequency signal (wavelength 15 mm) propagates is shortened to 1/2.5'/2, which is approximately 9°51. This has a smaller wavelength shortening effect than the wavelength of about 5.3 mm in a conventional transmission line on a G t A-semiconductor substrate.
そこで、第２図に示す約６．５μｍ幅の伝送線路のＴ字
型分岐点を考えると、Ａ点とＢ点間で約０゜０００７波
長（＝６．５ μｍ／９．５Ｗｍ）の電気長となり、ス
ミスチャート上の回転は約０．５°である。Therefore, considering the T-shaped branch point of a transmission line with a width of approximately 6.5 μm shown in Fig. 2, an electric current of approximately 0°0007 wavelength (=6.5 μm/9.5 Wm) is generated between points A and B. The rotation on the Smith chart is about 0.5°.
従って、第２図のような分岐点での電気長は無視でき、
回路設計上の問題点を大幅に低減できる。Therefore, the electrical length at the branch point as shown in Figure 2 can be ignored,
Problems in circuit design can be significantly reduced.
次に、高周波集積回路５０の製造プロセス例を第３図［
ａ）〜（ａｌを参照して説明する。但し、ＭＥＳＦＥＴ
の形成までのプロセスは従来と同様なので説明を省略し
、その後のプロセスについて以下に述べる。Next, an example of the manufacturing process of the high frequency integrated circuit 50 is shown in FIG.
a) ~ (Explained with reference to al. However, MESFET
The process up to the formation of is the same as the conventional one, so the explanation will be omitted, and the subsequent process will be described below.
ｆａｌＧ、Ａ、半導体基板１上に接地電極金属８を形成
し、その接地電極金属８上に非晶質のシリコン酸化膜を
誘電体１０として形成する。falG, A. A ground electrode metal 8 is formed on a semiconductor substrate 1, and an amorphous silicon oxide film is formed as a dielectric 10 on the ground electrode metal 8.
（ｂｌ レジスト１２等を用いた光露光等によ性、誘
電体１０にゲート電極金Ｉ７！６へ貫通する孔１９およ
びドレイン電極金Ｈ７へ貫通する孔２０をあける。(bl) A hole 19 penetrating to the gate electrode gold I7!6 and a hole 20 penetrating to the drain electrode gold H7 are made in the dielectric 10 by photo-exposure using a resist 12 or the like.
ＦＣ＋ ゲート電極金属６へ配線を行うための接続金
属１３およびドレイン電極金Ｍ７へ配線を行うための接
続金属１６ （例えば金等）をリフトオフ法等により形
成する。A connection metal 13 for wiring to the FC+ gate electrode metal 6 and a connection metal 16 (for example, gold) for wiring to the drain electrode gold M7 are formed by a lift-off method or the like.
（ｄ） レジスト等によりパターニングし、金等の低
抵抗率の金属をリフトオフ法等により形成し、誘電体１
０上にゲート配線金属１１およびドレイン配線金属１４
を形成する。(d) Patterning with resist etc. and forming a low resistivity metal such as gold by lift-off method etc. to form dielectric 1
Gate wiring metal 11 and drain wiring metal 14 on
form.
（ａｌ 接地電極金属８に、バイアホール等を用いて
接地金ｒｊＸ９より接地電位を与える。(Al Apply a ground potential to the ground electrode metal 8 from the ground metal rjX9 using a via hole or the like.
以上、高周波集積回路５０を例にとって本発明の詳細な
説明したが、本発明はこれによって限定されるわけでは
なく、半導体基板としては、例えばＳλや、ＩｎＰその
他の化合物半導体等が使用可能であり、ストリップ線路
の誘電体としては、非晶質のシリコン窒化膜等も使用可
能である。The present invention has been described above in detail by taking the high frequency integrated circuit 50 as an example, but the present invention is not limited thereto.For example, Sλ, InP, and other compound semiconductors can be used as the semiconductor substrate. As the dielectric material of the strip line, an amorphous silicon nitride film or the like can also be used.
発明の効果
本発明によれば、半導体基板上に低抵抗率金属により形
成した接地電極と、前記接地電極上に形成した前記半導
体基板より低誘電率の誘電体と、前記誘電体上に形成し
た低抵抗率金属による伝送線路とにより形成したストリ
ップ線路を具備してなることを特徴とする高周波集積回
路が提供され、これによりストリップ線路の誘電体の厚
さを薄くできるため伝送線路幅を細くできる。同時に、
この誘電体は半導体基板より低誘電率であるから、伝送
線路上を伝搬する高周波信号の波長短縮効果を低減でき
、これにより回路設計上の問題点が軽減される。Effects of the Invention According to the present invention, a ground electrode formed of a low resistivity metal on a semiconductor substrate, a dielectric material having a lower dielectric constant than the semiconductor substrate formed on the ground electrode, and a dielectric material formed on the dielectric material. Provided is a high-frequency integrated circuit characterized by comprising a strip line formed by a transmission line made of a low-resistivity metal, whereby the thickness of the dielectric of the strip line can be made thinner, so that the width of the transmission line can be made narrower. . at the same time,
Since this dielectric material has a lower dielectric constant than the semiconductor substrate, it is possible to reduce the wavelength shortening effect of high frequency signals propagating on the transmission line, thereby reducing problems in circuit design.
第１図は本発明の一実施例の高周波集積回路の要部断面
図、第２図は本発明の一実施例におけるＴ字型分岐点の
平面図、第３図（ａｌ （ｂｌ （Ｃ） Ｆｄ） （８
１は第１図に示す高周波集積回路の製造過程を示す要部
断面図、第４図は従来の高周波集積回路の一例の要部断
面図、第５図は従来のＴ字型分岐点の平面図である。
（符号の説明）
１・・・Ｇ、Ａ、半導体基板
８・・・接地電極金ｆｆｌ １０・・・誘電体
１１・・・ゲート配線金属
１４・・・ドレイン配線金属
１５・・・ストリップ線路。FIG. 1 is a sectional view of a main part of a high-frequency integrated circuit according to an embodiment of the present invention, FIG. 2 is a plan view of a T-shaped branch point according to an embodiment of the present invention, and FIG. Fd) (8
1 is a cross-sectional view of a main part showing the manufacturing process of the high-frequency integrated circuit shown in FIG. 1, FIG. 4 is a cross-sectional view of a main part of an example of a conventional high-frequency integrated circuit, and FIG. 5 is a plan view of a conventional T-shaped branch point. It is a diagram. (Explanation of symbols) 1...G, A, semiconductor substrate 8...ground electrode gold ffl 10...dielectric 11...gate wiring metal 14...drain wiring metal 15...strip line.
Claims (1)
極と、前記接地電極上に形成した前記半導体基板より低
誘電率の誘電体と、前記誘電体上に形成した低抵抗率金
属による伝送線路とにより形成したストリップ線路を具
備してなることを特徴とする高周波集積回路。1. A ground electrode formed of a low resistivity metal on a semiconductor substrate, a dielectric having a lower dielectric constant than the semiconductor substrate formed on the ground electrode, and a transmission line made of a low resistivity metal formed on the dielectric. A high frequency integrated circuit comprising a strip line formed by.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5625887A JPS63222442A (en) | 1987-03-11 | 1987-03-11 | High frequency integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5625887A JPS63222442A (en) | 1987-03-11 | 1987-03-11 | High frequency integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63222442A true JPS63222442A (en) | 1988-09-16 |
Family
ID=13022056
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5625887A Pending JPS63222442A (en) | 1987-03-11 | 1987-03-11 | High frequency integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63222442A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6433408B1 (en) | 1999-01-08 | 2002-08-13 | Nec Corporation | Highly integrated circuit including transmission lines which have excellent characteristics |
| JP2009246157A (en) * | 2008-03-31 | 2009-10-22 | Toshiba Corp | High frequency band semiconductor device |
-
1987
- 1987-03-11 JP JP5625887A patent/JPS63222442A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6433408B1 (en) | 1999-01-08 | 2002-08-13 | Nec Corporation | Highly integrated circuit including transmission lines which have excellent characteristics |
| JP2009246157A (en) * | 2008-03-31 | 2009-10-22 | Toshiba Corp | High frequency band semiconductor device |
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