JPS63222435A - Semiconductor substrate having polycrystalline layer - Google Patents
Semiconductor substrate having polycrystalline layerInfo
- Publication number
- JPS63222435A JPS63222435A JP5616087A JP5616087A JPS63222435A JP S63222435 A JPS63222435 A JP S63222435A JP 5616087 A JP5616087 A JP 5616087A JP 5616087 A JP5616087 A JP 5616087A JP S63222435 A JPS63222435 A JP S63222435A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- polycrystalline layer
- polycrystalline
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 239000000758 substrate Substances 0.000 title claims description 34
- 239000013078 crystal Substances 0.000 claims abstract description 55
- 239000000463 material Substances 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 12
- 238000005247 gettering Methods 0.000 abstract description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 5
- 239000001301 oxygen Substances 0.000 abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 abstract description 5
- 235000012431 wafers Nutrition 0.000 description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000006378 damage Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 101100389815 Caenorhabditis elegans eva-1 gene Proteins 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000003575 carbonaceous material Substances 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000000415 inactivating effect Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Landscapes
- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は多結晶層を有する半導体基板に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a semiconductor substrate having a polycrystalline layer.
（従来の技術）
従来の半導体基板は、■純粋なシリコン単結晶■ゲルマ
ニウム単結晶、■ｍｖｍ金属単結晶によるＮ型単結晶、
■Ｐ型の不純物を含むＮｌｌ単結晶、■Ｐ型型詰結晶■
いわゆる純絶縁型・Ｉ型車結晶、などによるウェハから
切り出されたチップにより構成され、その上に又はその
内部にエピタキシャル層や拡散層が形成され、この中に
能動。(Conventional technology) Conventional semiconductor substrates include: ■ Pure silicon single crystal ■ Germanium single crystal ■ N-type single crystal made of mvm metal single crystal,
■Nll single crystal containing P-type impurities, ■P-type packed crystal■
It consists of a chip cut out from a wafer made of a so-called pure insulating type I-type wheel crystal, etc., and an epitaxial layer or a diffusion layer is formed on or inside the chip, and an active layer is formed inside the chip.
受動回路素子が組込まれて半導体回路が形成されるのが
一般である。この場合ウェハチップ内の結晶配列に乱れ
が生じ、為に結晶内でスリップ現象が起ったり、結晶の
一部に亀裂や不連続点が発生したりする結晶特性の不揃
を抑え、且つ均一で高品質のウェハを形成させるために
は、その半導体基板内に封じ込まれている余分な酸素や
不純物元素、物質を除去しなければならない、その手段
として、ウェハの裏面を鏡面にしたり１反対にわざわざ
切欠きを作り酸素を追い出してみたり、不純物元素を不
活性化させたりするための物質をドープしたり、拡散し
たりすることが行われている。Generally, passive circuit elements are incorporated to form a semiconductor circuit. In this case, the crystal alignment within the wafer chip is disturbed, which causes a slip phenomenon within the crystal, and cracks or discontinuities occur in some parts of the crystal. In order to form high-quality wafers in semiconductor substrates, it is necessary to remove excess oxygen, impurity elements, and substances trapped within the semiconductor substrate. Efforts have been made to intentionally create notches to drive out oxygen, or to dope or diffuse substances to inactivate impurity elements.
最近では多結晶層をＣＶＤ法に依り生成させ、これに上
記不活性化物質をドープせしめたりする手法も一部で構
ぜられている。Recently, some techniques have been developed in which a polycrystalline layer is formed by CVD and doped with the above-mentioned inactivating substance.
（発明が解決しようとする問題点）
しかしこのような手段を採る場合は、製品歩留りの向上
には寄与するが、製造コストが極めて高くなり、結局高
性能、高品質、低コストの半導体を得ることが出来ない
、更にＣＶＤ法による多結晶層を単結晶層上に接着する
場合にはせいぜい０．０５ミクロン内外から２ミクロン
内外までしか厚みが得られず、しかも製造コストが甚だ
高くなり側底半導体基板を構成するに充分な厚みの多結
晶層は得られない。(Problem to be solved by the invention) However, if such a method is adopted, although it contributes to improving the product yield, the manufacturing cost becomes extremely high, and in the end, it is difficult to obtain semiconductors with high performance, high quality, and low cost. Furthermore, when bonding a polycrystalline layer onto a single crystal layer using the CVD method, the thickness can only be obtained from 0.05 microns to 2 microns at most, and the manufacturing cost is extremely high. A polycrystalline layer of sufficient thickness to constitute a semiconductor substrate cannot be obtained.
本発明はかかる要求をすべて満足し、低電圧から高電圧
化の広い電圧、電流レンジで実施可能な低コスト、高品
質の半導体基板を提供するにある。The present invention satisfies all of these requirements and provides a low-cost, high-quality semiconductor substrate that can be used in a wide voltage and current range from low voltages to high voltages.
（間７題点な解決するための手段）
上記目的を達成するために本発明は、以下の技術手段を
採用する。(Means for solving seven problems) In order to achieve the above object, the present invention employs the following technical means.
すなわち本発明は、
Ｐ型・Ｎ型或は■型の半導体単結晶層と該単結晶層の一
面に半導体多結晶層とを設け、該多結晶層の厚さをｌＯ
ミクロン以上としてなる多結晶層を有する半導体基板を
第１の発明とし、Ｐ型・Ｎ型或は■型の半導体単結晶層
と該単結晶層の一面に半導体多結晶層とを設け、該多結
晶層の厚さをｌθミクロン以上としてなる半導体基板で
あって、多結晶層は回転板上に設置された単結晶層上に
滴下されることにより構成されてなる多結晶層を有する
半導体基板を第２の発明、
Ｐ型・Ｎ型或は■型の半導体単結晶層と該単結晶層の一
面に半導体多結晶層とを設け、該多結晶層の厚さを１０
ミクロン以上としてなる半導体基板であって、多結晶層
にはイントリンシックゲッタ或はエクストリンシックゲ
ッタ材をドープしてなる多結晶層を有する半導体基板を
第３の発明
Ｐ型・Ｎ型或は■型の半導体単結晶層と該単結晶層の一
面に半導体多結晶層とを設け、該多結晶層の厚さをｌＯ
ミクロン以上としてなる半導体基板であって、多結晶層
２の単結晶層との接合面と反対の面に電極を取付けてな
る多結晶層を有する半導体基板を第４の発明、
Ｐ型・Ｎ型或は■型の半導体単結晶層と該単結晶層の一
面に半導体多結晶層とを設け、該多結晶層の厚さを１０
ミクロン以上としてなる半導体基板であって、単結晶層
にのみ能動素子を設けてなる多結晶層を有する半導体基
板を第５の発明としている。That is, in the present invention, a P-type, N-type, or ■-type semiconductor single crystal layer and a semiconductor polycrystalline layer are provided on one surface of the single crystal layer, and the thickness of the polycrystalline layer is set to lO.
A first invention provides a semiconductor substrate having a polycrystalline layer having a diameter of microns or more, which includes a P-type, N-type, or ■-type semiconductor single-crystal layer and a semiconductor polycrystalline layer on one surface of the single-crystal layer, A semiconductor substrate having a crystal layer having a thickness of lθ microns or more, wherein the polycrystalline layer is formed by being dropped on a single crystal layer placed on a rotating plate. A second invention, a P-type, N-type or ■-type semiconductor single crystal layer and a semiconductor polycrystalline layer are provided on one surface of the single crystal layer, and the thickness of the polycrystalline layer is set to 10
A semiconductor substrate having a polycrystalline layer having a diameter of microns or more, the polycrystalline layer of which is doped with an intrinsic getter or an extrinsic getter material, is a semiconductor substrate having a polycrystalline layer having a polycrystalline layer doped with an intrinsic getter material or an extrinsic getter material. A semiconductor single crystal layer and a semiconductor polycrystalline layer are provided on one surface of the single crystal layer, and the thickness of the polycrystalline layer is set to lO
A fourth invention provides a semiconductor substrate having a polycrystalline layer having a diameter of microns or more, the polycrystalline layer having an electrode attached to a surface opposite to the bonding surface with the single crystal layer of the polycrystalline layer 2, P type/N type. Alternatively, a ■-type semiconductor single-crystal layer and a semiconductor polycrystalline layer are provided on one surface of the single-crystalline layer, and the thickness of the polycrystalline layer is set to 10
A fifth aspect of the present invention is a semiconductor substrate having a diameter of microns or more and having a polycrystalline layer in which active elements are provided only in a single crystal layer.
（実施例） 以下図面に依りその製法並びに構成について説明する。(Example) The manufacturing method and structure thereof will be explained below with reference to the drawings.
第１図は本発明の概要を示す構成図、第２図はこれによ
、り出来上った半導体基板の概略側断面図である。FIG. 1 is a configuration diagram showing an outline of the present invention, and FIG. 2 is a schematic side sectional view of a semiconductor substrate produced thereby.
第１図に於て、ｌは単結晶ウェハで出来るだけ薄く切り
出されていることが望ましく、約１５０ミクロンから３
００ミクロンが適当である。この場合ウェハｌはあまり
薄いと切り出しにくくなり、基板にソリが出たり切り欠
きを生じたりするので、例えばワイヤーソーの如き並列
にウェハ切り出し得る手段を用い、ウニ八両面に均等な
圧力を与えることにより切り出す。いずれにしろ単結晶
形状や特性が充分保たれる厚さでなければならない。In Figure 1, l is preferably a single crystal wafer cut out as thinly as possible, from about 150 microns to 3.
00 microns is suitable. In this case, if the wafer l is too thin, it will be difficult to cut out, and warpage or notches may occur on the substrate. Therefore, use a means that can cut the wafer in parallel, such as a wire saw, and apply equal pressure to both sides of the wafer. Cut out by. In any case, the thickness must be such that the single crystal shape and properties are sufficiently maintained.
なお、この意味でウェハの厚さが５００ミクロン程度或
はそれ以上であってもよい。In this sense, the thickness of the wafer may be about 500 microns or more.
次にこのウェハ１は、石英や炭素材の支持具２上に置か
れる。この支持具２は、実施例の場合、回転軸３により
約８００°Ｃ或はそれ以上の炉内に於て回転される。そ
の時の回転速度は任意にコントロールされる。また必要
によりウェハｌと支持具２との間には、両者の密着をさ
けるための炭素粉を散布し、或はウェハｌ中に混入した
り拡散したりしないような密着阻止物質４を置くとよい
。なお、５は加熱炉辺である。Next, this wafer 1 is placed on a support 2 made of quartz or carbon material. In the case of the embodiment, this support 2 is rotated by a rotating shaft 3 in a furnace at about 800° C. or more. The rotation speed at that time can be controlled arbitrarily. If necessary, carbon powder may be sprinkled between the wafer 1 and the support 2 to prevent them from coming into close contact with each other, or an adhesion preventing substance 4 may be placed to prevent the wafer 1 from being mixed or diffused into the wafer 1. good. In addition, 5 is a heating furnace side.
一方つエバｌと同属、同質の物質、例えば多結晶シリコ
ン６かこれを保持する溶解炉７内に収納され、加熱体８
により約１４００℃内外の温度にて溶状に保たれている
。溶融された多結晶シリコン６はバイブ９を介して適当
にコントロールされた滴状体ｌＯにされ、回転している
又は回転しようとしている単結晶シリコンウェハ１上に
流入される。単結晶シリコンウェハｊ］−に流入された
多結晶シリコン溶融体は、支持具２の回転遠心力に依っ
て必要な厚さで且つ単結晶ウェハ１と同径に広がり、第
２図に示す如き単結晶層１１と多結晶層１２との一体構
成体が形成される。この場合、多結晶層の厚みは滴下量
により０．５ミクロンから３００ミクロン或はそれ以下
、以上にコントロールすることが出来る。発明者の実験
によると、本発明方法を用いて、多結晶層１２の厚みが
３０ｃｍ程度の半導体基板を短時間（数１０秒）のうち
に形成出来ることが確認されている。On the other hand, a heating element 8 is housed in a melting furnace 7 that holds a material of the same genus and quality as Eva 1, such as polycrystalline silicon 6.
It is maintained in a molten state at temperatures around 1400°C. The molten polycrystalline silicon 6 is formed into suitably controlled droplets 10 via a vibrator 9 and is flowed onto the monocrystalline silicon wafer 1 which is rotating or about to be rotated. The polycrystalline silicon melt that has flowed into the single-crystal silicon wafer j]- is spread to the required thickness and to the same diameter as the single-crystal wafer 1 by the centrifugal force of rotation of the support 2, as shown in FIG. An integral structure of monocrystalline layer 11 and polycrystalline layer 12 is formed. In this case, the thickness of the polycrystalline layer can be controlled from 0.5 microns to 300 microns or less by changing the amount of the drop. According to experiments conducted by the inventor, it has been confirmed that a semiconductor substrate having a polycrystalline layer 12 having a thickness of about 30 cm can be formed in a short time (several tens of seconds) using the method of the present invention.
また、単結晶層１１の結晶破壊回避の観点からは、第３
図に示す如く、溶融多結晶シリコンの流１ノ込みを単結
晶層１１に可及、Ｉ！！！Ｊに近づけて行うことが好ま
しい。なお、実施例では、支持具２を回転させたが、こ
れを回転させないで、いわゆるキャスティング法により
多結晶層１２を設けることも出来、更に前例のスピニン
グ法とこのキャスティング法の両方の場合に於て、溶融
多結晶シリコンの流入は、単結晶層１１の中央部分か或
はそれ以外の部分であるかを問わないし、またウェハ１
が水平に置かれているか或は斜めかを問わない。もっと
も、支持具２は、ウェハ１を収納し得る載置用溝を備え
たものが好ましい。In addition, from the viewpoint of avoiding crystal destruction of the single crystal layer 11, the third
As shown in the figure, one stream of molten polycrystalline silicon is applied to the single crystal layer 11, and I! ! ! It is preferable to do it close to J. In the example, the support 2 was rotated, but it is also possible to provide the polycrystalline layer 12 by a so-called casting method without rotating it. Therefore, it does not matter whether the molten polycrystalline silicon flows into the central portion of the single crystal layer 11 or other portions of the wafer 1.
It does not matter whether it is placed horizontally or diagonally. However, it is preferable that the support 2 is provided with a mounting groove in which the wafer 1 can be accommodated.
更に、溶融多結晶シリコンの流し込みが、実施例の場合
的８００℃或はそれ以上の炉内に於てなされたか、多結
晶層１２を厚く形成する（例えば５００ミクロン以上）
ような場合は、単結晶層１１を加熱せずに、すなわち支
持具２を常温下に置いても行われ得ることを確認してい
る。Additionally, the pouring of the molten polycrystalline silicon was performed in a furnace at 800° C. or higher, as in the case of the embodiment, or the polycrystalline layer 12 was formed to be thick (e.g., 500 microns or more).
In such a case, it has been confirmed that the heating can be carried out without heating the single crystal layer 11, that is, by placing the support 2 at room temperature.
第４図及び第５図は第２図の単結晶層１１、多結晶層１
２の−・体構成体上に能動素子を形成したものを略図化
したものである。なお、これらの図では、ウェハｌを１
８０ ”反転して描いている。第４図は多結晶層１２を
主として基板の厚みを補正するものとして構成し、単結
晶層ｌｌ内の能動素子１３を構成したいわゆる低電圧、
低電流タイプＬＳＩ用基板である。なお１４は絶縁層で
ある。Figures 4 and 5 show the single crystal layer 11 and polycrystalline layer 1 in Figure 2.
2 is a schematic diagram of the active element formed on the body structure of No. 2. Note that in these figures, wafer l is 1
80" is inverted. In FIG. 4, the polycrystalline layer 12 is configured mainly to correct the thickness of the substrate, and the so-called low voltage, which constitutes the active element 13 in the single crystal layer 11, is shown.
This is a low current type LSI board. Note that 14 is an insulating layer.
第５図は単結晶層１１と多結晶層１２の両層を用いて能
動素子１３を構成したもので、特に高電圧、高電流タイ
プで、例えばコレクター１５を多結晶層側に取付けたも
のである。第５図の如き構成に於ては低抵抗より高抵抗
までの抵抗層が得られ、また、薄い基板から厚い基板に
わたる一体構成体が自由に得られる。特に５０ミクロン
以上５０ΩＣ■以上の基板も作成しやすくなる。なお第
４図、第５図に於て単結晶層に能動素子を形成するに際
し、その厚みを一体構成体にした後に更に研磨によって
１００ミクロン〜１２０ミクロン程度にしてから上記素
子を形成したり、或は、研磨された単結晶上に更にエピ
タキシャル層を形成したり、はたまた埋込み層を形成す
ることが出来ることはいう迄もない。このような構成に
すると、多結晶層には、■多結晶層によるゲッタリング
効果に加え、■ドーピングによる酸素等のゲッタリング
効果を附加したり、発熱防止効果を附加したり、■単結
晶層の強化をはかる、といった多結晶層のもつ独自の作
用効果を充分に発揮させることが出来る。すなわち、半
導体単体からＬＳＩに至る高低あらゆる電圧電流に対応
できるものとすることが可能である。FIG. 5 shows an active element 13 constructed using both a single crystal layer 11 and a polycrystalline layer 12, and is particularly of a high voltage, high current type, for example, with a collector 15 attached to the polycrystalline layer side. be. In the configuration shown in FIG. 5, a resistance layer ranging from low resistance to high resistance can be obtained, and an integral structure ranging from a thin substrate to a thick substrate can be obtained freely. In particular, it becomes easier to create a substrate with a diameter of 50 microns or more and 50 ΩC or more. In FIGS. 4 and 5, when forming an active element in a single crystal layer, the thickness of the single crystal layer is reduced to about 100 to 120 microns by polishing after forming an integral structure, and then forming the above-mentioned element. It goes without saying that it is also possible to further form an epitaxial layer or a buried layer on the polished single crystal. With such a configuration, in addition to the gettering effect of the polycrystalline layer, the polycrystalline layer can be added with the gettering effect of oxygen, etc. through doping, the heat generation prevention effect, and the monocrystalline layer. The unique functions and effects of the polycrystalline layer, such as strengthening the structure, can be fully demonstrated. In other words, it is possible to handle voltages and currents of all voltages and currents, from single semiconductors to LSIs.
（発明の効果）
以上説明した如く、本発明に依れば、多結晶層全体に均
一なゲッタリング効果をもたせたいわゆるイントリンシ
ックゲッタ（ＩＧ）作用や、その外部の単結晶層から酸
素を吸収するエクストリンシックゲッタ（ＥＧ）や、基
体裏面に歪層を作るいわゆるバックダメイジによるゲッ
タリング効果をも併用可能な多結晶層基板が得られるこ
とになる。しかもその製法は単結晶層の厚さを従来のも
のより半分以下にすることが出来るので、単結晶ウェハ
を単結晶ロットから、より多く切り出せることと相まっ
て、この点からも低コスト製品の実現が可能となる。(Effects of the Invention) As explained above, according to the present invention, the so-called intrinsic getter (IG) effect that gives a uniform gettering effect to the entire polycrystalline layer, and the absorption of oxygen from the single crystal layer outside the polycrystalline layer, can be achieved. A polycrystalline layer substrate can be obtained that can also be used with the gettering effect of extrinsic getter (EG), which creates a strained layer on the back surface of the substrate, and so-called back damage. Moreover, this manufacturing method allows the thickness of the single crystal layer to be less than half that of conventional methods, making it possible to cut out more single crystal wafers from a single crystal lot, which also makes it possible to achieve low-cost products. becomes possible.
第１図及び第３図は本発明の概要を示す構成図、第２図
は半導体基板の概略側断面図、第４図は基板の片面を用
いる半導体側断面図、第５図は基板の両面を用いる半導
体側断面図である。
１・・・ウェハ ２・・・支持具６・・・多
結晶シリコン １１・・・単結晶層１２・・・多結晶
層
特許出願人 大阪チタニウム製造株式会社特許出願人
九州電子金属株式会社
代 理 人 弁理士 森 正 澄第１図
１・・・ウェハ ２・・・支持具６・・・多
結晶シリコン １１・・・中結晶層１２・・・多結晶
層
第２図
第４図
第５図1 and 3 are configuration diagrams showing the outline of the present invention, FIG. 2 is a schematic side sectional view of a semiconductor substrate, FIG. 4 is a side sectional view of a semiconductor using one side of the substrate, and FIG. 5 is a side sectional view of a semiconductor using both sides of the substrate. FIG. 1... Wafer 2... Support 6... Polycrystalline silicon 11... Single crystal layer 12... Polycrystalline layer Patent applicant Osaka Titanium Manufacturing Co., Ltd. Patent applicant Kyushu Electronic Metals Co., Ltd. Agent Person Patent Attorney Tadashi Mori Figure 1 1... Wafer 2... Support 6... Polycrystalline silicon 11... Medium crystal layer 12... Polycrystalline layer Figure 2 Figure 4 Figure 5
Claims (5)
層の一面に半導体多結晶層とを設け、該多結晶層の厚さ
を１０ミクロン以上としてなる多結晶層を有する半導体
基板。(1) A polycrystalline layer comprising a P-type, N-type, or I-type semiconductor single crystal layer and a semiconductor polycrystalline layer on one surface of the single-crystalline layer, and the thickness of the polycrystalline layer is 10 microns or more. A semiconductor substrate with
層の一面に半導体多結晶層とを設け、該多結晶層の厚さ
を１０ミクロン以上としてなる半導体基板であって、多
結晶層は回転板上に設置された単結晶層上に滴下される
ことにより構成されてなる多結晶層を有する半導体基板
。(2) A semiconductor substrate comprising a P-type, N-type, or I-type semiconductor single-crystal layer and a semiconductor polycrystalline layer on one surface of the single-crystalline layer, and the thickness of the polycrystalline layer is 10 microns or more. A semiconductor substrate having a polycrystalline layer formed by dropping the polycrystalline layer onto a single-crystalline layer placed on a rotating plate.
層の一面に半導体多結晶層とを設け、該多結晶層の厚さ
を１０ミクロン以上としてなる半導体基板であって、多
結晶層にはイントリンシックゲッタ或はエクストリンシ
ックゲッタ材をドープしてなる多結晶層を有する半導体
基板。(3) A semiconductor substrate comprising a P-type, N-type, or I-type semiconductor single-crystal layer and a semiconductor polycrystalline layer on one surface of the single-crystalline layer, the thickness of the polycrystalline layer being 10 microns or more. A semiconductor substrate having a polycrystalline layer in which the polycrystalline layer is doped with an intrinsic getter or an extrinsic getter material.
層の一面に半導体多結晶層とを設け、該多結晶層の厚さ
を１０ミクロン以上としてなる半導体基板であって、多
結晶層の単結晶層との接合面と反対の面に電極を取付け
てなる多結晶層を有する半導体基板。(4) A semiconductor substrate comprising a P-type, N-type, or I-type semiconductor single-crystal layer and a semiconductor polycrystalline layer on one surface of the single-crystalline layer, the thickness of the polycrystalline layer being 10 microns or more. A semiconductor substrate having a polycrystalline layer with an electrode attached to a surface opposite to a bonding surface of the polycrystalline layer with a single crystal layer.
層の一面に半導体多結晶層とを設け、該多結晶層の厚さ
を１０ミクロン以上としてなる半導体基板であって、単
結晶層にのみ能動素子を設けてなる多結晶層を有する半
導体基板。(5) A semiconductor substrate comprising a P-type, N-type, or I-type semiconductor single-crystal layer and a semiconductor polycrystalline layer on one surface of the single-crystalline layer, the thickness of the polycrystalline layer being 10 microns or more. A semiconductor substrate having a polycrystalline layer in which active elements are provided only in a single crystalline layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5616087A JPS63222435A (en) | 1987-03-11 | 1987-03-11 | Semiconductor substrate having polycrystalline layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5616087A JPS63222435A (en) | 1987-03-11 | 1987-03-11 | Semiconductor substrate having polycrystalline layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63222435A true JPS63222435A (en) | 1988-09-16 |
Family
ID=13019342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5616087A Pending JPS63222435A (en) | 1987-03-11 | 1987-03-11 | Semiconductor substrate having polycrystalline layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63222435A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03235333A (en) * | 1990-02-13 | 1991-10-21 | Mitsubishi Electric Corp | Semiconductor substrate having improved getter effect, semiconductor device using the substrate and manufacture thereof |
| US5189508A (en) * | 1988-03-30 | 1993-02-23 | Nippon Steel Corporation | Silicon wafer excelling in gettering ability and method for production thereof |
-
1987
- 1987-03-11 JP JP5616087A patent/JPS63222435A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5189508A (en) * | 1988-03-30 | 1993-02-23 | Nippon Steel Corporation | Silicon wafer excelling in gettering ability and method for production thereof |
| JPH03235333A (en) * | 1990-02-13 | 1991-10-21 | Mitsubishi Electric Corp | Semiconductor substrate having improved getter effect, semiconductor device using the substrate and manufacture thereof |
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