JPS63215988A - Mounting structure of ic chip for timepiece - Google Patents
Mounting structure of ic chip for timepieceInfo
- Publication number
- JPS63215988A JPS63215988A JP5058487A JP5058487A JPS63215988A JP S63215988 A JPS63215988 A JP S63215988A JP 5058487 A JP5058487 A JP 5058487A JP 5058487 A JP5058487 A JP 5058487A JP S63215988 A JPS63215988 A JP S63215988A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- circuit board
- printed circuit
- terminals
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 abstract description 15
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 10
- 239000010931 gold Substances 0.000 abstract description 8
- 229910052737 gold Inorganic materials 0.000 abstract description 8
- 229920003002 synthetic resin Polymers 0.000 abstract description 4
- 239000000057 synthetic resin Substances 0.000 abstract description 4
- 230000007547 defect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000013078 crystal Substances 0.000 description 3
- 238000000465 moulding Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Landscapes
- Electromechanical Clocks (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ＩＣチップの実装構造に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to an IC chip mounting structure.
ＩＣチップの実装構造として、特開昭５９−１５８３４
１ 、特開昭５６−５０５４４．特開昭５９−１２０８
８４が考案されている。これらは、配線パターンとＩＣ
チップの端子を金線、溶着。As an IC chip mounting structure, Japanese Patent Application Laid-Open No. 59-15834
1, JP-A-56-50544. Japanese Patent Publication No. 59-1208
84 have been devised. These are the wiring pattern and IC
Weld the chip terminals with gold wire.
半田付は等で接続し、更に接続部分を補強するためにモ
ールド剤で固着したものである。The connection is made by soldering, etc., and then fixed with a molding agent to strengthen the connection part.
しかし、従来の実装方式では配線パターンとＩＣチップ
の端子を金線、溶着、半田付けで接続する工程やモール
ドを行なう工程であるＩＣチップの実装工程を要した。However, the conventional mounting method requires an IC chip mounting process that includes a process of connecting the wiring pattern and the terminals of the IC chip using gold wire, welding, or soldering, and a process of molding.
又、この実装工程の不良については修正が不可能であっ
た。しかも、ＩＣチップや回路基板は他の時計部品と比
較しても高価なものであり、実装工程の歩留シは回路ブ
ロックのコストを左右することは周知である。Furthermore, it was impossible to correct defects in this mounting process. Furthermore, it is well known that IC chips and circuit boards are expensive compared to other watch components, and the yield of the mounting process influences the cost of the circuit block.
そこで本発明の目的とするところは、実装工程を簡素化
しコストの低減を図るとともに、実装工程の不良につい
ても簡単に修正できる実装構造を得ることにある。SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a mounting structure that simplifies the mounting process, reduces costs, and allows for easy correction of defects in the mounting process.
本発明のＩＣチップの実装構造は、
複数の端子を有するＩＣチップ、該ＩＣチップの端子に
対向した配線パターンを設けた絶縁部材、該端子と配線
パターンの平面位置を決めるための度決め部、該端子と
配線パターンとを導通可能に圧接する部材から成り、Ｉ
Ｃチップ又は配線パターンの少なくとも一方に突起部を
構成したことを特徴とする。The IC chip mounting structure of the present invention includes an IC chip having a plurality of terminals, an insulating member provided with a wiring pattern facing the terminals of the IC chip, a measuring part for determining the planar position of the terminals and the wiring pattern, It consists of a member that presses the terminal and the wiring pattern in electrically conductive contact, and
A feature is that a protrusion is formed on at least one of the C chip or the wiring pattern.
第１図は本発明の実施例を示す平面図、第２図、第３図
はその断面図である。FIG. 1 is a plan view showing an embodiment of the present invention, and FIGS. 2 and 3 are sectional views thereof.
１は合成樹脂で成形した地板である。２は地板１に載誼
し、地板１に対向する配線パターンを形成した回路基板
である。３は弾性を有する回路受である。４は金バンプ
で形成したステップモータ用出力端子、リセット端子、
水晶ユニット用端子、ＶＤＤ 、７８ｇ端子、テスト用
端子、書き込み用端子を有したＭＯ３ＩＣチップである
。５は水晶ユニット、６はロータ、ステータ、コイルブ
ロックから構成した周知のステップモータのコイルブロ
ックである。７は電池、８は電池７の陰極に圧接してい
る電池マイナス端子である１回路基板２には、前記各端
子に対向するステップモータ用出力端子０１ 、Ｏｔパ
ターン２α、２ｂ、ゲート。1 is a base plate molded from synthetic resin. 2 is a circuit board mounted on the base plate 1 and having a wiring pattern facing the base plate 1 formed thereon. 3 is an elastic circuit holder. 4 is a step motor output terminal formed of gold bumps, a reset terminal,
It is an MO3IC chip that has a crystal unit terminal, VDD, 78g terminal, test terminal, and write terminal. Reference numeral 5 indicates a crystal unit, and 6 indicates a coil block of a well-known step motor, which is composed of a rotor, a stator, and a coil block. 7 is a battery, and 8 is a battery negative terminal which is pressed into contact with the cathode of the battery 7.1 The circuit board 2 has an output terminal 01 for a step motor facing each terminal, Ot patterns 2α, 2b, and a gate.
）’Ｌ／イ：／ハ！ｌ−７２ Ｃ、２ｄ 、 ＶＤＤ
−ｐずターン２ｇ、’７８８ パターン２ｆ、リセ
ットパターン２ｙ、テスト端子２Ａ、２ｚｅ書き込み用
端子２ｊを形成（表面には金メッキを実施）しである、
又、これらのパターンの一部はＩＣチップの度決め穴２
によりオーバーハングさせである。更にＩＣチップの度
決め穴２には、ＩＣチップ４の四角をにげて四方向の側
面を平面的に位置決めし、パターンと工Ｏチ゛クプの端
子の平面的なずれを防止している０次にＩＣチップの断
面的な位置決めは、回路受３に設けたばね３αによって
押圧されている、しかも、地板１自身合成樹脂で成形し
であるためバンプ高さんのバラツキを吸収するだけのわ
ずかな可撓性を有している（想像線に示すように地板１
に凹部を形成すればより可撓性を増し導通の信頼性を°
増す）。従って、実装工程としては、回路基板の度決め
穴２ｋにＩＣチップ４を放り込み、回路受３を組み立て
ることで実装できるため非常に簡単になっている。又、
実装上での不良は熱圧着やワイヤーボンドをしないため
皆無となる。)'L/I:/Ha! l-72C, 2d, VDD
-p Z turn 2g, '788 pattern 2f, reset pattern 2y, test terminal 2A, 2ze write terminal 2j formed (gold plated on the surface),
Also, some of these patterns are used for measuring hole 2 of the IC chip.
This causes an overhang. Furthermore, in the alignment hole 2 of the IC chip, the four sides of the IC chip 4 are positioned planarly by removing the square, and the zero-order hole 2 prevents the planar misalignment of the pattern and the terminal of the O-chip. The cross-sectional positioning of the IC chip is pressed by a spring 3α provided on the circuit holder 3, and since the base plate 1 itself is molded from synthetic resin, it has a slight flexibility that is sufficient to absorb variations in bump height. (as shown in the imaginary line, the main plate 1
By forming a concave part, it increases flexibility and reliability of conduction.
increase). Therefore, the mounting process is very simple because it can be mounted by throwing the IC chip 4 into the alignment hole 2k of the circuit board and assembling the circuit receiver 3. or,
There are no defects during mounting because there is no thermocompression bonding or wire bonding.
万が一不良が出ても回路受５を外すことでＩＣチップ４
の交換あるいは回路基板２の交換をすれば良いため、修
理性も向上する。又、水晶ユニット５は平面的な位置を
地板の凹部１ｂでガイドし、端子を地板１と回路基板２
を介して回路受３０弾性部３ｂで押圧し導通なとってい
る。Even if a defect occurs, the IC chip 4 can be removed by removing the circuit receiver 5.
Since it is only necessary to replace the circuit board 2 or the circuit board 2, repairability is also improved. In addition, the crystal unit 5 is guided in its planar position by the concave portion 1b of the main plate, and the terminals are connected between the main plate 1 and the circuit board 2.
The circuit receiver 30 is pressed by the elastic portion 3b through the circuit holder 30 to establish conduction.
次に、第４図〜第９図は本発明の他の実施例である。先
ず第４図において、地板１には各バンプと略同位置に凹
部１αを設けである。これは、金バンプのバンプ高さん
に各々バラツキがあるため、この高さのバラツキを吸収
できるようにパターンの一部が若干たわまさられるべく
設定しである（地板凹部１αとパターンのスキマ！とバ
ンプ高さｈはＡ ） ｚの設定が好ましく、ＩＣチップ
４と地板サライ１−のスキマｔはｔ＞ｓが好ましい）、
これによりてよりパターンとバンプの導通の信頼性を向
上できる。又、ＩＣチップ４は回路受３に凸部５ｈを設
け、回路受３の全体の弾性で押圧した構造である。更に
回路基板２よりＩＣチップ４は突出させであるが、チッ
ピングの時にＩＣチップの端面に突起４αが残ることが
あり、それが平面的にパターンとバンプのずれを生じさ
せるのでそれを防止するためである。Next, FIGS. 4 to 9 show other embodiments of the present invention. First, in FIG. 4, the base plate 1 is provided with a recess 1α at approximately the same position as each bump. This is because the bump heights of the gold bumps vary, so in order to absorb this variation in height, a part of the pattern is set to be slightly warped (there is a gap between the base plate recess 1α and the pattern! The bump height h is preferably set to A), and the clearance t between the IC chip 4 and the ground plate 1- is preferably set to t>s),
This makes it possible to further improve the reliability of conduction between the pattern and the bump. Further, the IC chip 4 has a structure in which a convex portion 5h is provided on the circuit receiver 3 and is pressed by the elasticity of the entire circuit receiver 3. Furthermore, although the IC chip 4 is made to protrude from the circuit board 2, protrusions 4α may remain on the end face of the IC chip during chipping, which causes a two-dimensional misalignment between the pattern and the bumps. It is.
次に第５図において、回路基板２に形成した各パターン
の先端に曲げ部２１を設け、バンプ高さのバラツキを吸
収する方法を示したものである。Next, FIG. 5 shows a method of providing a bent portion 21 at the tip of each pattern formed on the circuit board 2 to absorb variations in bump height.
第６図は、ＩＣチップ４に金バンプを設けない場合の構
造を示したもので、パターンの先端（ＩＣチップの各端
子に対向した位置）にダボ２ｍを設けたものである。更
にダボ出し以外にも、パターン一部にハーフエツチング
による突起２３を形成（第９図）しても同じ効果がある
。FIG. 6 shows a structure in which no gold bumps are provided on the IC chip 4, in which dowels 2 m are provided at the tips of the patterns (positions facing each terminal of the IC chip). Furthermore, in addition to doweling, the same effect can be obtained by forming protrusions 23 on a part of the pattern by half etching (FIG. 9).
第７図は、Ｘａチップの平面的な位置決めを地板１の複
数の突起部１ｄで行なったもので、ＩＣチップ４の端子
とパターンの接続方法は前述の方法とで組合わせて行っ
たものである。又、地板１０代りに合成樹脂で成形した
回路受座を用いてもよい。In FIG. 7, the planar positioning of the Xa chip is performed using a plurality of protrusions 1d on the base plate 1, and the method for connecting the terminals of the IC chip 4 and the pattern is performed in combination with the method described above. be. Further, a circuit seat molded from synthetic resin may be used instead of the base plate 10.
第８図は、回路基板のパターンを他の実施例とは逆の方
向に形成した方法であり、電気的にＶＤＤと同電位又は
電気的に浮かせたパターン２ｑによってＩＣチップ４の
平面的な位置決めを行なりた構造である。穴２ｒはパタ
ーン２９を曲げる穴である。又、想像線で示すようにＩ
Ｃチップ４の平面ガイドに絶縁性を有する回路基板２の
一部（複数個所の半抜き等）に突出部で行なっても良い
。FIG. 8 shows a method in which the circuit board pattern is formed in the opposite direction to that of the other embodiments, and the two-dimensional positioning of the IC chip 4 is performed using a pattern 2q that is electrically at the same potential as VDD or electrically floating. This is the structure in which this was done. The hole 2r is a hole for bending the pattern 29. Also, as shown by the imaginary line, I
The planar guide of the C-chip 4 may be formed by a protrusion on a part of the insulating circuit board 2 (eg, a plurality of half-cuts).
更に、実施例の金バンブで説明した部分においては半田
バンプでも同じ効果が得られ、回路基板のパターンには
金メッキを行なうことで導通の信頼性向上させることを
付は加えておく。Furthermore, it should be added that the same effect can be obtained with solder bumps in the parts explained using the gold bumps in the embodiment, and the reliability of conduction can be improved by gold plating the circuit board pattern.
以上のように、回路基板、地仮にＩＣチップとパターン
の平面的な位置決めをし、回路受でＩＣチップを押圧す
ることによって、ＩＣチップの実装において基板とチッ
プを固着させない実装構造にしたことで、実装工数の削
減ができるとともに、実装工程、或はＩＣチップや回路
基板の不良があっても回路受を外すことによって容易に
取シかえることができる等の優れた効果を有するもので
ある。更にＩＣチップのパンプヤ配線パターンのＩＣ端
子の接触部に設けた突起は、多数の端子と配線パターン
の接続を容易にするとともに、接触部の接点圧を高めら
れることから導通のけ傾注を高められる効果も生む。As described above, by positioning the IC chip and the pattern on the circuit board and the ground plane, and pressing the IC chip with the circuit support, we have created a mounting structure that does not allow the board and chip to stick together when mounting the IC chip. This has excellent effects such as reducing the number of mounting steps, and even if there is a defect in the mounting process or in the IC chip or circuit board, it can be easily replaced by removing the circuit receiver. Furthermore, the protrusions provided at the contact parts of the IC terminals of the IC chip's pump wiring pattern facilitate the connection of multiple terminals and the wiring pattern, and increase the contact pressure at the contact parts, thereby increasing the degree of conduction. It also produces effects.
第１図は、本発明の実施例における平面図、第２図、第
３図はその断面図である。第４図〜第９図は、本発明の
他の実施例における断面図である１・・・・・・・・・
地 板
２・・・・・・・・・回路基板
３・・・・・・・・・回路受
４・・・・・・・・・ＩＣチップ
以 上FIG. 1 is a plan view of an embodiment of the present invention, and FIGS. 2 and 3 are sectional views thereof. 4 to 9 are cross-sectional views of other embodiments of the present invention 1...
Ground plate 2...Circuit board 3...Circuit receiver 4...IC chip or more
Claims (1)
対向した配線パターンを設けた絶縁部材、前記端子と配
線パターンの平面位置を決めるための度決め部を有した
絶縁部材もしくは機枠、該端子と配線パターンとを導通
可能に圧接する部材から成り、ＩＣチップ又は配線パタ
ーンの少なくとも一方に突起部を構成したことを特徴と
する時計用ＩＣチップの実装構造。An IC chip having a plurality of terminals, an insulating member provided with a wiring pattern facing the terminals of the IC chip, an insulating member or machine frame having a measuring part for determining the planar position of the terminals and the wiring pattern, and the terminal. 1. A mounting structure for an IC chip for a watch, comprising a member that presses and connects a wiring pattern and a wiring pattern in a conductive manner, and comprising a protrusion on at least one of the IC chip or the wiring pattern.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5058487A JPS63215988A (en) | 1987-03-05 | 1987-03-05 | Mounting structure of ic chip for timepiece |
| GB8804409A GB2203270B (en) | 1987-03-05 | 1988-02-25 | Timepiece assembly. |
| US07/164,299 US5008868A (en) | 1987-03-05 | 1988-03-04 | Structure for mounting an integrated circuit |
| CH848/88A CH678256B5 (en) | 1987-03-05 | 1988-03-07 | |
| SG41694A SG41694G (en) | 1987-03-05 | 1994-03-22 | Timepiece assembly |
| HK40894A HK40894A (en) | 1987-03-05 | 1994-04-28 | Timepiece assembly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5058487A JPS63215988A (en) | 1987-03-05 | 1987-03-05 | Mounting structure of ic chip for timepiece |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63215988A true JPS63215988A (en) | 1988-09-08 |
Family
ID=12863025
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5058487A Pending JPS63215988A (en) | 1987-03-05 | 1987-03-05 | Mounting structure of ic chip for timepiece |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63215988A (en) |
-
1987
- 1987-03-05 JP JP5058487A patent/JPS63215988A/en active Pending
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