JPS63215210A - Pulse generator - Google Patents

Abstract

PURPOSE:To easily obtain a pulse with simple circuit constitution by constituting the titled circuit by a switch whose three contacts cannot be short-circuited at the same time, a capacitor, a charging resistor and a discharging resistor for the said capacitor and obtaining a pulse output across the charging resistor. CONSTITUTION:With a switch 2 turned on, that is, when a moving contact is thrown from a contact 2c to a contact 2a, a current flows from a capacitor 3 and a 2nd resistor 5 to other pole of a DC power supply from a DC power supply 1 via the contacts 2a, 2b and is charged in the capacitor 3, then a waveform of a point B shown in figure (b) is outputted across the 2nd resistor 5. With the switch 2 turned off, that is, when the moving contact is thrown from the contact 2a to the contact 2c, the electric charge stored in the capacitor 3 flows to a 1st resistor 4 via the contacts 2b, 2c and is discharged. Thus, one pulse is generated across the 2nd resistor 5 by turn-on/off of the switch 2. In this case, in selecting the capacitance of the capacitor 3 and the resistance of the 1st resistor 4 and the 2nd resistor 5 properly, an optional pulse width is obtained.

Description

【発明の詳細な説明】 産業上の利用分野 カーペット、毛布等の暖房器具の制御回路をはじめとす
るあらゆる制御回路に使用するパルス発生回路に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse generating circuit used in all kinds of control circuits, including control circuits for heating appliances such as carpets and blankets.

従来の技術 従来のパルス発生回路は一般的に第３図に示す如くＤ型
フリフプフロップ（以後Ｄ−ＦＦと記述する）１１を２
個、スイッチ１ｏ、インバータ１２、アンドゲート１を
各１個とクロック発振器を要していた。動作としては第
４図へ）　、　＠　、　（Ｃ１に示す如く入力信号ＩＮ
とクロック信号ＣＫをＤ−ＦＦに入力すると出力信号Ｏ
ＵＴが１つのパルスとして出力される。2. Description of the Related Art A conventional pulse generation circuit generally has two D-type flip-flops (hereinafter referred to as D-FF) 11 as shown in FIG.
1, one switch 1o, one inverter 12, one AND gate 1, and a clock oscillator. For the operation, see Figure 4), @, (as shown in C1, the input signal IN
and clock signal CK are input to D-FF, output signal O
UT is output as one pulse.

発明が解決しようとする問題点 このような従来回路では、回路構成が複雑なうえ、高価
なものとなる。又、パルス幅を変更しようとすればクロ
ック信号ＣＫの発振周波数を変更する方法があるがクロ
ック信号ＯＫは他の回路の周期信号となっている事が一
般的でありクロック信号ＣＫの周期を変更する事が困難
である。又、パルス幅を変更する場合の他の方法として
第４図の出力信号○ＵＴの２倍或は３倍というようにし
ようとすればＤ−ＦＦが更に１段或は２段必要となり更
に複雑になり、任意のパルス幅がとれないと云う欠点が
ある。Problems to be Solved by the Invention Such conventional circuits have a complex circuit configuration and are expensive. Also, if you want to change the pulse width, there is a way to change the oscillation frequency of the clock signal CK, but the clock signal OK is generally a periodic signal of another circuit, so it is necessary to change the period of the clock signal CK. It is difficult to do. Also, if you try to change the pulse width by two or three times the output signal ○UT shown in Figure 4, one or two stages of D-FF will be required, making it even more complicated. The disadvantage is that an arbitrary pulse width cannot be obtained.

問題点を解決するだめの手段 本発明は上記問題点を解決するため、同時に３接点が短
絡することのないスイッチと、コンデンサと、このコン
デンサの充電用抵抗器と放電用抵抗器により構成し、充
電用抵抗器の両端から１つのパルス出力を得るものであ
る。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention consists of a switch whose three contacts do not short-circuit at the same time, a capacitor, and a charging resistor and a discharging resistor for this capacitor. One pulse output is obtained from both ends of the charging resistor.

作　　用 本発明は上記した構成により、任意のパルス幅の１つの
パルスが非常に簡単な構成で得られる。Function The present invention can obtain one pulse of any pulse width with a very simple configuration using the above-described configuration.

実施例 第１図は本発明のパルス発生回路の一実施例を示す回路
図である。第２図は同時に３接点が短絡することのない
スイッチ２がＯＮした時とＯＦＦした時の各部の波形で
ある。Embodiment FIG. 1 is a circuit diagram showing an embodiment of the pulse generating circuit of the present invention. FIG. 2 shows the waveforms of various parts when the switch 2 is turned on and turned off, in which the three contacts are not short-circuited at the same time.

第１図に於いてスイッチ２がＯＮした時、即ち可動接片
が接点２Ｃから接点２ａに切換わった時直流電源１から
前記接点２ａ　、２ｂを経てコンデンサ３、第２の抵抗
器６から直流電源の異極へと電流が流れて前記コンデン
サ３に充電される間、前記第２の抵抗器６の両端に第２
図のａ３）、の８点の波形が出力される。この時、直流
電源１のマイナス側とＡ点間では第２図の式のＡ点の波
形が出力される。In FIG. 1, when the switch 2 is turned on, that is, when the movable contact piece is switched from the contact 2C to the contact 2a, the DC power supply 1 passes through the contacts 2a and 2b to the capacitor 3 and the second resistor 6. While the current flows to different polarities of the power supply and charges the capacitor 3, a second resistor 6 is connected to both ends of the second resistor 6.
Waveforms at eight points a3) in the figure are output. At this time, the waveform at point A in the equation of FIG. 2 is output between the negative side of DC power supply 1 and point A.

スイッチ２が０ＦＦＩ、た時、即ち可動接片が接点２ａ
から接点２Ｃに切換った時、コンデンサ３に蓄えられた
電荷が接点２ｂ、２ａを経て第１の抵抗器４に流れて放
電される。When switch 2 is 0FFI, that is, the movable contact piece is at contact 2a.
When switching from to contact 2C, the charge stored in capacitor 3 flows to first resistor 4 via contacts 2b and 2a and is discharged.

このようにしてスイッチ２のＯＮ、ＯＦＦにより１つの
パルスが第２の抵抗器６の両端に発生する。In this way, one pulse is generated across the second resistor 6 by turning the switch 2 ON and OFF.

コンデンサ３の容量と第１の抵抗器４、第２の抵抗器５
を適切に選ぶことにより任意のパルス幅が得られる。ま
た、スイッチ２のＯＮ、ＯＦＦを繰返しても第１の抵抗
器が充分に小さければ、例えば１００Ω程度であれば実
用上何ら支障なく繰返し１つのパルスが発生する。Capacity of capacitor 3, first resistor 4, second resistor 5
An arbitrary pulse width can be obtained by appropriately selecting . Further, even if the switch 2 is repeatedly turned ON and OFF, if the first resistor is sufficiently small, for example, about 100Ω, one pulse can be repeatedly generated without any practical problem.

発明の効果 以上述べてきたように、本発明によれば、きわめて簡易
な回路構成で、任意のパルス副の１つのパルスが得られ
実用的にきわめて有用である。Effects of the Invention As described above, according to the present invention, one pulse of an arbitrary pulse sub-pulse can be obtained with an extremely simple circuit configuration, and is extremely useful in practice.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例におけるパルス発生回路の回
路図、第２図は第１図の各部の波形図、第３図は従来の
パルス発生回路の回路図、第４図は第３図の各部の波形
図である。 １・・・・・・直流電源、２・・・・・・スイッチ、２
ａ、２ｂ。 ２Ｃ・・・・・・接点、３・・・・・・コンデンサ、４
・・・・・・第１の抵抗器、６・・・・・・第２の抵抗
器。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名そ　
　　あ 派　　　　　　　　　派　−− ０ウ　　　　　　　　　　　　　　　　　　　　　　　
　　　ｒｌ　　　　＾、＜　　”）　　　。 派 慟FIG. 1 is a circuit diagram of a pulse generation circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram of each part of FIG. 1, FIG. 3 is a circuit diagram of a conventional pulse generation circuit, and FIG. It is a waveform chart of each part of a figure. 1...DC power supply, 2...Switch, 2
a, 2b. 2C...Contact, 3...Capacitor, 4
...First resistor, 6...Second resistor. Name of agent: Patent attorney Toshio Nakao and one other person
A faction -- 0u
rl ^, < ”).

Claims (1)

【特許請求の範囲】[Claims] 同時に３接点が短絡することのないスイッチの中央接点
にコンデンサを接続し、前記スイッチの一方の側接点に
第１の抵抗器を接続し、前記コンデンサと前記第１の抵
抗器の接続点に第２の抵抗器の一端を接続し、前記第２
の抵抗器の他端を直流電源の一方に接続し、直流電源の
異極側に前記スイッチの他方の側端子を接続し、前記第
２の抵抗器両端から１つのパルスを出力する構成とした
ことを特徴とするパルス発生回路。A capacitor is connected to the center contact of a switch in which three contacts are not short-circuited at the same time, a first resistor is connected to one side contact of the switch, and a second resistor is connected to the connection point between the capacitor and the first resistor. Connect one end of the second resistor to the second resistor.
The other end of the resistor is connected to one side of a DC power source, the other side terminal of the switch is connected to a different polarity side of the DC power source, and one pulse is output from both ends of the second resistor. A pulse generation circuit characterized by: